524
11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
27.2.16.24
PMC Peripheral Clock Disable Register 1
Name:
PMC_PCDR1
Address:
0x400E0504
Access:
Write-only
This register can only be written if the WPEN bit is cleared in
“PMC Write Protect Mode Register” on page 521
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note:
To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
–
–
–
–
PID34
PID33
PID32
Summary of Contents for SAM4S Series
Page 44: ...44 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...
Page 412: ...412 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...
Page 1105: ...1105 11100B ATARM 31 Jul 12 SAM4S Series Preliminary ...
Page 1143: ...1143 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 4 64 lead LQFP Package Drawing ...
Page 1145: ...1145 11100B ATARM 31 Jul 12 SAM4S Series Preliminary Figure 43 5 64 lead QFN Package Drawing ...