Atmel AVR XMEGA D Series, Manual, Page: 264 / 331

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8210C–AVR–09/11
Atmel AVR XMEGA D
21.15 Register Description - ADC Channel
21.15.1 CTRL – Control Register
• Bit 7 – START: START Conversion on Channel
Setting this bit will start a conversion on the channel. The bit is cleared by hardware when the
conversion has started. Setting this bit when it already is set will have no effect. Writing or read-
ing this bit is equivalent to writing the CH[3:0]START bits in
”CTRLA – Control register A” on
page 257 .
• Bit 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:2 – GAIN[2:0]: Gain Factor
These bits define the gain factor for the ADC gain stage.
See Table 21-5 on page 260 . Gain is valid only with certain MUX settings. See ”MUXCTRL –
MUX Control registers” on page 265 .
• Bit 1:0 – INPUTMODE[1:0]: Channel Input Mode
These bits define the channel mode. Changing input mode will corrupt any data in the pipeline.
Bit 7 6 5 4 3 2 1 0
+0x00 START – – GAIN[2:0] INPUTMODE[1:0] CTRL
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 21-7. ADC gain factor.
GAIN[2:0] Group Configuration Gain Factor
000 1X 1x
001 2X 2x
010 4X 4x
011 8X 8x
100 16X 16x
101 32X 32x
110 64X 64x
111 DIV2 ½x
Table 21-8. Channel input modes, CONVMODE=0 (unsigned mode).
INPUTMODE[1:0] Group Configuration Description
00 INTERNAL Internal positive input signal
01 SINGLEENDED Single-ended positive input signal
10 Reserved
11 Reserved