Atmel AVR XMEGA D Series, Manual, Page: 136 / 331

136
8210C–AVR–09/11
Atmel AVR XMEGA D
12.3 Block Diagram
Figure 12-2 on page 136 shows a detailed block diagram of the timer/counter without the
extensions.
Figure 12-2. Timer/counter block diagram.
The counter register (CNT), period registers with buffer (PER and PERBUF), and compare and
capture registers with buffers (CCx and CCxBUF) are 16-bit registers. All buffer register have a
buffer valid (BV) flag that indicates when the buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period
(PER) value to determine whether the counter has reached TOP or BOTTOM.
The counter value is also compared to the CCx registers. These comparisons can be used to
generate interrupt requests, generate events for the event system. The waveform generator
modes use these comparisons to set the waveform period or pulse width.
A prescaled peripheral clock and events from the event system can be used to control the coun-
ter. The event system is also used as a source to the input capture. Combined with the
quadrature decoding functionality in the event system (QDEC), the timer/counter can be used
for quadrature decoding.
Base Counter
Compare/Capture
(Unit x = {A,B,C,D})
Counter
=
Waveform
Generation
BV
=
BV
= 0
"count"
"clear"
"direction"
"load"
Control Logic
OVF/UNF
(INT Req.)
ERRIF
(INT Req.)
TOP
"match" CCxIF
(INT Req.)
Control Logic
Clock Select
"ev" UPDA
TE
BOTTOM
OCx Out
Event
Select
CCx
CCBUFx
PERBUF
PER
CNT
CTRLD
CTRLA