377
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 3:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
28.16.12 CMPH – Compare Register High
The CMPH and CMPL register pair represents the 16-bit value, CMP. For details on reading and
writing 16-bit registers, refer to
”Accessing 16-bit Registers” on page 13
• Bit 7:0 – CMP[15:0]: Compare Value High
These are the eight msbs of the 16-bit ADC compare value. In signed mode, the number repre-
sentation is 2's complement, and the msb is the sign bit.
28.16.13 CMPL – Compare Register Low
• Bit 7:0 – CMP[7:0]: Compare Value Low
These are the eight lsbs of the 16-bit ADC compare value. In signed mode, the number repre-
sentation is 2's complement.
28.17 Register Description - ADC Channel
28.17.1
CTRL – Channel Control Register
• Bit 7 – START: START Conversion on Channel
Setting this bit will start a conversion on the channel. The bit is cleared by hardware when the
conversion has started. Setting this bit when it already is set will have no effect. Writing or read-
ing this bit is equivalent to writing the CH[3:0]START bits in
”CTRLA – Control register A” on
.
• Bit 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4:2 – GAIN[2:0]: Gain Factor
These bits define the gain factor for the ADC gain stage.
Bit
7
6
5
4
3
2
1
0
CMP[15:0]
CMPH
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CMP[7:0]
CMPL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
START
–
–
GAIN[2:0]
INPUTMODE[1:0]
CTRL
Read/Write
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
