ATtiny15L
21
External Interrupt
The external interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is
configured as an output. This feature provides a way of generating a software interrupt. The external interrupt can be trig-
gered by a falling or rising edge, a pin change, or a low-level. This is set up as indicated in the specification for the MCU
Control Register – MCUCR. When the external interrupt is enabled and is configured as level-triggered, the interrupt will
trigger as long as the pin is held low.
The external interrupt is set up as described in the specification for the MCU Control Register – MCUCR.
Pin Change Interrupt
The pin change interrupt is triggered by any change in logical value on any input or I/O pin. Change on pins PB4..0 will
always cause an interrupt. Change on pin PB5 will cause an interrupt if the pin is configured as input or I/O, as described in
the section “Pin Descriptions” on page 4. Observe that, if enabled, the interrupt will trigger even if the changing pin is con-
figured as an output. This feature provides a way of generating a software interrupt. Also observe that the pin change
interrupt will trigger even if the pin activity triggers another interrupt, for example the external interrupt. This implies that one
external event might cause several interrupts. The values on the pins are sampled before detecting edges. If pin change
interrupt is enabled, pulses that last longer than one CPU clock period will generate an interrupt. Shorter pulses are not
guaranteed to generate an interrupt.
The MCU Control Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
•
Bits 7 - Res: Reserved bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
•
Bit 6- PUD: Pull-up Disable
This PUD bit must be set (one) to disable internal pull-up registers at Port B.
•
Bit 5 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP instruction is executed. To avoid
the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit
just before the execution of the SLEEP instruction.
•
Bits 4,3 - SM1,SM0: Sleep Mode Select bits 1 and 0
These bits select between the three available Sleep modes, as shown in the following table.
For details, refer to the paragraph “Sleep Modes” below.
•
Bit 2 - Res: Reserved bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit
7
6
5
4
3
2
1
0
$35
-
PUD
SE
SM1
SM0
-
ISC01
ISC00
MCUCR
Read/Write
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Table 7.
Sleep Modes
SM1
SM0
Sleep Mode
0
0
Idle Mode
0
1
ADC Noise Reduction Mode
1
0
Power-down Mode
1
1
Reserved
