41.5.8. Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC),
except the following register:
•
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-
Protection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller
on page 50
41.5.9. Analog Connections
I/O-pins (AINx), as well as the VREFA/VREFB reference voltage pins are analog inputs to the ADC.
41.5.10. Calibration
The BIAS and LINEARITY calibration values from the production test must be loaded from the NVM
Software Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified
accuracy.
41.6. Functional Description
41.6.1. Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order
to reduce the conversion time, see
Conversion Timing and Sampling Rate
.
The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The input
values can be either internal or external (connected I/O pins). The user can also configure whether the
conversion should be single-ended or differential.
41.6.2. Basic Operation
41.6.2.1. Initialization
The following registers are enable-protected, meaning that they can only be written when the ADC is
disabled (CTRLA.ENABLE=0):
•
Control B register (CTRLB)
•
Reference Control register (REFCTRL)
•
Event Control register (EVCTRL)
•
Calibration register (CALIB)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
41.6.2.2. Enabling, Disabling and Resetting
The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The
ADC is disabled by writing CTRLA.ENABLE=0.
The ADC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled.
Refer to
for details.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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