25.8.1. Control A in COUNT32 mode (CTRLA.MODE=0)
Name:
CTRLA
Offset:
0x00
Reset:
0x0000
Property:
PAC Write-Protection, Enable-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
COUNTSYNC
GPTRST
BKTRST
PRESCALER[3:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MATCHCLR
MODE[1:0]
ENABLE
SWRST
Access
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit 15 – COUNTSYNC: COUNT Read Synchronization Enable
The COUNT register requires synchronization when reading. Disabling the synchronization will prevent
reading valid values from the COUNT register.
This bit is not enable-protected.
Value
Description
0
COUNT read synchronization is disabled
1
COUNT read synchronization is enabled
Bit 14 – GPTRST: GP Registers Reset On Tamper Enable
Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the
peripheral is disabled.
This bit is not synchronized.
Bit 13 – BKTRST: GP Registers Reset On Tamper Enable
All BKUPn registers are affected. This bit can be written only when the peripheral is disabled.
This bit is not synchronized.
Value
Description
0
BKUPn registers will not reset when a tamper condition occurs.
1
BKUPn registers will reset when a tamper condition occurs.
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter
clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These
bits are not synchronized.
Value
Name
Description
0x0
OFF
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV1
CLK_RTC_CNT = GCLK_RTC/1
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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