Atmel ATSAML22G16A-AUT Manual Download Page 282 | Manualshive

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Related Links

PAC - Peripheral Access Controller

on page 50

23.5.9. Analog Connections

Not applicable.

23.6. Functional Description

23.6.1. Voltage Regulator System Operation

23.6.1.1. Enabling, Disabling, and Resetting

The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can
be disabled by writing the Enable bit in the VREG register (VREG.ENABLE) to zero. The main voltage
regulator output supply level is automatically defined by the performance level or the sleep mode selected
in the Power Manager module.

Related Links

PM – Power Manager

23.6.1.2. Initialization

After a Reset, the LDO voltage regulator supplying VDDCORE is enabled.

23.6.1.3. Selecting a Voltage Regulator

In active mode, the type of the main voltage regulator supplying VDDCORE can be switched on the fly.
The two alternatives are a LDO regulator and a Buck converter.

The main voltage regulator switching sequence:

•

The user changes the value of the Voltage Regulator Selection bit in the Voltage Regulator System
Control register (VREG.SEL)

•

The start of the switching sequence is indicated by clearing the Voltage Regulator Ready bit in the
STATUS register (STATUS.VREGRDY=0)

•

Once the switching sequence is completed, STATUS.VREGRDY will read '1'

The Voltage Regulator Ready (VREGRDY) interrupt can also be used to detect a zero-to-one transition of
the STATUS.VREGRDY bit.

23.6.1.4. Voltage Scaling Control

The VDDCORE supply will change under certain circumstances:

•

When a new performance level (PL) is set

•

When the standby sleep mode is entered or left

•

When a sleepwalking task is requested in standby sleep mode

To prevent high peak current on the main power supply and to have a smooth transition of VDDCORE,
both the voltage scaling step size and the voltage scaling frequency can be controlled: VDDCORE is
changed by the selected step size of the selected period until the target voltage is reached.

The Voltage Scaling Voltage Step field is in the VREG register, VREG.VSVSTEP. The Voltage Scaling
Period field is VREG.VSPER.

The following waveform shows an example of changing performance level from PL0 to PL2.

Atmel SAM L22G / L22J / L22N [DATASHEET]

Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016

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Summary of Contents for ATSAML22G16A-AUT

Page 1: ...e mode and down to 490nA in ultra low power backup mode with RTC Features Processor ARM Cortex M0 CPU running at up to 32MHz Single cycle hardware multiplier Micro Trace Buffer Memory Protection Unit...

Page 2: ...by using two TCs One 24 bit Timer Counters for Control TCC with extended functions Four compare channels with optional complementary output Generation of synchronized pulse width modulation PWM patte...

Page 3: ...stal oscillator XOSC32K 0 4 32MHz crystal oscillator XOSC 32 768kHz ultra low power internal oscillator OSCULP32K 16 12 8 4MHz high accuracy internal oscillator OSC16M 48MHz Digital Frequency Locked L...

Page 4: ...8 Power Supply and Start Up Considerations 32 8 1 Power Domain Overview 32 8 2 Power Supply Considerations 32 8 3 Power Up 35 8 4 Power On Reset and Brown Out Detector 35 8 5 Performance Level Overvie...

Page 5: ...tion 81 14 10 Device Identification 82 14 11 Functional Description 83 14 12 Register Summary 89 14 13 Register Description 91 15 Clock System 115 15 1 Clock Distribution 115 15 2 Synchronous and Asyn...

Page 6: ...am 181 19 4 Signal Description 181 19 5 Product Dependencies 182 19 6 Functional Description 182 19 7 Register Summary 185 19 8 Register Description 185 20 PM Power Manager 188 20 1 Overview 188 20 2...

Page 7: ...lock Diagram 312 24 4 Signal Description 312 24 5 Product Dependencies 312 24 6 Functional Description 313 24 7 Register Summary 319 24 8 Register Description 319 25 RTC Real Time Counter 331 25 1 Ove...

Page 8: ...515 28 4 Signal Description 516 28 5 Product Dependencies 516 28 6 Functional Description 517 28 7 Register Summary 524 28 8 Register Description 524 29 PORT I O Pin Controller 538 29 1 Overview 538...

Page 9: ...5 Product Dependencies 646 33 6 Functional Description 648 33 7 Register Summary 657 33 8 Register Description 658 34 SERCOM I2C SERCOM Inter Integrated Circuit 678 34 1 Overview 678 34 2 Features 678...

Page 10: ...erview 888 38 2 Features 888 38 3 Block Diagram 889 38 4 Signal Description 890 38 5 Product Dependencies 890 38 6 Functional Description 891 38 7 Register Summary 900 38 8 Register Description 902 39...

Page 11: ...verview 1060 43 2 Features 1060 43 3 Block Diagram 1061 43 4 Signal Description 1061 43 5 Product Dependencies 1061 43 6 Functional Description 1063 43 7 Register Summary 1088 43 8 Register Descriptio...

Page 12: ...External Reset Circuit 1197 48 5 Unused or Unconnected Pins 1198 48 6 Clocks and Crystal Oscillators 1198 48 7 Programming and Debug Ports 1201 48 8 USB Interface 1204 48 9 LCD 1205 48 10 SERCOM I2C...

Page 13: ...16 bit resolution two analog comparators with window mode Peripheral Touch Controller supporting up to 256 buttons sliders wheels and proximity sensing programmable Watchdog Timer brown out detector a...

Page 14: ...utput channels per TC instance 2 2 2 Timer Counter for Control TCC instances 1 1 1 Waveform output channels per TCC 4 4 4 DMA channels 16 16 16 USB interface 1 1 1 AES engine 1 1 1 Configurable Custom...

Page 15: ...QFP WLCSP Oscillators Event System channels 8 8 8 SW Debug Interface Yes Yes Yes Watchdog Timer WDT Yes Yes Yes Note 1 L22J L22G All SLCD Pins can be configured also as GPIOs L22N 44 SLCD Pins can be...

Page 16: ...ision DSU DID REVISION The device variant denotes functional differences whereas the die revision marks evolution of the die 3 1 SAM L22N Table 3 1 SAM L22N Ordering Codes Ordering Code FLASH bytes SR...

Page 17: ...QFN48 ATSAML22G18A UUT WLCSP49 3 4 Device Identification The DSU Device Service Unit peripheral provides the Device Selection bits in the Device Identification register DID DEVSEL in order to identify...

Page 18: ...vision DSU DID REVISION The device variant denotes functional differences whereas the die revision marks evolution of the die Related Links DSU Device Service Unit on page 76 DID on page 100 Atmel SAM...

Page 19: ...CONTROLLER Cache M DMA 1x TIMER COUNTER FOR CONTROL WO7 IOBUS DMA DMA DMA DMA DMA MEMORY TRACE BUFFER S WO0 WO1 REAL TIME COUNTER WATCHDOG TIMER RESETN OSCILLATORS CONTROLLER XOUT XIN XOUT32 XIN32 OS...

Page 20: ...tances Timer Counter instances PTC signals and ADC signals The number of PTC X and Y signals is configurable Related Links Peripherals Configuration Summary on page 73 Atmel SAM L22G L22J L22N DATASHE...

Page 21: ...CORE VDDANA VDDIO Figure 5 2 49 Pin WLCSP P A 0 0 P A 0 1 G N D A V D D A N A P A 0 2 P A 0 3 P B 0 8 P B 0 9 P A 0 5 P A 0 4 P A 0 6 P A 0 7 G N D P A 0 8 P A 0 9 P A 1 0 P A 1 1 G N D V D D I O 3 V...

Page 22: ...GND VDDOUT PA1 VDDA PB1 PB0 PB3 PB2 PB5 PB4 PA2 PA3 PA7 PA6 PA4 PB7 PB6 PB8 PB9 PA12 PA13 PA14 PA15 PB23 PB22 PB30 PB31 PB11 PA8 PA9 PA5 PA31 PA30 PA27 PA10 PA11 PB12 PB13 PB14 PB15 VDDIO GND VDDIO GN...

Page 23: ...ANA PB1 PB0 PB3 PB2 PB30 PB31 PC2 PC3 PC5 PA7 PA6 PA4 PA5 PB8 PB9 PA12 PA13 PA14 PA15 PB25 PB24 PC7 PB23 PB22 PA1 PA0 PC26 PC24 PC25 PC6 PC27 PA31 PA30 VDDCORE PA27 PA16 PA17 PA18 PA19 VDDIO PA24 PA25...

Page 24: ...l Non Maskable Interrupt input Digital Generic Clock Generator GCLK GCLK_IO 4 0 Generic Clock source clock inputs or generic clock generator output Digital Custom Control Logic CCL IN 11 0 Logic Input...

Page 25: ...rt A Digital PB09 PB00 Parallel I O Controller I O Port B Digital PB25 PB11 Parallel I O Controller I O Port B Digital PB31 PB30 Parallel I O Controller I O Port B Digital PC03 PC00 Parallel I O Contr...

Page 26: ...l SOF 1kHz USB Start of Frame Digital Real Timer Clock RTC RTC_IN 4 0 Tamper or external wake up pins Digital RTC_OUT Tamper output Digital Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22...

Page 27: ...3 ADC VREFA ADC AIN 1 AC AIN 1 PTC XY 9 5 9 PB04 EIC EXTINT 4 ADC AIN 12 AC AIN 2 PTC XY 10 6 10 PB05 EIC EXTINT 5 ADC AIN 13 AC AIN 3 PTC XY 11 9 13 PB06 EIC EXTINT 6 ADC AIN 14 PTC XY 12 SLCD LP 0 C...

Page 28: ...T 2 PTC X 30 SLCD LP 34 SERCOM1 PAD 2 SERCOM2 PAD 2 TCC WO 2 AC CMP 0 CCL IN 2 28 38 55 PA19 EIC EXTINT 3 PTC X 31 SLCD LP 35 SERCOM1 PAD 3 SERCOM2 PAD 3 TCC WO 3 AC CMP 1 CCL OUT 0 56 PC16 EIC EXTINT...

Page 29: ...N 1 62 98 PB01 EIC EXTINT 1 ADC AIN 9 SERCOM3 PAD 3 SERCOM5 PAD 3 TC 3 WO 1 RTC IN 2 RTC OUT SUPC OUT 0 CCL IN 2 47 63 99 PB02 EIC EXTINT 2 ADC AIN 10 SERCOM3 PAD 0 SERCOM5 PAD 0 TC 2 WO 0 RTC IN 1 SU...

Page 30: ...ce Pinout Only the SWCLK pin is mapped to the normal PORT functions A debugger cold plugging or hot plugging detection will automatically switch the SWDIO port to the SWDIO function Table 7 4 Serial W...

Page 31: ...B04 PB05 PB06 PB07 PB08 PB09 VDDANA pin8 GNDANA pin7 2 PA08 PA09 PA10 PA11 VDDIO pin21 GND pin22 3 PA12 PA13 PA14 PA15 PB11 PB12 PB13 PB14 PB15 VDDIO pin21 VDDIO pin34 GND pin22 GND pin33 4 PA16 PA17...

Page 32: ...DDIO powers I O lines and OSC16M XOSC the internal regulator for VDDCORE and the Automatic Power Switch Voltage is 1 62V to 3 63V VDDANA powers I O lines and the ADC AC LCD and PTC Voltage is 1 62V to...

Page 33: ...e most efficient mode when the CPU and peripherals are running This mode can be selected by software on the fly Low Power LP mode This is the default mode used when the chip is in standby mode Shutdow...

Page 34: ...8 2 4 Power Up Sequence 8 2 4 1 Supply Order VDDIO and VDDANA must have the same supply sequence Ideally they must be connected together 8 2 4 2 Minimum Rise Rate One integrated power on reset POR cir...

Page 35: ...on Refer to the Clock Mask Register section in the PM Power Manager documentation for the list of clocks that are running by default Synchronous system clocks that are running receive the 4MHz clock f...

Page 36: ...ted Links SUPC Supply Controller on page 279 8 5 Performance Level Overview By default the device will start in Performance Level 0 This PL0 is aiming for the lowest power consumption by limiting logi...

Page 37: ...apability will be ensured in PL2 When transitioning between performance levels the Supply Controller SUPC will provide a configurable smooth voltage scaling transition Atmel SAM L22G L22J L22N DATASHE...

Page 38: ...x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 0x40002000 0x40002400 0x40002800 0x40002C00 0x40003000 0x41000000 USB DSU NVMCTRL PORT DMAC MTB HMATRIXHS AHB APB Bridge B 0x41002000 0x40004000 0...

Page 39: ...edded Flash 0x00000000 256 128 64 Embedded RWW section 0x00400000 8 4 2 Embedded SRAM 0x20000000 32 16 8 Peripheral Bridge A 0x40000000 64 64 64 Peripheral Bridge B 0x41000000 64 64 64 Peripheral Brid...

Page 40: ...on 0x06 SUPC BOD33 14 BOD33 Disable BOD33 Disable at power on 0x0 SUPC BOD33 16 15 BOD33 Action BOD33 Action at power on 0x1 SUPC BOD33 25 17 Reserved Factory settings do not change 0x08F 26 WDT Enab...

Page 41: ...AL ADC Bias Calibration Should be written to CALIB register 12 6 Reserved Reserved for future use 17 13 USB TRANSN USB TRANSN calibration value Should be written to the USB PADCAL register 22 18 USB T...

Page 42: ...Table Offset Register Present or absent Present Unprivileged Privileged support Present or absent Present Memory Protection Unit Not present or 8 region 8 region Reset all registers Present or absent...

Page 43: ...ility to the Cortex M0 processor Refer to section MTB Micro Trace Buffer and the CoreSight MTB M0 Technical Reference Manual for details http www arm com Memory Protection Unit MPU The Memory Protecti...

Page 44: ...flag is set and the corresponding interrupt is enabled The interrupt requests for one peripheral are ORed together on system level generating one interrupt request for each peripheral An interrupt req...

Page 45: ...ce buffer in SRAM is configurable by software CoreSight compliant 11 3 2 Overview When enabled the MTB records the changes in program flow that are reported by the Cortex M0 processor over the executi...

Page 46: ...ight ROM Table The offset of each register from the base address is fixed and as defined by the CoreSight MTB M0 Technical Reference Manual The MTB has four programmable registers to control the behav...

Page 47: ...Fetch 0 DSU Privileged SRAM access MASTERS DMAC Fetch 1 DSU DMAC WB 0 DMAC WB 1 DSU USB DSU MTB Table 11 4 High Speed Bus Matrix Masters High Speed Bus Matrix Masters Master ID CM0 Cortex M0 Processor...

Page 48: ...SABLE 0x0 or LOW 0x1 there will be a minimum latency of one cycle for the RAM access The priority order for concurrent accesses are decided by two factors First the QoS level for the master and second...

Page 49: ...SCTRL FQOS 0x2 DMAC Direct Memory Access Controller Write Back Access 5 6 Direct IP QOSCTRL WRBQ OS 0x2 USB Universal Serial Bus 7 Direct IP QOSCTRL 0x3 MTB Micro Trace Buffer 8 Direct STATIC 3 0x3 No...

Page 50: ...ts access errors for the peripheral modules or bridges 12 3 Block Diagram Figure 12 1 PAC Block Diagram INTFLAG PERIPHERAL m PERIPHERAL 0 BUSn BUS0 Peripheral ERROR Peripheral ERROR WRITE CONTROL WRIT...

Page 51: ...all peripherals is disabled and the PAC continues normal operation 12 4 8 Register Access Protection All registers with write access can be write protected optionally by the Peripheral Access Controll...

Page 52: ...Protected write To avoid unexpected writes to a peripheral s registers each peripheral can be write protected Only the registers denoted as PAC Write Protection in the module s datasheet can be prote...

Page 53: ...status or when the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS register The errors generated while accessing the PAC module regist...

Page 54: ...output event Error ERR Generated when one of the interrupt flag registers bits is set Writing a one to an Event Output bit in the Event Control Register EVCTRL ERREO enables the corresponding output e...

Page 55: ...0x15 15 8 FREQM EIC RTC WDT 0x16 23 16 0x17 31 24 0x18 INTFLAGB 7 0 MTB DMAC PORT NVMCTRL DSU USB 0x19 15 8 0x1A 23 16 0x1B 31 24 0x1C INTFLAGC 7 0 TCC SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0...

Page 56: ...uarters and 16 bit halves of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed directly Some registers are optionally write protected by the Peripheral Access Controller PAC...

Page 57: ...key Value Name Description 0x0 OFF No action 0x1 CLEAR Clear the peripheral write control 0x2 SET Set the peripheral write control 0x3 LOCK Set and lock the peripheral write control until the next ha...

Page 58: ...12 2 PERID Values Periph Bridge Name BridgeNumber PERID Values A 0 0 N B 1 32 N C 2 64 N D 3 96 N E 4 128 N Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 20...

Page 59: ...Peripheral Access Error Event Output is enabled or not When enabled an event will be generated when one of the interrupt flag registers bits INTFLAGAHB INTFLAGn is set Value Description 0 Peripheral...

Page 60: ...ble This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits INTFLAGAHB INTFLAGn is set Writing...

Page 61: ...ble This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits INTFLAGAHB INTFLAGn is set Writing...

Page 62: ...cess Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 HSRAMDMAC HPB2 HPB0 HPB1 HSRAMDSU HSRAMCM0P FLASH Access R W R W R W R W R W R W R W Rese...

Page 63: ...24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 FREQM EIC RTC WDT Access R W R W R W R W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM...

Page 64: ...Bit 2 MCLK Interrupt Flag for MCLK Bit 1 PM Interrupt Flag for PM Bit 0 PAC Interrupt Flag for PAC Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 64...

Page 65: ...interrupt flag Name INTFLAGB Offset 0x18 Reset 0x000000 Property Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3...

Page 66: ...0 19 18 17 16 CCL TRNG AES Access R W R W R W Reset 0 0 0 Bit 15 14 13 12 11 10 9 8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCC...

Page 67: ...its 8 9 10 11 TCn Interrupt Flag for TCn n 3 0 Bits 1 2 3 4 5 6 SERCOMn Interrupt Flag for SERCOMn n 5 0 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 6...

Page 68: ...0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 11 FREQM Peripheral FREQM Write Protection Status Bit 10 EIC Peripheral EIC Write...

Page 69: ...tus Bit 2 MCLK Peripheral MCLK Write Protection Status Bit 1 PM Peripheral PM Write Protection Status Bit 0 PAC Peripheral PAC Write Protection Status Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E S...

Page 70: ...17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 MTB DMAC PORT NVMCTRL DSU USB Access R R R R R R Reset 0 0 0 0 0 0 Bit 5 MTB Peripheral MTB Write Protection Status Bit 4...

Page 71: ...R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCC SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 18 CCL Peripheral CCL Write Protecti...

Page 72: ...n Status Bits 8 9 10 11 TCn Peripheral TCn Write Protection Status n 3 0 Bits 1 2 3 4 5 6 SERCOMn Peripheral SERCOMn Write Protection Status n 5 0 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L...

Page 73: ...8 M reference 1 FDPLL96 M clk source 2 FDPLL96 M 32kHz 4 N 0 CFD Y PDTOP OSC32K CTRL 0x40001 400 0 5 Y Backup 5 N 1 CFD PDBACK UP SUPC 0x40001 800 0 6 Y Backup 6 N N A PDBACK UP GCLK 0x40001 C00 7 Y C...

Page 74: ...0 A00 11 3 Y CPU 18 CORE 15 SLOW 3 N 6 RX 7 TX Y PDTOP SERCO M3 0x42001 000 12 4 Y CPU 19 CORE 15 SLOW 4 N 8 RX 9 TX Y PDTOP SERCO M4 0x42001 400 13 5 Y CPU 20 CORE 15 SLOW 5 N 10 RX 11 TX Y PDTOP SER...

Page 75: ...13 Y CPU 26 13 N 21 22 SOC0 1 55 56 COMP0 1 57 WIN0 Y PDTOP PTC 0x42003 800 22 14 Y CPU 27 14 N 23 STCONV 58 EOC 59 WCOMP PDTOP SLCD 0x42003 C00 23 15 Y CPU 15 N 60 62 FC0 2 63 DT 32 DMU 33 ACMDR DY 3...

Page 76: ...Class B compliance for example The DSU can be accessed simultaneously by a debugger and the CPU as it is connected on the High Speed Bus Matrix For security reasons some of the DSU features will be li...

Page 77: ...s peripheral other parts of the system must be configured correctly as described below 14 5 1 IO Lines The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to s...

Page 78: ...Access Controller on page 50 14 5 7 Analog Connections Not applicable 14 6 Debug Operation 14 6 1 Principle of Operation The DSU provides basic services to allow on chip debug using the ARM Debug Acc...

Page 79: ...Hot Plugging Hot Plugging is the detection of a debugger probe when the system is not in reset Hot Plugging is not possible under reset because the detector is reset when POR or RESET are asserted Ho...

Page 80: ...ries prior to erasing the Flash array To ensure that the Chip Erase operation is completed check the Done bit of the Status A register STATUSA DONE The Chip Erase operation depends on clocks and power...

Page 81: ...sing the AHB AP are limited to the DSU address range and DSU commands are restricted When issuing a Chip Erase sensitive information is erased from volatile memory and Flash The DSU implements a secur...

Page 82: ...ugger Hot Plugging No Related Links NVMCTRL Non Volatile Memory Controller on page 515 Security Bit on page 523 14 10 Device Identification Device identification relies on the ARM CoreSight component...

Page 83: ...ation refer to the ARM Debug Interface Version 5 Architecture Specification 14 10 2 Chip Identification Method The DSU DID register identifies the device by implementing the following information Proc...

Page 84: ...2 command is issued from The internal range the CRC32 can be operated at any memory location The external range the CRC32 operation is restricted DATA ADDR and LENGTH values are forced see below Table...

Page 85: ...nge data between the CPU and the debugger during run time as well as in debug mode This enables the user to build a custom debug protocol using only these registers The DCC0 and DCC1 registers are acc...

Page 86: ...ults The tester should monitor the STATUSA register When the operation is completed STATUSA DONE is set There are two different modes ADDR AMOD 0 exit on error default In this mode the algorithm termi...

Page 87: ...Read 0 write 1 decrement address 4 Read 1 write 0 decrement address 5 Read 0 write 1 6 Read 1 write 0 decrement address 7 Read all zeros bit_index is not used Table 14 5 AMOD Bit Descriptions for MBIS...

Page 88: ...rotected Chip Erase command and status Yes CRC32 Yes only full array or full EEPROM CoreSight Compliant Device identification Yes Debug communication channels Yes Testing of onboard memories MBIST No...

Page 89: ...x11 15 8 DATA 15 8 0x12 23 16 DATA 23 16 0x13 31 24 DATA 31 24 0x14 DCC1 7 0 DATA 7 0 0x15 15 8 DATA 15 8 0x16 23 16 DATA 23 16 0x17 31 24 DATA 31 24 0x18 DID 7 0 DEVSEL 7 0 0x19 15 8 DIE 3 0 REVISION...

Page 90: ...4 0x1FE8 PID2 7 0 REVISION 3 0 JEPU JEPIDCH 2 0 0x1FE9 15 8 0x1FEA 23 16 0x1FEB 31 24 0x1FEC PID3 7 0 REVAND 3 0 CUSMOD 3 0 0x1FED 15 8 0x1FEE 23 16 0x1FEF 31 24 0x1FF0 CID0 7 0 PREAMBLEB0 7 0 0x1FF1...

Page 91: ...ves of a 16 bit register can be accessed directly Some registers are optionally write protected by the Peripheral Access Controller PAC Optional PAC write protection is denoted by the PAC Write Protec...

Page 92: ...Memory Built In Self Test Writing a 0 to this bit has no effect Writing a 1 to this bit starts the memory BIST algorithm Bit 2 CRC 32 bit Cyclic Redundancy Check Writing a 0 to this bit has no effect...

Page 93: ...it is set when a DSU operation failure is detected Bit 2 BERR Bus Error Writing a 0 to this bit has no effect Writing a 1 to this bit clears the Bus Error bit This bit is set when a bus error is detec...

Page 94: ...ain Bit 1 DBGPRES Debugger Present Writing a 0 to this bit has no effect Writing a 1 to this bit has no effect This bit is set when a debugger probe is detected This bit is never cleared Bit 0 PROT Pr...

Page 95: ...0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR 5 0 AMOD 1 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 2 ADDR 29 0 Address Initial word start address needed for memory operations Bit...

Page 96: ...GTH 21 14 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LENGTH 13 6 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LENGTH 5 0...

Page 97: ...16 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA 7 0 Access R W...

Page 98: ...9 18 17 16 DATA 23 16 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0...

Page 99: ...9 18 17 16 DATA 23 16 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0...

Page 100: ...The value of this field defines the processor used on the device Bits 27 23 FAMILY 4 0 Product Family The value of this field corresponds to the Product Family part of the ordering code Bits 21 16 SER...

Page 101: ...in a product family and product series Refer to the Ordering Information for device configurations and corresponding values for Flash memory density pin count and device variant Atmel SAM L22G L22J L2...

Page 102: ...1 x Bits 31 12 ADDOFF 19 0 Address Offset The base address of the component relative to the base address of this ROM table Bit 1 FMT Format Always reads as 1 indicating a 32 bit ROM table Bit 0 EPRES...

Page 103: ...1 x Bits 31 12 ADDOFF 19 0 Address Offset The base address of the component relative to the base address of this ROM table Bit 1 FMT Format Always read as 1 indicating a 32 bit ROM table Bit 0 EPRES...

Page 104: ...6 END 23 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 END 15 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 END 7 0 Access R R R R R R R R Reset 0 0 0...

Page 105: ...stem Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table This bit is set at power up if the device is not protected indicating that the system...

Page 106: ...3 2 1 0 FKBC 3 0 JEPCC 3 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7 4 FKBC 3 0 4KB Count These bits will always return zero when read indicating that this debug component occupies one 4KB b...

Page 107: ...Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PARTNBL 7 0 Access R R R R R R R R Reset 1 1 0 1 0 0 0 0 Bits 7 0 PARTNBL 7 0 Part Number Low These bits will always return 0xD0 when r...

Page 108: ...Access R R R R R R R R Reset 1 1 1 1 1 1 0 0 Bits 7 4 JEPIDCL 3 0 Low part of the JEP 106 Identity Code These bits will always return 0xF when read indicating a Atmel device Atmel JEP 106 identity co...

Page 109: ...ts 7 4 REVISION 3 0 Revision Number Revision of the peripheral Starts at 0x0 and increments by one at both major and minor revisions Bit 3 JEPU JEP 106 Identity Code is used This bit will always retur...

Page 110: ...5 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVAND 3 0 CUSMOD 3 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7 4 REVAND 3 0 Revision Number These bits will always return 0x0 when read...

Page 111: ...22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB0 7 0 Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 Bits 7 0 PREAMBLEB0 7 0 Preamble Byte 0 These b...

Page 112: ...E 3 0 Access R R R R R R R R Reset 0 0 0 1 0 0 0 0 Bits 7 4 CCLASS 3 0 Component Class These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table refer to th...

Page 113: ...2 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB2 7 0 Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 Bits 7 0 PREAMBLEB2 7 0 Preamble Byte 2 These bi...

Page 114: ...2 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB3 7 0 Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 Bits 7 0 PREAMBLEB3 7 0 Preamble Byte 3 These bi...

Page 115: ...nce WDT 32kHz 1kHz 32kHz 1kHz CLK_ULP32K EIC SLCD CLK_SLCD_OSC The SAM L22 clock system consists of Clock sources controlled by OSCCTRL and OSC32KCTRL A clock source provides a time base that is used...

Page 116: ...l Channel 16 SERCOM 0 Syncronous Clock Controller MCLK CLK_SERCOM0_APB GCLK_SERCOM0_CORE GCLK 15 2 Synchronous and Asynchronous Clocks As the CPU and the peripherals can be in different clock domains...

Page 117: ...ring both read and write synchronization the corresponding bit in SYNCBUSY is shared Figure 15 3 Register Synchronization Overview Synchronous Domain CLK_APB Asynchronous Domain GCLK Non Sync d reg Pe...

Page 118: ...ing a read synchronized register before its corresponding SYNCBUSY bit is cleared will return the last synchronized value before sleep mode Moreover if a register is also write synchronized any write...

Page 119: ...Generic Clock Periph Channel Clock request Peripheral Clock request ENABLE RUNSTDBY ONDEMAND CLKEN RUNSTDBY ENABLE RUNSTDBY GENEN All clock sources in the system can be run in an on demand mode the cl...

Page 120: ...eral will be lower At the same time the synchronization to the synchronous CPU clock domain is dependent on the peripheral clock speed and will take longer with a slower peripheral clock This will cau...

Page 121: ...number of Peripheral Clocks depends on how many peripherals the device has Note The Generator 0 is always the direct source of the GCLK_MAIN signal 16 2 Features Provides a device defined configurable...

Page 122: ...r GCLK_PERIPH 1 GCLK_PERIPH m 16 4 Signal Description Table 16 1 GCLK Signal Description Signal Name Type Description GCLK_IO 7 0 Digital I O Clock source for Generators when input Generic Clock signa...

Page 123: ...ite protected by the Peripheral Access Controller PAC Note Optional write protection is indicated by the PAC Write Protection property in the register description When the CPU is halted in debug mode...

Page 124: ...CLK will be reset to their initial state except for Peripheral Channels and associated Generators that have their Write Lock bit set to 1 PCHCTRLm WRTLOCK For further details refer to Configuration Lo...

Page 125: ...lue in the Division Factor bit field of the Generator Control register GENCTRLn DIV How the actual division factor is calculated is depending on the Divide Selection bit GENCTRLn DIVSEL If GENCTRLn DI...

Page 126: ...zation is complete The Peripheral Clock is gated when disabled Related Links PCHCTRLmn on page 138 16 6 3 3 Selecting the Clock Source for a Peripheral When changing a peripheral clock source by writi...

Page 127: ...f the system is in a sleep mode where the Generic Clocks are stopped a peripheral that needs its clock in order to execute a process must request it from the Generic Clock Controller The Generic Clock...

Page 128: ...heral clock domains some registers need to be synchronized when written or read An exception is the Channel Enable bit in the Peripheral Channel Control registers PCHCTRLm CHEN When changing this bit...

Page 129: ...31 24 DIV 15 8 0x28 GENCTRLn2 7 0 SRC 3 0 0x29 15 8 RUNSTDBY DIVSEL OE OOV IDC GENEN 0x2A 23 16 DIV 7 0 0x2B 31 24 DIV 15 8 0x2C GENCTRLn3 7 0 SRC 3 0 0x2D 15 8 RUNSTDBY DIVSEL OE OOV IDC GENEN 0x2E...

Page 130: ...8 0x9A 23 16 0x9B 31 24 0x9C PCHCTRLm7 7 0 WRTLOCK CHEN GEN 3 0 0x9D 15 8 0x9E 23 16 0x9F 31 24 0xA0 PCHCTRLm8 7 0 WRTLOCK CHEN GEN 3 0 0xA1 15 8 0xA2 23 16 0xA3 31 24 0xA4 PCHCTRLm9 7 0 WRTLOCK CHEN...

Page 131: ...8 0xC6 23 16 0xC7 31 24 0xC8 PCHCTRLm18 7 0 WRTLOCK CHEN GEN 3 0 0xC9 15 8 0xCA 23 16 0xCB 31 24 0xCC PCHCTRLm19 7 0 WRTLOCK CHEN GEN 3 0 0xCD 15 8 0xCE 23 16 0xCF 31 24 0xD0 PCHCTRLm20 7 0 WRTLOCK C...

Page 132: ...ition the 8 bit quarters and 16 bit halves of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed directly Some registers are optionally write protected by the Peripheral Acces...

Page 133: ...enerators that have their WRTLOCK bit in PCHCTRLm set to 1 Refer to GENCTRL Reset Value for details on GENCTRL register reset Refer to PCHCTRL Reset Value for details on PCHCTRL register reset Due to...

Page 134: ...RST register bit between clock domains is complete This bit is set when the synchronization of the CTRLA SWRST register bit between clock domains is started Bits 2 3 4 5 6 GENCTRLx Generator Control x...

Page 135: ...n value for the corresponding Generator The actual division factor is dependent on the state of DIVSEL The number of relevant DIV bits for each Generator can be seen in this table Written bits outside...

Page 136: ...lue Description 0 No Generator clock signal on pin GCLK_IO 1 The Generator clock signal is output on the corresponding GCLK_IO unless GCLK_IO is selected as a generator source in the GENCTRLn SRC bit...

Page 137: ...se A Power Reset will reset all GENCTRLn registers the Reset values of the GENCTRLn registers are shown in table below Table 16 5 GENCTRLn Reset Value after a Power Reset GCLK Generator Reset Value af...

Page 138: ...rator n GENCTRLn as assigned in PCHCTRLm GEN will also be locked It can only be unlocked by a Power Reset Note that Generator 0 cannot be locked Value Description 0 The Peripheral Channel register and...

Page 139: ...e the content of that PCHCTRL remains unchanged PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping Table 16 9 PCHCTRLm Mapping index m Name Description 0 GCLK_DFLL48M_REF DFLL48M Re...

Page 140: ..._CORE 17 GCLK_SERCOM1_CORE SERCOM1_CORE 18 GCLK_SERCOM2_CORE SERCOM2_CORE 19 GCLK_SERCOM3_CORE SERCOM3_CORE 20 GCLK_SERCOM4_CORE SERCOM4_CORE 21 GCLK_SERCOM5_CORE SERCOM5_CORE 22 GCLK_TCC0 TCC0 23 GCL...

Page 141: ...dition the clock can be masked for individual modules enabling the user to minimize power consumption 17 2 Features Generates CPU AHB and APB system clocks Clock source and division factor from GCLK C...

Page 142: ...CPU from executing instructions 17 5 3 3 APBx and AHBx Clock The APBx clocks CLK_APBx and the AHBx clocks CLK_AHBx are the root clock source used by modules requiring a clock on the APBx and the AHBx...

Page 143: ...GCLK_MAIN is divided by an 8 bit prescaler Each of the derived clocks can run from any divided or undivided main clock ensuring synchronous clock sources for each clock domain Each clock domain CPU BU...

Page 144: ...peripheral modules Writing DIV bits allows a new clock setting to be written to all synchronous clocks belonging to the corresponding clock domain at the same time Each clock domain can be changed wi...

Page 145: ...rresponding bit in the Clock Mask registers APBxMASK to 0 1 The default state of the peripheral clocks is shown here Table 17 1 Peripheral Clock Default State CPU Clock Domain Peripheral Clock Default...

Page 146: ...be read or written The module can be re enabled later by writing the corresponding mask bit to 1 A module may be connected to several clock domains for instance AHB and APB in which case it will have...

Page 147: ...The interrupt request remains active until the interrupt flag is cleared the interrupt is disabled or the peripheral is reset An interrupt flag is cleared by writing a 1 to the corresponding bit in th...

Page 148: ...C APBCMASK 7 0 TCC0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS 0x1D 15 8 SLCD PTC AC ADC TC3 TC2 TC1 TC0 0x1E 23 16 CCL TRNG AES 0x1F 31 24 17 8 Register Description Registers can be 8 16 o...

Page 149: ...in this register are reserved Name CTRLA Offset 0x00 Reset 0x00 Property PAC Write Protection Bit 7 6 5 4 3 2 1 0 Access Reset Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datas...

Page 150: ...3 2 1 0 CKRDY Access R W Reset 0 Bit 0 CKRDY Clock Ready Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the Clock Ready Interrupt Enable bit and the correspo...

Page 151: ...Property PAC Write Protection Bit 7 6 5 4 3 2 1 0 CKRDY Access R W Reset 0 Bit 0 CKRDY Clock Ready Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will set the Clock Re...

Page 152: ...1 to the flag This flag is set when the synchronous CPU APBx and AHBx clocks have frequencies as indicated in the CLKCFG registers and will generate an interrupt if INTENCLR SET CKRDY is 1 Writing a 0...

Page 153: ...domain To ensure correct operation frequencies must be selected so that FHS FCPU FBUP i e BUPDIV CPUDIV HSDIV Frequencies must never exceed the specified maximum frequency for each clock domain Value...

Page 154: ...up clock domain To ensure correct operation frequencies must be selected so that FCPU F_BUP i e BUPDIV CPUDIV Also frequencies must never exceed the specified maximum frequency for each clock domain V...

Page 155: ...W Reset 1 1 1 1 1 1 1 1 Bit 8 NVMCTRL NVMCTRL AHB Clock Enable Value Description 0 The AHB clock for the NVMCTRL is stopped 1 The AHB clock for the NVMCTRL is enabled Bit 7 PAC PAC AHB Clock Enable V...

Page 156: ...APBB APBB AHB Clock Enable Value Description 0 The AHB clock for the APBB is stopped 1 The AHB clock for the APBB is enabled Bit 0 APBA APBA AHB Clock Enable Value Description 0 The AHB clock for the...

Page 157: ...d and reserved for future use For compatibility with future devices always write reserved bits to their reset value If no reset value is given write 0 Bit 11 FREQM FREQM APBA Clock Enable Value Descri...

Page 158: ...Description 0 The APBA clock for the OSC32KCTRL is stopped 1 The APBA clock for the OSC32KCTRL is enabled Bit 4 OSCCTRL OSCCTRL APBA Clock Enable Value Description 0 The APBA clock for the OSCCTRL is...

Page 159: ...APBA clock for the PM is enabled Bit 0 PAC PAC APBA Clock Enable Value Description 0 The APBA clock for the PAC is stopped 1 The APBA clock for the PAC is enabled Atmel SAM L22G L22J L22N DATASHEET A...

Page 160: ...k Enable Value Description 0 The APBB clock for the PORT is stopped 1 The APBB clock for the PORT is enabled Bit 2 NVMCTRL NVMCTRL APBB Clock Enable Value Description 0 The APBB clock for the NVMCTRL...

Page 161: ...B is enabled Reserved bits are unused and reserved for future use For compatibility with future devices always write reserved bits to their reset value If no reset value is given write 0 Atmel SAM L22...

Page 162: ...R W R W R W R W R W R W R W R W Reset 1 1 1 1 1 1 1 1 Bit 18 CCL CCL APBC Clock Enable Value Description 0 The APBC clock for the CCL is stopped 1 The APBC clock for the CCL is enabled Bit 17 TRNG TR...

Page 163: ...k for the ADC is enabled Bit 11 TC3 TC3 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC3 is stopped 1 The APBC clock for the TC3 is enabled Bit 10 TC2 TC2 APBC Mask Clock Enable V...

Page 164: ...ue Description 0 The APBC clock for the SERCOM3 is stopped 1 The APBC clock for the SERCOM3 is enabled Bit 3 SERCOM2 SERCOM2 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM2 i...

Page 165: ...Value Description 0 The APBC clock for the EVSYS is stopped 1 The APBC clock for the EVSYS is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 165...

Page 166: ...K_FREQM_MSR sources can be measured Ratio can be measured with 24 bit accuracy 18 3 Block Diagram Figure 18 1 FREQM Block Diagram ENABLE VALUE REFNUM INTFLAG GCLK_FREQM_REF GCLK_FREQM_MSR DONE START C...

Page 167: ...145 GCLK Generic Clock Controller on page 121 18 5 4 DMA Not applicable 18 5 5 Interrupts The interrupt request line is connected to the interrupt controller Using FREQM interrupt requires the interr...

Page 168: ...page 121 18 6 2 2 Enabling Disabling and Resetting The FREQM is enabled by writing a 1 to the Enable bit in the Control A register CTRLA ENABLE The peripheral is disabled by writing CTRLA ENABLE 0 The...

Page 169: ...terrupt request remains active until the interrupt flag is cleared the interrupt is disabled or the FREQM is reset See INTFLAG for details on how to clear interrupt flags All interrupt requests from t...

Page 170: ...Related Links Register Synchronization on page 116 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 170...

Page 171: ...and the 8 bit halves of a 16 bit register can be accessed directly Some registers require synchronization when read and or written Synchronization is denoted by the Read Synchronized and or Write Syn...

Page 172: ...on 0 The peripheral is disabled 1 The peripheral is enabled Bit 0 SWRST Software Reset Writing a 0 to this bit has no effect Writing a 1 to this bit resets all registers in the FREQM to their initial...

Page 173: ...rty Bit 7 6 5 4 3 2 1 0 START Access W Reset 0 Bit 0 START Start Measurement Value Description 0 Writing a 0 has no effect 1 Writing a 1 starts a measurement Atmel SAM L22G L22J L22N DATASHEET Atmel 4...

Page 174: ...REFNUM 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 7 0 REFNUM 7 0 Number of Reference Clock Cycles Selects the duration of a measurement in number of CLK_FREQM_REF cycles Th...

Page 175: ...pt Enable Writing a 1 to this bit has no effect Writing a 1 to this bit will clear the Measurement Done Interrupt Enable bit which disables the Measurement Done interrupt Value Description 0 The Measu...

Page 176: ...upt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will set the Measurement Done Interrupt Enable bit which enables the Measurement Done interrupt Value Description 0 The Measure...

Page 177: ...0 DONE Mesurement Done This flag is cleared by writing a 1 to it This flag is set when the STATUS BUSY bit has a one to zero transition Writing a 0 to this bit has no effect Writing a 1 to this bit w...

Page 178: ...a 1 to it This bit is set when an overflow condition occurs to the value counter Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the OVF status Bit 0 BUSY FREQM Status Value D...

Page 179: ...R Reset 0 0 Bit 1 ENABLE Enable This bit is cleared when the synchronization of CTRLA ENABLE is complete This bit is set when the synchronization of CTRLA ENABLE is started Bit 0 SWRST Synchronization...

Page 180: ...R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 VALUE 15 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 VALUE 7 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 23...

Page 181: ...urces POR BOD12 BOD33 User reset sources External reset RESET Watchdog reset and System Reset Request Backup exit sources Real Time Counter RTC and Battery Backup Power Switch BBPS 19 3 Block Diagram...

Page 182: ...When the CPU is halted in debug mode the RSTC continues normal operation 19 5 8 Register Access Protection All registers with write access can be optionally write protected by the Peripheral Access C...

Page 183: ...Reset WDT Reset System Reset Request RTC BBPS RTC OSC32KCTRL RSTC CTRLA IORET bit of PM Y N N N N GCLK with WRTLOCK Y Y N N Y Debug logic Y Y Y N Y Others Y Y Y Y Y The external Reset is generated whe...

Page 184: ...tional Features Not applicable 19 6 4 DMA Operation Not applicable 19 6 5 Interrupts Not applicable 19 6 6 Events Not applicable 19 6 7 Sleep Mode Operation The RSTC module is active in all sleep mode...

Page 185: ...quarters and 16 bit halves of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed directly Some registers are optionally write protected by the Peripheral Access Controller PA...

Page 186: ...6 SYST System Reset Request This bit is set if a System Reset Request has occurred Refer to the Cortex processor documentation for more details Bit 5 WDT Watchdog Reset This bit is set if a Watchdog T...

Page 187: ...ing the Battery Backup Mode period Name BKUPEXIT Offset 0x02 Reset Latest Backup Exit Source Property Bit 7 6 5 4 3 2 1 0 BBPS RTC Access R R Reset x x Bit 2 BBPS Battery Backup Power Switch This bit...

Page 188: ...technique consists of adjusting the regulator output voltage to reduce power consumption The user can select on the fly the performance level configuration which best suits the application In backup...

Page 189: ...relevant If Backup sleep mode is requested by the system while in debug mode the core domains are kept on and the debug modules are kept running to allow the debugger to access internal registers When...

Page 190: ...onsumption and maximum operating frequency 20 6 1 2 Power Domains In addition to the supply domains such as VDDIO and VDDANA the device provides these power domains PDTOP PDBACKUP Related Links Power...

Page 191: ...uction and actual writing of the SLEEPCFG register due to bridges Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction Note After power up the MAINV...

Page 192: ...mode the user must select the idle Sleep Mode in the Sleep Configuration register SLEEPCFG SLEEPMODE IDLE Exiting IDLE mode The processor wakes the system up when it detects any non masked interrupt...

Page 193: ...onfiguration is retained When the device exits the BACKUP mode the I O line configuration can either be released or stretched based on the I O Retention bit in the CTRLA register CTRLA IORET If IORET...

Page 194: ...rformance Level Transitions BACKUP ACTIVE PLn IDLE PLn SLEEPCFG IDLE IRQ SLEEPCFG STANDBY IRQ SLEEPCFG BACKUP OFF ACTIVE PL0 RESET PLCFG PLSEL STANDBY Backup Reset ext reset SLEEPCFG OFF 20 6 3 6 Regu...

Page 195: ...ower auto 3 on on Standby case 3 low power low power auto 3 on on Standby case 4 low power low power off on on Backup off off off off on OFF off off off off off Note 1 RAMs mode by default STDBYCFG BB...

Page 196: ...ator YES main voltage regulator 0x1 PERFORMANCE main voltage regulator 0x2 LP 2 2 low power regulator Note 1 SleepWalking is running on GCLK clock or synchronous clock This is not related to XOSC32K o...

Page 197: ...main regulator to transition to the voltage level corresponding to PL2 causing additional wake up time Latency due to the CPU clock source wake up time Latency due to the NVM memory access Latency du...

Page 198: ...bit in the INTFLAG register Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources Refer to the Nested Vector Inte...

Page 199: ...wide Atomic 8 16 and 32 bit accesses are supported In addition the 8 bit quarters and 16 bit halves of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed directly Some registe...

Page 200: ...Bit 2 IORET I O Retention Note This bit is not reset by a backup reset Value Description 0 After waking up from Backup mode I O lines are not held 1 After waking up from Backup mode I O lines are held...

Page 201: ...oftware has to make sure the SLEEPCFG register reads the wanted value before issuing WFI instruction Value Name Definition 0x0 Reserved Reserved 0x1 Reserved Reserved 0x2 IDLE CPU AHBx and APBx clocks...

Page 202: ...time from standby sleep mode Changing this bit when the current performance level is not PL0 is discarded and a violation is reported to the PAC module Value Description 0 The Performance Level mechan...

Page 203: ...ccess R W Reset 0 Bit 0 PLRDY Performance Level Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the Performance Ready Interrupt Enable bit and the correspondi...

Page 204: ...e Protection Bit 7 6 5 4 3 2 1 0 PLRDY Access R W Reset 0 Bit 0 PLRDY Performance Level Ready Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will set the Performance Re...

Page 205: ...Performance Level Ready This flag is set when the performance level is ready and will generate an interrupt if INTENCLR SET PLRDY is 1 Writing a 1 to this bit has no effect Writing a 1 to this bit cl...

Page 206: ...to Table 20 4 for details Value Description 0 No Back Biasing in Standby mode 1 Back Biasing in Standby mode 2 Standby OFF mode 3 Always OFF mode Bits 7 6 VREGSMOD 1 0 VREG Switching Mode Refer to Reg...

Page 207: ...ure detection with safe clock switch Clock failure event output 16MHz Internal Oscillator OSC16M Fast startup 4 8 12 16MHz output frequencies available Digital Frequency Locked Loop DFLL48M Internal o...

Page 208: ...inue to operate in any sleep mode where the selected source clock is running The OSCCTRL interrupts can be used to wake up the device from sleep modes The events can trigger other operations in the sy...

Page 209: ...ar register INTFLAG Note Optional write protection is indicated by the PAC Write Protection property in the register description When the CPU is halted in debug mode all write protection is automatica...

Page 210: ...ed and in most cases result in a lower power consumption The XOSC will behave differently in different sleep modes based on the settings of XOSCCTRL RUNSTDBY XOSCCTRL ONDEMAND and XOSCCTRL ENABLE If X...

Page 211: ...clock activity from the XOSC There must be at least one rising and one falling XOSC clock edge during 4 safe clock periods to meet non failure conditions If no or insufficient activity is detected th...

Page 212: ...tion The OSC16M is an internal oscillator operating in open loop mode and generating 4 8 12 or 16MHz frequency The OSC16M frequency is selected by writing to the Frequency Select field in the OSC16M r...

Page 213: ...s NVM User Row Mapping on page 40 Closed Loop Operation In closed loop operation the DFLL48M output frequency is continuously regulated against a precise reference clock of relatively low frequency Th...

Page 214: ...t frequency On coarse lock the DFLL Locked on Coarse Value bit STATUS DFLLLCKC in the Status register will be set Fine Lock In this stage the control logic tunes the value in DFLLVAL FINE so that the...

Page 215: ...K_DFLL48M 2 MULMAX the DFLL Reference Clock Stopped bit in the Status register STATUS DFLLRCS will be set Detecting a stopped reference clock can take a long time in the order of 217 CLK_DFLL48M cycle...

Page 216: ...cking will quickly compensate for any frequency drift during sleep if DFLLCTRL STABLE is zero If DFLLCTRL LLAW is 1 when disabling the DFLL48M the DFLL48M will lose all its locks and needs to regain t...

Page 217: ...1500 3 16 Thus LDR is set to 1499 and LDRFRAC to 3 Related Links GCLK Generic Clock Controller on page 121 OSC32KCTRL 32KHz Oscillators Controller on page 258 21 6 6 1 Basic Operation Initialization...

Page 218: ...ve startup time Table 21 4 CLK_DPLL Behavior after First Edge Detection LBYPASS CLK_DPLL Behavior 0 Normal Mode the CLK_DPLL is turned off when lock signal is low 1 Lock Bypass Mode the CLK_DPLL is al...

Page 219: ...stable state Figure 21 6 RATIOCTRL register update operation CKR LDR LDRFRAC CK CLK_DPLL mult0 mult1 LOCK LOCKL Digital Filter Selection The PLL digital filter PI controller is automatically adjusted...

Page 220: ...ondition occurs Each interrupt can be individually enabled by writing a 1 to the corresponding bit in the Interrupt Enable Set register INTENSET and disabled by writing a 1 to the corresponding bit in...

Page 221: ...uired because the DFLL controller may change the content of the DFLLVAL register any time If a read operation is issued while the DFLL controller is updating the DFLLVAL content a zero will be returne...

Page 222: ...0E 23 16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 0x0F 31 24 0x10 XOSCCTRL 7 0 ONDEMAND RUNSTDBY SWBACK CFDEN XTALEN ENABLE 0x11 15 8 STARTUP 3 0 AMPGC GAIN 2 0 0x12 CFDPRESC 7 0 CFDPRESC 2 0 0x13 EVCTRL 7...

Page 223: ...of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed directly Some registers are optionally write protected by the Peripheral Access Controller PAC Write protection is denot...

Page 224: ...0 0 0 Bit 19 DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will set the DPLL Loop Ratio Update Complete Interrupt Enable...

Page 225: ...upt is enabled and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set Bit 12 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable Writing 0 to this bit has no effect...

Page 226: ...dy Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will set the DFLL Ready Interrupt Enable bit which enables the DFLL Ready interrupt and set the corresponding interrupt re...

Page 227: ...rrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will set the XOSC Ready Interrupt Enable bit which enables the XOSC Ready interrupt Value Description 0 The XOSC Ready interrupt...

Page 228: ...RTO DPLL Loop Divider Ratio Update Complete Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will clear the DPLL Loop Divider Ratio Update Complete Interrupt Enable bit which...

Page 229: ...upt is enabled and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set Bit 12 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable Writing 0 to this bit has no effect...

Page 230: ...dy Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will clear the DFLL Ready Interrupt Enable bit which disables the DFLL Ready interrupt Value Description 0 The DFLL Ready...

Page 231: ...rupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will clear the XOSC Ready Interrupt Enable bit which disables the XOSC Ready interrupt Value Description 0 The XOSC Ready interrup...

Page 232: ...request if INTENSET DPLLLDRTO is 1 Writing 0 to this bit has no effect Writing 1 to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag Bit 18 DPLLLTO DPLL Lock Timeout This fl...

Page 233: ...KC is 1 Writing 0 to this bit has no effect Writing 1 to this bit clears the DFLL Lock Coarse interrupt flag Bit 10 DFLLLCKF DFLL Lock Fine This flag is cleared by writing 1 to it This flag is set on...

Page 234: ...f the XOSC Clock Failure bit in the Status register STATUS CLKFAIL and will generate an interrupt request if INTENSET CLKFAIL is 1 Writing 0 to this bit has no effect Writing 1 to this bit clears the...

Page 235: ...R R R Reset 0 0 0 0 Bit 19 DPLLLDRTO DPLL Loop Divider Ratio Update Complete Value Description 0 DPLL Loop Divider Ratio Update Complete not detected 1 DPLL Loop Divider Ratio Update Complete detected...

Page 236: ...d Bit 9 DFLLOOB DFLL Out Of Bounds Value Description 0 No DFLL Out Of Bounds detected 1 DFLL Out Of Bounds detected Bit 8 DFLLRDY DFLL Ready Value Description 0 DFLL registers update is ongoing Regist...

Page 237: ...safe clock Bit 1 CLKFAIL XOSC Clock Failure Value Description 0 No XOSC failure detected 1 A XOSC failure was detected Bit 0 XOSCRDY XOSC Ready Value Description 0 XOSC is not ready 1 XOSC is stable...

Page 238: ...Reset 0 0 0 Bits 2 0 CFDPRESC 2 0 Clock Failure Detector Prescaler These bits select the prescaler for the clock failure detector The OSC16M oscillator is used to clock the CFD prescaler The CFD safe...

Page 239: ...lure detector event output is enabled or not and an output event will be generated when the Clock Failure detector detects a clock failure Value Description 0 Clock Failure detector event output is di...

Page 240: ...alue Description 0 The oscillator is always on if enabled 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source The oscillator is disabled if no perip...

Page 241: ...Value Description 0 The oscillator is disabled 1 The oscillator is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 241...

Page 242: ...t start up time for the oscillator The OSCULP32K oscillator is used to clock the start up counter Table 21 5 Start Up Time for External Multipurpose Crystal Oscillator STARTUP 3 0 Number of OSCULP32K...

Page 243: ...cy MHz 0x0 2 0x1 4 0x2 8 0x3 16 0x4 30 0x5 0x7 Reserved Bit 7 ONDEMAND On Demand Control The On Demand operation mode allows the oscillator to be enabled or disabled depending on peripheral clock requ...

Page 244: ...s reset once the XOSC putput clock is switched back to the external clock or crystal oscillator Bit 3 CFDEN Clock Failure Detector Enable This bit controls the clock failure detector Value Description...

Page 245: ...clock before the DFLL is locked 1 Output clock when DFLL is locked Bit 10 BPLCKC Bypass Coarse Lock This bit controls the coarse lock procedure Value Description 0 Bypass coarse lock is disabled 1 Byp...

Page 246: ...opped in standby sleep mode If ONDEMAND is one the DFLL will be running when a peripheral is requesting the clock If ONDEMAND is zero the clock source will always be running in standby sleep mode Bit...

Page 247: ...the peripheral is enabled disabled The value written to DFLLCTRL ENABLE will read back immediately after written Value Description 0 The DFLL oscillator is disabled 1 The DFLL oscillator is enabled At...

Page 248: ...1 0 FINE 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 16 DIFF 15 0 Multiplication Ratio Difference In closed loop mode DFLLCTRL MODE 1 this bit group indicates the differe...

Page 249: ...up indicates the maximum step size allowed during coarse adjustment in closed loop mode When adjusting to a new frequency the expected output frequency overshoot depends on this step size Bits 25 16 F...

Page 250: ...otection Bit 7 6 5 4 3 2 1 0 READREQ Access W Reset 0 Bit 7 READREQ Read Request To be able to read the current value of the DFLLVAL register in closed loop mode this bit must be written to 1 Atmel SA...

Page 251: ...enabled 1 The DPLL is enabled when a peripheral is requesting the DPLL to be used as a clock source The DPLL is disabled if no peripheral is requesting the clock source Bit 6 RUNSTDBY Run in Standby T...

Page 252: ...zation there is a delay between writing these bits and the effect on the DPLL output clock The value written will read back immediately and the DPLLRATIO bit in the DPLL Synchronization Busy register...

Page 253: ...1 0 Access R W R W R W R W R W R W Reset 0 0 0 0 0 0 Bits 26 16 DIV 10 0 Clock Divider These bits set the XOSC clock division factor and can be calculated with following formula f 2 1 Bit 12 LBYPASS...

Page 254: ...put after startup and lock time 1 DPLL clock is output after startup time Bit 2 LPEN Low Power Enable Value Description 0 The low power mode is disabled Time to Digital Converter is enabled 1 The low...

Page 255: ...W Reset 0 0 Bits 1 0 PRESC 1 0 Output Clock Prescaler These bits define the output clock prescaler setting Value Name Description 0x0 DIV1 DPLL output is divided by 1 0x1 DIV2 DPLL output is divided...

Page 256: ...nization is in progress Bit 2 DPLLRATIO DPLL Loop Divider Ratio Synchronization Status Value Description 0 The DPLLRATIO register has been synchronized 1 The DPLLRATIO register value has changed and i...

Page 257: ...put clock is off 1 The DPLL output clock in on Bit 0 LOCK DPLL Lock status bit Value Description 0 The DPLL Lock signal is cleared when the DPLL is disabled or when the DPLL is trying to reach the tar...

Page 258: ...interrupts upon status changes via the INTENSET INTENCLR and INTFLAG registers 22 2 Features 32 768kHz Crystal Oscillator XOSC32K Programmable start up time Crystal or external input clock on XIN32 I...

Page 259: ...crystal oscillator may affect the jitter of neighboring pads 22 5 Product Dependencies In order to use this peripheral other parts of the system must be configured correctly as described below 22 5 1...

Page 260: ...OSC32KCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar improper operation or data loss may result during debugging 22 5 7 Register Acc...

Page 261: ...External Crystal Oscillator Control register XOSC32K ENABLE 1 The XOSC32K is disabled by writing a 0 to the Enable bit in the 32KHz External Crystal Oscillator Control register XOSC32K ENABLE 0 To en...

Page 262: ...tion refer also to Real Time Counter Clock Selection Related Links GCLK Generic Clock Controller on page 121 RTC Real Time Counter on page 331 22 6 3 Clock Failure Detection Operation The Clock Failur...

Page 263: ...caled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application When the XOSC32K clock is switched to the safe clock...

Page 264: ...K can be used as a source for Generic Clock Generators GCLK or for the Real Time Counter RTC To ensure proper operation the GCLK or RTC modules must be disabled before the clock selection is changed R...

Page 265: ...nterrupt is disabled or the OSC32KCTRL is reset See the INTFLAG register for details on how to clear interrupt flags The OSC32KCTRL has one common interrupt request line for all the interrupt sources...

Page 266: ...0 CFDEO 0x18 0x1B Reserved 0x1C OSCULP32K 7 0 0x1D 15 8 WRTLOCK CALIB 4 0 22 8 Register Description Registers can be 8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition the...

Page 267: ...Related Links PAC Peripheral Access Controller on page 50 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 267...

Page 268: ...has no effect Writing a 1 to this bit will clear the XOSC32K Clock Failure Interrupt Enable bit which disables the XOSC32K Clock Failure interrupt Value Description 0 The XOSC32K Clock Failure Detecti...

Page 269: ...it has no effect Writing a 1 to this bit will set the XOSC32K Clock Failure Interrupt Enable bit which enables the XOSC32K Clock Failure interrupt Value Description 0 The XOSC32K Clock Failure Detecti...

Page 270: ...Status register STATUS CLKFAIL and will generate an interrupt request if INTENSET CLKFAIL is 1 Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the XOSC32K Clock Failure Detec...

Page 271: ...ription 0 XOSC32K is not switched and provided the crystal oscillator 1 XOSC32K is switched to be provided by the safe clock Bit 2 CLKFAIL XOSC32K Clock Failure Detector Value Description 0 XOSC32K is...

Page 272: ...bits select the source for the RTC Value Name Description 0x0 ULP1K 1 024kHz from 32KHz internal ULP oscillator 0x1 ULP32K 32 768kHz from 32KHz internal ULP oscillator 0x2 0x3 Reserved 0x4 XOSC1K 1 0...

Page 273: ...EL Access R W Reset 0 Bit 0 SLCDSEL SLCD Clock Source Selection This bit selects the clock source for the SLCD Value Name Description 0 ULP32K 32 768kHz from 32KHz internal ULP oscillator 1 XOSC32K 32...

Page 274: ...1 The XOSC32K configuration is locked Bits 10 8 STARTUP 2 0 Oscillator Start Up Time These bits select the start up time for the oscillator The OSCULP32K oscillator is used to clock the start up count...

Page 275: ...t is enabled Bit 3 EN32K 32KHz Output Enable Value Description 0 The 32KHz output is disabled 1 The 32KHz output is enabled Bit 2 XTALEN Crystal Oscillator Enable This bit controls the connections bet...

Page 276: ...2K frequency divided by 2 Bit 1 SWBACK Clock Switch Back This bit clontrols the XOSC32K output switch back to the external clock or crystal scillator in case of clock recovery Value Description 0 The...

Page 277: ...hether the Clock Failure Detector event output is enabled and an event will be generated when the CFD detects a clock failure Value Description 0 Clock Failure Detector Event output is disabled no eve...

Page 278: ...et Bit 15 WRTLOCK Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration Value Description 0 The OSCULP32K configuration is not locked 1 The OSCULP32K co...

Page 279: ...mpling mode The SUPC generates also a selectable reference voltage which can be used by analog modules like the ADC 23 2 Features Voltage Regulator System Main voltage regulator LDO or Buck Converter...

Page 280: ...BBPS Backup domain Core domain PM performance level sleep mode OUT 1 0 PSOK Wakeup from RTC DETREF VREF reference voltages Main VREG Automatic Power Switch BKOUT 23 4 Signal Description Signal Name Ty...

Page 281: ...interrupts requires the interrupt controller to be configured first Related Links Nested Vector Interrupt Controller on page 44 23 5 6 Events Not applicable 23 5 7 Debug Operation When the CPU is halt...

Page 282: ...Regulator System Control register VREG SEL The start of the switching sequence is indicated by clearing the Voltage Regulator Ready bit in the STATUS register STATUS VREGRDY 0 Once the switching sequ...

Page 283: ...level or remains in the current performance level Table 23 1 VDDCORE Level in Standby Mode VREG RUNSTDBY VREG STDBYPL0 VDDCORE Supply in Standby Mode 0 LPVREG 1 0 MAINVREG in current performance leve...

Page 284: ...tch 23 6 3 1 Initialization The Battery Backup Power Switch BBPS is disabled at power up and the backup domain is supplied by main power 23 6 3 2 Forced Battery Backup Power Switch The Backup domain i...

Page 285: ...tch is not stopped in any sleep mode Entering Battery Backup Mode Entering backup mode can be triggered by either Wait for interrupt WFI instruction Automatic Power Switch BBPS CONF APWS When the Auto...

Page 286: ...nd hysteresis BODVDD ACTION and BODVDD HYST The BOD33 register is Enable Protected meaning that they can only be written when the respective BOD is disabled BOD33 ENABLE 0 and SYNCBUSY BOD33EN 0 As lo...

Page 287: ...toring the supply voltage VDD or VBAT depending on BOD33 VMON if it is enabled BOD33 ENABLE 1 and if the BOD33 Configuration bit in the BOD33 register is cleared BOD33 ACTCFG 0 for active mode BOD33 S...

Page 288: ...ackup domain i e VDD or VBAT 23 6 6 Interrupts The SUPC has the following interrupt sources which are either synchronous or asynchronous wake up sources VDDCORE Voltage Ready VCORERDY asynchronous Aut...

Page 289: ...er brown out detections operate asynchronously from the peripheral bus As a consequence the BOD33 Enable bit BOD33 ENABLE need synchronization when written The Write Synchronization of the Enable bit...

Page 290: ...4 0x10 BOD33 7 0 RUNBKUP RUNSTDBY STDBYCFG ACTION 1 0 HYST ENABLE 0x11 15 8 PSEL 3 0 VMON ACTCFG 0x12 23 16 LEVEL 5 0 0x13 31 24 BKUPLEVEL 5 0 0x14 0x17 Reserved 0x18 VREG 7 0 RUNSTDBY STDBYPL0 SEL EN...

Page 291: ...al Access Controller PAC PAC Write protection is denoted by the PAC Write Protection property in each individual register description Refer to Register Access Protection for details Some registers req...

Page 292: ...Bit 10 VCORERDY VDDCORE Voltage Ready Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the VDDCORE Ready Interrupt Enable bit which disables the VDDCORE Ready...

Page 293: ...lue Description 0 The BOD33 Synchronization Ready interrupt is disabled 1 The BOD33 Synchronization Ready interrupt is enabled and an interrupt request will be generated when the BOD33 Synchronization...

Page 294: ...0 Bit 10 VCORERDY VDDCORE Voltage Ready Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will set the VDDCORE Ready Interrupt Enable bit which enables the VDDCORE Ready...

Page 295: ...terrupt Value Description 0 The BOD33 Synchronization Ready interrupt is disabled 1 The BOD33 Synchronization Ready interrupt is enabled and an interrupt request will be generated when the BOD33 Synch...

Page 296: ...his bit has no effect Writing a 1 to this bit clears the VCORERDY interrupt flag Bit 9 APWSRDY Automatic Power Switch Ready This flag is cleared by writing a 1 to it This flag is set on a zero to one...

Page 297: ...set on a zero to one transition of the BOD33 Detection bit in the Status register STATUS BOD33DET and will generate an interrupt request if INTENSET BOD33DET 1 Writing a 0 to this bit has no effect W...

Page 298: ...ry Backup Power Switch Value Description 0 the backup domain is supplied by VDD 1 the backup domain is supplied by VBAT Bit 10 VCORERDY VDDCORE Voltage Ready Value Description 0 the VDDCORE voltage is...

Page 299: ...synchronization is ongoing 1 BOD33 synchronization is complete Bit 1 BOD33DET BOD33 Detection Value Description 0 No BOD33 detection 1 BOD33 has detected that the I O power supply is going below the B...

Page 300: ...AT or in Backup Sleep Mode These bits set the triggering voltage threshold for the BOD33 when the BOD33 monitors VBAT or in backup sleep mode This bit field is not synchronized Bits 21 16 LEVEL 5 0 BO...

Page 301: ...by mode 1 The BOD33 monitors the VBAT power pin in active and standby mode Bit 8 ACTCFG BOD33 Configuration in Active Sleep Mode This bit is not synchronized Value Description 0 In active mode the BOD...

Page 302: ...tart up This bit field is not synchronized Value Name Description 0x0 NONE No action 0x1 RESET The BOD33 generates a reset 0x2 INT The BOD33 generates an interrupt 0x3 BKUP The BOD33 puts the device i...

Page 303: ...g in s If VSPER 0 the period between two voltage steps is 1 s Bits 19 16 VSVSTEP 3 0 Voltage Scaling Voltage Step This field sets the voltage step height when the VDDCORE voltage is changing to reach...

Page 304: ...e the voltage regulator remains in the current performance level 1 In Standby sleep mode the voltage regulator is used in PL0 Bit 2 SEL Voltage Regulator Selection This bit is loaded from NVM User Row...

Page 305: ...reference typical value 0x2 2 048V voltage reference typical value 0x3 4 096V voltage reference typical value Others Reserved Bit 7 ONDEMAND On Demand Control The On Demand operation mode allows to en...

Page 306: ...pheral is requesting it If VREF ONDEMAND 0 the voltage reference will always be running in standby sleep mode Bit 2 VREFOE Voltage Reference Output Enable Value Description 0 The Voltage Reference out...

Page 307: ...in Power Supply Bit 2 WAKEEN Wake Enable Value Description 0 The device is not woken up when switched from battery backup power to Main Power 1 The device is woken up when switched from battery backup...

Page 308: ...L 1 0 RTC Toggle Output Value Description 0 The output will not toggle on RTC event 1 The output will toggle on RTC event Bits 17 16 SET 1 0 Set Output Writing a 0 to a bit has no effect Writing a 1 t...

Page 309: ...Value Description 0 The output is not enabled 1 The output is enabled and driven by the SUPC Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 309...

Page 310: ...logical low level on the input pin or when the backup I O is not enabled These bits are set when the corresponding backup I O pin detects a logical high level on the input pin when the backup I O is...

Page 311: ...oo early or too late a system reset will be issued Compared to the normal mode this can also catch situations where a code error causes the WDT to be cleared frequently When enabled the WDT will run i...

Page 312: ...ed Links PM Power Manager on page 188 24 5 3 Clocks The WDT bus clock CLK_WDT_APB can be enabled and disabled masked in the Main Clock module MCLK A 1KHz oscillator clock CLK_WDT_OSC is required to cl...

Page 313: ...pt Flag Status and Clear INTFLAG register Optional write protection by the Peripheral Access Controller PAC is denoted by the PAC Write Protection property in each individual register description PAC...

Page 314: ...n the Configuration register CONFIG WINDOW must be defined Enable protection is denoted by the Enable Protected property in the register description 24 6 2 2 Configurable Reset Values After a Power on...

Page 315: ...curs The Normal mode operation is illustrated in the figure Normal Mode Operation Figure 24 2 Normal Mode Operation t ms WDT Count 5 10 15 20 25 30 35 PER 3 0 1 Timely WDT Clear TOWDT WDT Timeout Syst...

Page 316: ...to the corresponding bit in the Interrupt Enable Set INTENSET register and disabled by writing a 1 to the corresponding bit in the Interrupt Enable Clear INTENCLR register An interrupt request is gene...

Page 317: ...24 6 8 1 Always On Mode The Always On mode is enabled by setting the Always On bit in the Control A register CTRLA ALWAYSON 1 When the Always On mode is enabled the WDT runs continuously regardless o...

Page 318: ...ut period the watchdog time out system reset is generated prior to the Early Warning interrupt Consequently the Early Warning interrupt will never be generated In window mode the Early Warning interru...

Page 319: ...ly Some registers are optionally write protected by the Peripheral Access Controller PAC Optional PAC write protection is denoted by the PAC Write Protection property in each individual register descr...

Page 320: ...enabled and can only be disabled by a power on reset POR Bit 2 WEN Watchdog Timer Window Mode Enable This bit enables Window mode It can only be written if the peripheral is disabled unless CTRLA ALW...

Page 321: ...Value Description 0 The WDT is disabled 1 The WDT is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 321...

Page 322: ...k cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 cloc...

Page 323: ...cles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles 0xC 0xF Reserve...

Page 324: ...d the generation of the Early Warning interrupt These bits are loaded from NVM User Row at startup Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x...

Page 325: ...roperty PAC Write Protection Bit 7 6 5 4 3 2 1 0 EW Access R W Reset 0 Bit 0 EW Early Warning Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit clears the Early Warning In...

Page 326: ...Property PAC Write Protection Bit 7 6 5 4 3 2 1 0 EW Access R W Reset 0 Bit 0 EW Early Warning Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit sets the Early Warning Int...

Page 327: ...ing This flag is cleared by writing a 1 to it This flag is set when an Early Warning interrupt occurs as defined by the EWOFFSET bit group in EWCTRL Writing a 0 to this bit has no effect Writing a 1 t...

Page 328: ...ter is complete 1 Write synchronization of the CLEAR register is ongoing Bit 3 ALWAYSON Always On Synchronization Busy Value Description 0 Write synchronization of the CTRLA ALWAYSON bit is complete 1...

Page 329: ...0 Write synchronization of the CTRLA ENABLE bit is complete 1 Write synchronization of the CTRLA ENABLE bit is ongoing Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Com...

Page 330: ...hdog time out period is restarted In Window mode any writing attempt to this register before the time out period started i e during TOWDTW will issue an immediate system Reset Writing 0xA5 during the...

Page 331: ...he clock source By this a wide range of resolutions and time out periods can be configured With a 32 768kHz clock source the minimum counter tick interval is 30 5 s and time out periods can range up t...

Page 332: ...lock Diagram Mode 1 16 Bit Counter CLK_RTC_OSC CLK_RTC_CNT OSC32KCTRL PRESCALER COMPn PER COUNT 0x0000 Periodic Events CMPn OVF Figure 25 3 RTC Block Diagram Mode 2 Clock Calendar C LK_RTC_CNT CLK_RTC...

Page 333: ...ripheral other parts of the system must be configured correctly as described below 25 5 1 I O Lines Not applicable 25 5 2 Power Management The RTC will continue to operate in any sleep mode where the...

Page 334: ...r on page 432 25 5 5 Interrupts The interrupt request line is connected to the Interrupt Controller Using the RTC interrupt requires the Interrupt Controller to be configured first Related Links Neste...

Page 335: ...aler bits in the Control A register CTRLA PRESCALER Clear on Match bit in the Control A register CTRLA MATCHCLR Clock Representation bit in the Control A register CTRLA CLKREP The following registers...

Page 336: ...h COMP0 occurs This allows the RTC to generate periodic interrupts or events with longer periods than the prescaler events Note that when CTRLA MATCHCLR is 1 INTFLAG CMP0 and INTFLAG OVF will both be...

Page 337: ...A register CTRLA MATCHCLR is set the counter is cleared on the next counter cycle when an alarm match with ALARM0 occurs This allows the RTC to generate periodic interrupts or events with longer perio...

Page 338: ...nding bit in the prescaler has toggled Refer to Periodic Intervals for details Setting the Event Output bit in the Event Control Register EVCTRL xxxEO 1 enables the corresponding output event Writing...

Page 339: ...A CLOCKSYNC is 1 The Timestamp Value register TIMESTAMP Required write synchronization is denoted by the Write Synchronized property in the register description Required read synchronization is denote...

Page 340: ...f the periodic events from the prescaler When the correction is applied at the end of the correction cycle period the interval between the previous periodic event and the next occurrence may also be s...

Page 341: ...more details Synchronous versus asynchronous stability debouncing is configured by the Debounce Asynchronous Enable bit in the Control B register CTRLB DEBASYNC Synchronous CTRLB DEBASYNC 0 INn is sy...

Page 342: ...LK_RTC CLK_RTC_DEB IN OUT NE NE PE TAMLVL 1 PE NE PE Whenever an edge is detected input must be stable for 4 consecutive CLK_RTC_DEB in order for edge to be considered valid CLK_RTC CLK_RTC_DEB IN NE...

Page 343: ...n with Majority Debouncing 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 CLK_RTC CLK_RTC_DEB IN IN shift 0 IN shift 1 IN shift 2 MAJORITY3 OUT CLK_RTC CLK_RTC_DEB IN IN shift 0 IN shift 1 IN shift 2 MAJORIT...

Page 344: ...I O pins must also be configured to correctly route the signal to the external pins Select the frequency of the output signal by configuring the RTC Active Layer Frequency field in the Control B regi...

Page 345: ...0 0x0B 15 8 OVF TAMPER CMP0 0x0C INTFLAG 7 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 0x0D 15 8 OVF TAMPER CMP0 0x0E DBGCTRL 7 0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7 0 COMP0 COUNT FREQCORR ENABLE SWRST...

Page 346: ...3 16 0x6B 31 24 TAMPEVT 0x6C 0x7F Reserved 0x80 BKUP0 7 0 BKUP 7 0 0x81 15 8 BKUP 15 8 0x82 23 16 BKUP 23 16 0x83 31 24 BKUP 31 24 0x84 BKUP1 7 0 BKUP 7 0 0x85 15 8 BKUP 15 8 0x86 23 16 BKUP 23 16 0x8...

Page 347: ...s of a 16 bit register can be accessed directly Some registers require synchronization when read and or written Synchronization is denoted by the Read Synchronized and or Write Synchronized property i...

Page 348: ...Tamper Enable Only GP registers enabled by the CTRLB GPnEN bits are affected This bit can be written only when the peripheral is disabled This bit is not synchronized Bit 13 BKTRST GP Registers Reset...

Page 349: ...ared on a Compare Alarm 0 match Bits 3 2 MODE 1 0 Operating Mode This bit group defines the operating mode of the RTC This bit is not synchronized Value Name Description 0x0 COUNT32 Mode 0 32 bit coun...

Page 350: ...precedence meaning that all other writes in the same write operation will be discarded Due to synchronization there is a delay between writing CTRLA SWRST and until the reset is complete CTRLA SWRST...

Page 351: ...on 0x0 DIV2 CLK_RTC_OUT CLK_RTC 2 0x1 DIV4 CLK_RTC_OUT CLK_RTC 4 0x2 DIV8 CLK_RTC_OUT CLK_RTC 8 0x3 DIV16 CLK_RTC_OUT CLK_RTC 16 0x4 DIV32 CLK_RTC_OUT CLK_RTC 32 0x5 DIV64 CLK_RTC_OUT CLK_RTC 64 0x6 D...

Page 352: ...tput is disabled 1 The RTC active layer output is enabled Bit 5 DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously 1 The tamper input debounce...

Page 353: ...Value Description 0 Tamper event input is disabled and incoming events will be ignored 1 Tamper event input is enabled and incoming events will capture the COUNT value Bit 15 OVFEO Overflow Event Out...

Page 354: ...r every compare match Bits 7 0 PEREOn Periodic Interval n Event Output Enable n 7 0 Value Description 0 Periodic Interval n event is disabled and will not be generated 1 Periodic Interval n event is e...

Page 355: ...ch disables the Overflow interrupt Value Description 0 The Overflow interrupt is disabled 1 The Overflow interrupt is enabled Bit 14 TAMPER Tamper Interrupt Enable Writing a 0 to this bit has no effec...

Page 356: ...pt Enable bit which disables the Periodic Interval n interrupt Value Description 0 Periodic Interval n interrupt is disabled 1 Periodic Interval n interrupt is enabled Atmel SAM L22G L22J L22N DATASHE...

Page 357: ...ich enables the Overflow interrupt Value Description 0 The Overflow interrupt is disabled 1 The Overflow interrupt is enabled Bit 14 TAMPER Tamper Interrupt Enable Writing a 0 to this bit has no effec...

Page 358: ...pt Enable bit which enables the Periodic Interval n interrupt Value Description 0 Periodic Interval n interrupt is disabled 1 Periodic Interval n interrupt is enabled Atmel SAM L22G L22J L22N DATASHEE...

Page 359: ...lag Bit 14 TAMPER Tamper event This flag is set after a damper condition occurs and an interrupt request will be generated if INTENCLR TAMPER INTENSET TAMPER is 1 Writing a 0 to this bit has no effect...

Page 360: ...set by a software reset This bit controls the functionality when the CPU is halted by an external debugger Value Description 0 The RTC is halted when the CPU is halted by an external debugger 1 The RT...

Page 361: ...te synchronization for GPn register is complete 1 Write synchronization for GPn register is ongoing Bit 15 COUNTSYNC Count Read Sync Enable Synchronization Busy Status Value Description 0 Write synchr...

Page 362: ...or FREQCORR register is ongoing Bit 1 ENABLE Enable Synchronization Busy Status Value Description 0 Read write synchronization for CTRLA ENABLE bit is complete 1 Read write synchronization for CTRLA E...

Page 363: ...ion value is positive i e frequency will be decreased 1 The correction value is negative i e frequency will be increased Bits 5 0 VALUE 5 0 Correction Value These bits define the amount of correction...

Page 364: ...0 19 18 17 16 COUNT 23 16 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2...

Page 365: ...OMP 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 COMP 31 0 Compare Value The 32...

Page 366: ...ess R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP 7 0 Access R W R W R W R...

Page 367: ...its 32 28 DEBNCn Debounce Enable n Value Description 0 Debouncing is disabled for Tamper input INn 1 Debouncing is enabled for Tamper input INn Bits 24 20 TAMLVLn Tamper Level Select n Value Descripti...

Page 368: ...ription 0x0 OFF Off Disabled 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare INn to OUT When a mismatch occurs capture timestamp and set Tamper fla...

Page 369: ...TURE Capture timestamp and set Tamper flag 0x3 ACTL Compare INn to OUT When a mismatch occurs capture timestamp and set Tamper flag Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_D...

Page 370: ...O RO RO Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT 15 8 Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT 7 0 Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0...

Page 371: ...to this bit has no effect Writing a 1 to this bit clears the tamper detection bit Value Description 0 A tamper input event has not been detected 1 A tamper input event has been detected Bits 4 0 TAMP...

Page 372: ...ess R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BKUP 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BKUP 7 0 Access R W R W R...

Page 373: ...TAMPER CMP1 CMP0 0x0C INTFLAG 7 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 0x0D 15 8 OVF TAMPER CMP1 CMP0 0x0E DBGCTRL 7 0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7 0 COMP1 COMP0 PER COUNT FREQCORR ENABLE...

Page 374: ...16 BKUP 23 16 0x83 31 24 BKUP 31 24 0x84 BKUP1 7 0 BKUP 7 0 0x85 15 8 BKUP 15 8 0x86 23 16 BKUP 23 16 0x87 31 24 BKUP 31 24 0x88 BKUP2 7 0 BKUP 7 0 0x89 15 8 BKUP 15 8 0x8A 23 16 BKUP 23 16 0x8B 31 24...

Page 375: ...tly Some registers require synchronization when read and or written Synchronization is denoted by the Read Synchronized and or Write Synchronized property in each individual register description Optio...

Page 376: ...enabled by the CTRLB GPnEN bits are affected This bit can be written only when the peripheral is disabled This bit is not synchronized Value Description 0 GPn registers will not reset when a tamper co...

Page 377: ...Mode 2 Clock calendar 0x3 Reserved Bit 1 ENABLE Enable Due to synchronization there is delay from writing CTRLA ENABLE until the peripheral is enabled disabled The value written to CTRLA ENABLE will r...

Page 378: ...il the reset is complete CTRLA SWRST will be cleared when the reset is complete Value Description 0 There is not reset operation ongoing 1 The reset operation is ongoing Atmel SAM L22G L22J L22N DATAS...

Page 379: ...ion 0x0 DIV2 CLK_RTC_OUT CLK_RTC 2 0x1 DIV4 CLK_RTC_OUT CLK_RTC 4 0x2 DIV8 CLK_RTC_OUT CLK_RTC 8 0x3 DIV16 CLK_RTC_OUT CLK_RTC 16 0x4 DIV32 CLK_RTC_OUT CLK_RTC 32 0x5 DIV64 CLK_RTC_OUT CLK_RTC 64 0x6...

Page 380: ...tput is disabled 1 The RTC active layer output is enabled Bit 5 DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously 1 The tamper input debounce...

Page 381: ...Input Enable Value Description 0 Tamper event input is disabled and incoming events will be ignored 1 Tamper event input is enabled and incoming events will capture the CLOCK value Bit 15 OVFEO Overf...

Page 382: ...is disabled and will not be generated 1 Compare n event is enabled and will be generated for every compare match Bits 7 0 PEREOn Periodic Interval n Event Output Enable n 7 0 Value Description 0 Peri...

Page 383: ...low interrupt is disabled 1 The Overflow interrupt is enabled Bit 14 TAMPER Tamper Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the Tamper Interrupt Enable...

Page 384: ...alue Description 0 Periodic Interval n interrupt is disabled 1 Periodic Interval n interrupt is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 38...

Page 385: ...flow interrupt is disabled 1 The Overflow interrupt is enabled Bit 14 TAMPER Tamper Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will set the Tamper Interrupt Enable...

Page 386: ...alue Description 0 Periodic Interval n interrupt is disabled 1 Periodic Interval n interrupt is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 38...

Page 387: ...t flag Bit 14 TAMPER Tamper This flag is set after a tamper condition occurs and an interrupt request will be generated if INTENCLR TAMPER INTENSET TAMPER is one Writing a 0 to this bit has no effect...

Page 388: ...eset by a software reset This bit controls the functionality when the CPU is halted by an external debugger Value Description 0 The RTC is halted when the CPU is halted by an external debugger 1 The R...

Page 389: ...iption 0 Write synchronization for CTRLA COUNTSYNC bit is complete 1 Write synchronization for CTRLA COUNTSYNC bit is ongoing Bits 6 5 COMPn Compare n Synchronization Busy Status n 1 0 Value Descripti...

Page 390: ...or FREQCORR register is ongoing Bit 1 ENABLE Enable Synchronization Busy Status Value Description 0 Read write synchronization for CTRLA ENABLE bit is complete 1 Read write synchronization for CTRLA E...

Page 391: ...ion value is positive i e frequency will be decreased 1 The correction value is negative i e frequency will be increased Bits 5 0 VALUE 5 0 Correction Value These bits define the amount of correction...

Page 392: ...COUNT 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 COUNT 15 0 Counter Value T...

Page 393: ...5 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 PER 15 0 Counter Period These bits d...

Page 394: ...7 6 5 4 3 2 1 0 COMP 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 COMP 15 0 Compare Value The 16 bit value of COMP0 is continuously compared with the 16 bit COUNT value W...

Page 395: ...0 Bit 7 6 5 4 3 2 1 0 COMP 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 COMP 15 0 Compare Value The 16 bit value of COMPn is continuously compared with the 16 bit COUNT...

Page 396: ...ess R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP 7 0 Access R W R W R W R...

Page 397: ...its 32 28 DEBNCn Debounce Enable n Value Description 0 Debouncing is disabled for Tamper input INn 1 Debouncing is enabled for Tamper input INn Bits 24 20 TAMLVLn Tamper Level Select n Value Descripti...

Page 398: ...ription 0x0 OFF Off Disabled 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare INn to OUT When a mismatch occurs capture timestamp and set Tamper fla...

Page 399: ...TURE Capture timestamp and set Tamper flag 0x3 ACTL Compare INn to OUT When a mismatch occurs capture timestamp and set Tamper flag Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_D...

Page 400: ...12 11 10 9 8 COUNT 15 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT 7 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15 0 COUNT 15 0 Count Timestamp Value The 16 bit v...

Page 401: ...0 to this bit has no effect Writing a 1 to this bit clears the tamper detection bit Value Description 0 A tamper input event has not been detected 1 A tamper input event has been detected Bits 4 0 TAM...

Page 402: ...ess R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BKUP 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BKUP 7 0 Access R W R W R...

Page 403: ...PER5 PER4 PER3 PER2 PER1 PER0 0x0D 15 8 OVF TAMPER ALARM0 0x0E DBGCTRL 7 0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7 0 ALARM0 COUNT FREQCORR ENABLE SWRST 0x11 15 8 CLOCKSYNC MASK0 0x12 23 16 GP1 GP0 0x13...

Page 404: ...0x69 15 8 0x6A 23 16 0x6B 31 24 TAMPEVT 0x6C 0x7F Reserved 0x80 BKUP0 7 0 BKUP 7 0 0x81 15 8 BKUP 15 8 0x82 23 16 BKUP 23 16 0x83 31 24 BKUP 31 24 0x84 BKUP1 7 0 BKUP 7 0 0x85 15 8 BKUP 15 8 0x86 23 1...

Page 405: ...lves of a 16 bit register can be accessed directly Some registers require synchronization when read and or written Synchronization is denoted by the Read Synchronized and or Write Synchronized propert...

Page 406: ...rs Reset On Tamper Enable Only GP registers enabled by the CTRLB GPnEN bits are affected This bit can be written only when the peripheral is disabled This bit is not synchronized Bit 13 BKTRST GP Regi...

Page 407: ...n a Compare Alarm 0 match Bit 6 CLKREP Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value CLOCK register This bit can be written only...

Page 408: ...BGCTRL to their initial state and the RTC will be disabled Writing a 1 to CTRLA SWRST will always take precedence meaning that all other writes in the same write operation will be discarded Due to syn...

Page 409: ...DIV2 CLK_RTC_OUT CLK_RTC 2 0x1 DIV4 CLK_RTC_OUT CLK_RTC 4 0x2 DIV8 CLK_RTC_OUT CLK_RTC 8 0x3 DIV16 CLK_RTC_OUT CLK_RTC 16 0x4 DIV32 CLK_RTC_OUT CLK_RTC 32 0x5 DIV64 CLK_RTC_OUT CLK_RTC 64 0x6 DIV128...

Page 410: ...C Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously 1 The tamper input debouncers operate asynchronously Bit 4 DEBMAJ Debouncer Majority Enable Value...

Page 411: ...ble Value Description 0 Tamper event input is disabled and incoming events will be ignored 1 Tamper event input is enabled and all incoming events will capture the CLOCK value Bit 15 OVFEO Overflow Ev...

Page 412: ...every compare match Bits 7 0 PEREOn Periodic Interval n Event Output Enable n 7 0 Value Description 0 Periodic Interval n event is disabled and will not be generated 1 Periodic Interval n event is ena...

Page 413: ...it which disables the Overflow interrupt Value Description 0 The Overflow interrupt is disabled 1 The Overflow interrupt is enabled Bit 14 TAMPER Tamper Interrupt Enable Bit 8 ALARM0 Alarm 0 Interrupt...

Page 414: ...The Overflow interrupt is disabled 1 The Overflow interrupt is enabled Bit 14 TAMPER Tamper Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will set the Tamper Interrup...

Page 415: ...alue Description 0 Periodic Interval n interrupt is disabled 1 Periodic Interval n interrupt is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 41...

Page 416: ...nterrupt flag Bit 14 TAMPER Tamper This flag is set after a tamper condition occurs and an interrupt request will be generated if INTENCLR TAMPER INTENSET TAMPER is 1 Writing a 0 to this bit has no ef...

Page 417: ...eset by a software reset This bit controls the functionality when the CPU is halted by an external debugger Value Description 0 The RTC is halted when the CPU is halted by an external debugger 1 The R...

Page 418: ...iption 0 Write synchronization for GPn register is complete 1 Write synchronization for GPn register is ongoing Bit 15 CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status Value Description 0...

Page 419: ...ead write synchronization for FREQCORR register is complete 1 Read write synchronization for FREQCORR register is ongoing Bit 1 ENABLE Enable Synchronization Busy Status Value Description 0 Read write...

Page 420: ...ion value is positive i e frequency will be decreased 1 The correction value is negative i e frequency will be increased Bits 5 0 VALUE 5 0 Correction Value These bits define the amount of correction...

Page 421: ...1 0 MINUTE 1 0 SECOND 5 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 26 YEAR 5 0 Year The year offset with respect to the reference year defined in software The year is cons...

Page 422: ...Bits 5 0 SECOND 5 0 Second 0 59 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 422...

Page 423: ...0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR 3 0 MINUTE 5 2 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE 1 0 SECOND 5 0 Access R W R W R W R W R W R W R W R W Reset...

Page 424: ...ALARM are valid Value Name Description 0x0 OFF Alarm Disabled 0x1 SS Match seconds only 0x2 MMSS Match seconds and minutes only 0x3 HHMMSS Match seconds minutes and hours only 0x4 DDHHMMSS Match secon...

Page 425: ...ess R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP 7 0 Access R W R W R W R...

Page 426: ...its 32 28 DEBNCn Debounce Enable n Value Description 0 Debouncing is disabled for Tamper input INn 1 Debouncing is enabled for Tamper input INn Bits 24 20 TAMLVLn Tamper Level Select n Value Descripti...

Page 427: ...ription 0x0 OFF Off Disabled 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare INn to OUT When a mismatch occurs capture timestamp and set Tamper fla...

Page 428: ...TURE Capture timestamp and set Tamper flag 0x3 ACTL Compare INn to OUT When a mismatch occurs capture timestamp and set Tamper flag Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_D...

Page 429: ...y the TIMESTAMP when a tamper condition occurs Bits 28 25 MONTH 3 0 Month The month value is captured by the TIMESTAMP when a tamper condition occurs Bits 25 21 DAY 4 0 Day The day value is captured b...

Page 430: ...0 to this bit has no effect Writing a 1 to this bit clears the tamper detection bit Value Description 0 A tamper input event has not been detected 1 A tamper input event has been detected Bits 4 0 TAM...

Page 431: ...ess R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BKUP 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BKUP 7 0 Access R W R W R...

Page 432: ...active channel to SRAM and grant the higher prioritized channel to start transfer as the new active channel Once a DMA channel is done with its transfer interrupts and events can be generated optiona...

Page 433: ...event inputs One event input for each of the 4 least significant DMA channels Can be selected to trigger normal transfers periodic transfers or conditional transfers Can be selected to suspend or res...

Page 434: ...ow 26 5 1 I O Lines Not applicable 26 5 2 Power Management The DMAC will continue to operate in any sleep mode where the selected source clock is running The DMAC s interrupts can be used to wake up t...

Page 435: ...d optionally by the Peripheral Access Controller PAC except the following registers Interrupt Pending register INTPEND Channel ID register CHID Channel Interrupt Flag Status and Clear register CHINTFL...

Page 436: ...el to the arbiter If there are several DMA channels with pending transfer requests the arbiter chooses which channel is granted access to become the active channel The DMA channel granted access as th...

Page 437: ...DMA channel and the corresponding first transfer descriptor must be configured as outlined by the following steps DMA channel configurations The channel number of the DMA channel to configure must be...

Page 438: ...ransfer Descriptors Together with the channel configurations the transfer descriptors decides how a block transfer should be executed Before a DMA channel is enabled CHCTRLA ENABLE is written to one a...

Page 439: ...share memory section BASEADDR WRBADDR The benefit of having them in two separate sections is that the same transaction for a channel can be repeated without having to modify the first transfer descri...

Page 440: ...annel Number Level Enable Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Priority Levels When a cha...

Page 441: ...ter PRICTRL0 LVLPRIx for the corresponding priority level Figure 26 6 Dynamic Round Robin Priority Scheduling Channel N Channel N Channel 0 Channel x Channel x 1 Channel x last acknowledge request Cha...

Page 442: ...ended or disabled depending on the configuration in the Block Action bit group in the Block Transfer Control register BTCTRL BLOCKACT If the transaction has further block transfers pending DESCADDR wi...

Page 443: ...s the corresponding Channel Busy status flag is set in Channel Status register CHSTATUS BUSY When the trigger action is complete the Channel Busy status flag is cleared All channel busy status flags a...

Page 444: ...BTCTRL STEPSEL 1 and BTCTRL STEPSIZE 0x1 As the destination address for both channels are peripherals destination incrementation is disabled BTCTRL DSTINC 0 Figure 26 8 Source Address Increment SRC D...

Page 445: ...ter CHINTFLAG SUSP is set and the Channel Fetch Error bit in the Channel Status register CHSTATUS FERR is set If enabled the optional suspend interrupt is generated 26 6 3 Additional Features 26 6 3 1...

Page 446: ...he DESCADDR location of the descriptor from the List Optionally clear the Suspend block action Set the descriptor VALID bit to 1 7 Go to step 4 if needed Adding a Descriptor Between Existing Descripto...

Page 447: ...t field of the Channel Control B register CHCTRLB CMD If the channel is already suspended the channel operation resumes from where it previously stopped when the Resume command is detected When the Re...

Page 448: ...r Conditional Transfer on Strobe The event input is used to trigger a transfer on peripherals with pending transfer requests This event action is intended to be used with peripheral triggers e g for t...

Page 449: ...nding Channels register is set PENDCH PENDCHn and the event is acknowledged A software trigger will now trigger a transfer The figure below shows an example where conditional event is enabled with per...

Page 450: ...ntil the next block suspend detection When the block transfer is completed the channel continues the operation not suspended and the event is acknowledged 26 6 3 5 Event Output Selection Event output...

Page 451: ...ed CTRL DMAENABLE 0 when the entire DMAC module is disabled 26 6 3 7 CRC Operation A cyclic redundancy check CRC is an error detection technique used to find errors in data It is commonly used to dete...

Page 452: ...is selected by writing to the CRC Polynomial Type bit in the CRC Control register CRCCTRL CRCPOLY the default is CRC 16 The CRC engine operates on byte only When the DMA is used as data source for th...

Page 453: ...during a burst transfer or that an invalid descriptor has been fetched Refer to Error Handling for details Channel Suspend SUSP Indicates that the corresponding channel has been suspended Refer to Ch...

Page 454: ...e Operation RESUME resume a suspended channel operation Skip Next Block Suspend Action SSKIP skip the next block suspend transfer condition Setting the Channel Control B Event Input Enable bit CHCTRLB...

Page 455: ...8 0x12 23 16 0x13 31 24 0x14 PRICTRL0 7 0 RRLVLEN0 LVLPRI0 3 0 0x15 15 8 RRLVLEN1 LVLPRI1 3 0 0x16 23 16 RRLVLEN2 LVLPRI2 3 0 0x17 31 24 RRLVLEN3 LVLPRI3 3 0 0x18 0x1F Reserved 0x20 INTPEND 7 0 ID 3 0...

Page 456: ...7 0 SUSP TCMPL TERR 0x4F CHSTATUS 7 0 FERR BUSY PEND 26 8 Register Description Registers can be 8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition the 8 bit quarters and 16...

Page 457: ...riting a 0 to this bit will disable the DMA module When writing a 0 during an ongoing transfer the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is abor...

Page 458: ...arbiter block When cleared all requests with the corresponding level will be ignored For details on arbitration schemes refer to the Arbitration section These bits are not enable protected Value Descr...

Page 459: ...means the CRCSRC cannot be modified when the CRC operation is ongoing The lock is signaled by the CRCBUSY status bit CRC generation complete is generated and signaled from the selected source when use...

Page 460: ...30 0x3F CHN DMA channel 31 Bits 3 2 CRCPOLY 1 0 CRC Polynomial Type These bits define the size of the data transfer for each bus access when the CRC is used with I O interface as shown in the table be...

Page 461: ...Value Name Description 0x3 Reserved Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 461...

Page 462: ...0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCDATAIN 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCDATAIN 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0...

Page 463: ...ration is ongoing CRCCHKSUM will contain the actual content Name CRCCHKSUM Offset 0x08 Reset 0x00000000 Property PAC Write Protection Enable Protected Bit 31 30 29 28 27 26 25 24 CRCCHKSUM 31 24 Acces...

Page 464: ...ittle endian to the data the final result in the checksum register will be zero See the description of CRCCHKSUM to read out different versions of the checksum Bit 0 CRCBUSY CRC Module Busy This flag...

Page 465: ...et by a software reset This bit controls the functionality when the CPU is halted by an external debugger Value Description 0 The DMAC is halted when the CPU is halted by an external debugger 1 The DM...

Page 466: ...ritical Latency Bits 3 2 FQOS 1 0 Fetch Quality of Service These bits define the memory priority access during the fetch operation FQOS 1 0 Name Description 0x0 DISABLE Background no sensitive operati...

Page 467: ...W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 SWTRIGn Channel n Software Trigger n 15 0 This bit is cleared when the Channel Pending bit in the Channel Status register CHSTATUS PEND for th...

Page 468: ...th level 3 priority 1 Round robin arbitration scheme for channels with level 3 priority Bits 27 24 LVLPRI3 3 0 Level 3 Channel Priority Number When round robin arbitration is enabled PRICTRL0 RRLVLEN3...

Page 469: ...s register holds the channel number of the last DMA channel being granted access as the active channel with priority level 1 When static arbitration is enabled PRICTRL0 RRLVLEN1 0 for priority level 1...

Page 470: ...pend interrupt Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the Channel ID ID Suspend interrupt flag Bit 9 TCMPL Transfer Complete This bit will read 1 when the channel sel...

Page 471: ...corresponding channel interrupt sources When no pending channels interrupts are available these bits will always return zero value when read When the bits are written indirect access to the correspon...

Page 472: ...0 0 0 0 Bit 7 6 5 4 3 2 1 0 CHINT7 CHINT6 CHINT5 CHINT4 CHINT3 CHINT2 CHINT1 CHINT0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15 0 CHINTn Channel n Pending Interrupt n 15 0 This bit is set wh...

Page 473: ...0 0 Bit 7 6 5 4 3 2 1 0 BUSYCH7 BUSYCH6 BUSYCH5 BUSYCH4 BUSYCH3 BUSYCH2 BUSYCH1 BUSYCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15 0 BUSYCHn Busy Channel n x 15 0 This bit is cleared when th...

Page 474: ...NDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15 0 PENDCHn Pending Channel n n 15 0 This bit is cleared when trigger execution defined by channel trigger acti...

Page 475: ...rbiter grants a new channel access The value is valid only when the active channel active busy flag ABUSY is set Bit 15 ABUSY Active Channel Busy This bit is cleared when the active transfer count is...

Page 476: ...W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 BASEADDR 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 BASEADDR 7 0 Access R W R W...

Page 477: ...s R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 WRBADDR 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WRBADDR 7 0 Access R W R...

Page 478: ...et 0 0 0 0 Bits 3 0 ID 3 0 Channel ID These bits define the channel number that will be affected by the channel registers CH Before reading or writing a channel register the channel ID bit group must...

Page 479: ...nternal data transfer buffer is empty and the DMA transfer is aborted The internal data transfer buffer will be empty once the ongoing burst transfer is completed Writing a 1 to this bit will enable t...

Page 480: ...T 2 0 Access R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 Bits 25 24 CMD 1 0 Software Command These bits define the software commands Refer to Channel Suspend and Channel Resume and Next Suspend Sk...

Page 481: ...COM2 TX SERCOM2 TX Trigger 0x08 SERCOM3 RX SERCOM3 RX Trigger 0x09 SERCOM3 TX SERCOM3 TX Trigger 0x0A SERCOM4 RX SERCOM4 RX Trigger 0x0B SERCOM4 TX SERCOM4 TX Trigger 0c0C SERCOM5 RX SERCOM5 RX Trigge...

Page 482: ...rbitration These bits are not enable protected TRIGACT 1 0 Name Description 0x0 LVL0 Channel Priority Level 0 0x1 LVL1 Channel Priority Level 1 0x2 LVL2 Channel Priority Level 2 0x3 LVL3 Channel Prior...

Page 483: ...only for the least significant DMA channels Refer to table User Multiplexer Selection and Event Generator Selection of the Event System for details EVACT 2 0 Name Description 0x0 NOACT No action 0x1 T...

Page 484: ...Channel Suspend interrupt is enabled Bit 1 TCMPL Channel Transfer Complete Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the Channel Transfer Complete Inte...

Page 485: ...n 0 The Channel Suspend interrupt is disabled 1 The Channel Suspend interrupt is enabled Bit 1 TCMPL Channel Transfer Complete Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to thi...

Page 486: ...refer to CHCTRLB CMD For details on available event input actions refer to CHCTRLB EVACT For details on available block actions refer to BTCTRL BLOCKACT Bit 1 TCMPL Channel Transfer Complete This fla...

Page 487: ...it is cleared when the channel trigger action is completed when a bus error is detected or when the channel is disabled This bit is set when the DMA channel starts a DMA transfer Bit 0 PEND Channel Pe...

Page 488: ...8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition the 8 bit quarters and 16 bit halves of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed direc...

Page 489: ...BEATSIZE 1 2 0x2 X4 Next ADDR ADDR BEATSIZE 1 4 0x3 X8 Next ADDR ADDR BEATSIZE 1 8 0x4 X16 Next ADDR ADDR BEATSIZE 1 16 0x5 X32 Next ADDR ADDR BEATSIZE 1 32 0x6 X64 Next ADDR ADDR BEATSIZE 1 64 0x7 X...

Page 490: ...The Source Address Increment is enabled Bits 9 8 BEATSIZE 1 0 Beat Size These bits define the size of one beat A beat is the size of one data transfer bus access and the setting apply to both read and...

Page 491: ...Write Back memory will suspend the DMA channel operation when fetching the corresponding descriptor The bit is automatically cleared in the Write Back memory section when channel is aborted when an e...

Page 492: ...it group holds the 16 bit block transfer count During a transfer the internal counter value is decremented by one after each beat transfer The internal counter is written to the corresponding write ba...

Page 493: ...eset Bit 23 22 21 20 19 18 17 16 SRCADDR 23 16 Access Reset Bit 15 14 13 12 11 10 9 8 SRCADDR 15 8 Access Reset Bit 7 6 5 4 3 2 1 0 SRCADDR 7 0 Access Reset Bits 31 0 SRCADDR 31 0 Transfer Source Addr...

Page 494: ...t Bit 23 22 21 20 19 18 17 16 DSTADDR 23 16 Access Reset Bit 15 14 13 12 11 10 9 8 DSTADDR 15 8 Access Reset Bit 7 6 5 4 3 2 1 0 DSTADDR 7 0 Access Reset Bits 31 0 DSTADDR 31 0 Transfer Destination Ad...

Page 495: ...14 13 12 11 10 9 8 DESCADDR 15 8 Access Reset Bit 7 6 5 4 3 2 1 0 DESCADDR 7 0 Access Reset Bits 31 0 DESCADDR 31 0 Next Descriptor Address This bit group holds the SRAM address of the next descripto...

Page 496: ...other external interrupts but is connected to the NMI request of the CPU enabling it to interrupt any other interrupt mode 27 2 Features Up to 16 external pins plus one non maskable pin Dedicated indi...

Page 497: ...7 5 3 Clocks The EIC bus clock CLK_EIC_APB can be enabled and disabled by the Main Clock Controller the default state of CLK_EIC_APB can be found in the Peripheral Clock Masking section Some optional...

Page 498: ...r similar improper operation or data loss may result during debugging 27 5 8 Register Access Protection All registers with write access can be write protected optionally by the Peripheral Access Contr...

Page 499: ...e EIC is enabled by writing a 1 the Enable bit in the Control A register CTRLA ENABLE The EIC is disabled by writing CTRLA ENABLE to 0 The EIC is reset by setting the Software Reset bit in the Control...

Page 500: ...CLK module Figure 27 2 Interrupt Detections intreq_extint x edge detection filter intreq_extint x edge detection no filter intreq_extint x level detection filter intreq_extint x level detection no fil...

Page 501: ...CKSEL The External Interrupt flag INTFLAG EXTINT x or Non Maskable Interrupt flag NMIFLAG NMI is set when the last sampled state of the pin differs from the previously sampled state In this mode the E...

Page 502: ...f enabled 27 6 8 Sleep Mode Operation In sleep modes an EXTINTx pin can wake up the device if the corresponding condition matches the configuration in CONFIG0 CONFIG1 register and the corresponding bi...

Page 503: ...3 2 0 FILTEN2 SENSE2 2 0 0x1E 23 16 FILTEN5 SENSE5 2 0 FILTEN4 SENSE4 2 0 0x1F 31 24 FILTEN7 SENSE7 2 0 FILTEN6 SENSE6 2 0 0x20 CONFIG1 7 0 FILTEN1 SENSE1 2 0 FILTEN0 SENSE0 2 0 0x21 15 8 FILTEN3 SENS...

Page 504: ...can only be written when the module is disabled Enable protection is denoted by the Enable Protected property in each individual register description Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E S...

Page 505: ...Synchronization Busy register will be set SYNCBUSY ENABLE 1 SYNCBUSY ENABLE will be cleared when the operation is complete This bit is not Enable Protected Value Description 0 The EIC is disabled 1 Th...

Page 506: ...ated 1 The NMI edge detection is asynchronously operated Bit 3 NMIFILTEN Non Maskable Interrupt Filter Enable Value Description 0 NMI filter is disabled 1 NMI filter is enabled Bits 2 0 NMISENSE 2 0 N...

Page 507: ...it 0 NMI Non Maskable Interrupt This flag is cleared by writing a 1 to it This flag is set when the NMI pin matches the NMI sense configuration and will generate an interrupt request Writing a 0 to th...

Page 508: ...1 ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA ENABLE bit is complete 1 Write synchronization for CTRLA ENABLE bit is ongoing Bit 0 SWRST Software Res...

Page 509: ...Bit 7 6 5 4 3 2 1 0 EXTINTEO 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 EXTINTEO 15 0 External Interrupt x Event Output These bits enable the event associated with the...

Page 510: ...t 15 14 13 12 11 10 9 8 EXTINT 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 E...

Page 511: ...it 15 14 13 12 11 10 9 8 EXTINT 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 EXTINT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0...

Page 512: ...0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 EXTINT 15 0 External Interrupt x This flag is cleared by writing a 1 to it This flag is set when EXTINTx pin matches the exter...

Page 513: ...YNCH 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ASYNCH 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 ASYNCH 15 0 Asynchronous Ed...

Page 514: ...NSE1 2 0 FILTEN0 SENSE0 2 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 3 7 11 15 19 23 27 31 FILTENx Filter x Enable x 7 0 Value Description 0 Filter is disabled for EXTINT n 8...

Page 515: ...emulation area All NVM sections are memory mapped to the AHB including calibration and system configuration 32 bit APB interface for commands and control Programmable wait states for read optimization...

Page 516: ...number of wait states Refer to the Electrical Characteristics for the exact number of wait states to be used for a particular frequency range Related Links Electrical Characteristics on page 1147 28 5...

Page 517: ...NVM has a row erase granularity while the write granularity is by page In other words a single row erase will erase all four pages in the row while four write operations are used to write the complet...

Page 518: ...OTPROT fuses and the upper rows can be allocated to EEPROM as shown in the figure below The boot loader section is protected by the lock bit s corresponding to this address space and by the BOOTPROT 2...

Page 519: ...cked Table 28 1 Region Size Memory Size KB Region Size KB 256 16 128 8 64 4 32 2 To lock or unlock a region the Lock Region and Unlock Region commands are provided Writing one of these commands will t...

Page 520: ...ce directly Read data is available after the configured number of read wait states CTRLB RWS set in the NVM Controller The number of cycles data are delayed to the AHB bus is determined by the read wa...

Page 521: ...memory is to be written Procedure for Manual Page Writes CTRLB MANW 1 The row to be written to must be erased before the write command is given Write to the page buffer by addressing the NVM main addr...

Page 522: ...cal Memory Map of the device for calibration and auxiliary space address mapping The bootloader resides in the main array starting at offset zero The allocated boot loader section is write protected T...

Page 523: ...ontroller cache reduces the device power consumption and improves system performance when wait states are required Only the NVM main array address space is cached It is a direct mapped cache that impl...

Page 524: ...19 15 8 0x1A 0x1B Reserved 0x1C ADDR 7 0 ADDR 7 0 0x1D 15 8 ADDR 15 8 0x1E 23 16 ADDR 21 16 0x1F 31 24 0x20 LOCK 7 0 LOCK 7 0 0x21 15 8 LOCK 15 8 28 8 Register Description Registers can be 8 16 or 32...

Page 525: ...can only be written when the module is disabled Enable protection is denoted by the Enable Protected property in each individual register description Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E S...

Page 526: ...bus on the same cycle as an AHB bus access the AHB bus access will be given priority The command will then be executed when the NVM block and the AHB bus are idle INTFLAG READY must be 1 when the comm...

Page 527: ...location in the ADDR register 0x42 SPRM Sets the Power Reduction Mode 0x43 CPRM Clears the Power Reduction Mode 0x44 PBC Page Buffer Clear Clears the page buffer 0x46 INVALL Invalidates all cache line...

Page 528: ...Value Description 0 The cache is enabled 1 The cache is disabled Bits 17 16 READMODE 1 0 NVMCTRL Read Mode Value Name Description 0x0 NO_MISS_PENALTY The NVM Controller cache system does not insert wa...

Page 529: ...de when entering sleep NVM block exits low power mode upon first access 0x1 WAKEUPINSTANT NVM block enters low power mode when entering sleep NVM block exits low power mode when exiting sleep 0x2 Rese...

Page 530: ...20 RWWEEP 11 0 Read While Write EEPROM emulation area Pages Indicates the number of pages in the RWW EEPROM emulation address space Bits 18 16 PSZ 2 0 Page Size Indicates the page size Not all device...

Page 531: ...ss R W R W Reset 0 0 Bit 1 ERROR Error Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit clears the ERROR interrupt enable This bit will read as the current value of the E...

Page 532: ...cess R W R W Reset 0 0 Bit 1 ERROR Error Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit sets the ERROR interrupt enable This bit will read as the current value of the E...

Page 533: ...is bit can be cleared by writing a 1 to its bit location Value Description 0 No errors have been received since the last clear 1 At least one error has occurred since the last clear Bit 0 READY NVM Re...

Page 534: ...cleared 1 Programming of at least one locked lock region has happened since this bit was last cleared Bit 2 PROGE Programming Error Status This bit can be cleared by writing a 1 to its bit location V...

Page 535: ...en entering sleep with SLEEPPRM set accordingly PRM can be cleared in three ways through AHB access to the NVM block through the command interface SPRM and CPRM or when exiting sleep with SLEEPPRM set...

Page 536: ...Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 21 0 ADDR 21 0 NVM Address ADDR drives the...

Page 537: ...R R R R Reset 0 0 0 0 0 0 0 x Bits 15 0 LOCK 15 0 Region Lock Bits In order to set or clear these bits the CMD register must be used Default state after erase will be unlocked 0x0000 Value Descriptio...

Page 538: ...atomic 8 16 or 32 bit write The PORT is connected to the high speed bus matrix through an AHB APB bridge The Pin Direction Data Output Value and Data Input Value registers may also be accessed using t...

Page 539: ...29 5 Product Dependencies In order to use this peripheral other parts of the system must be configured correctly as following 29 5 1 I O Lines The I O lines of the PORT are mapped to pins of the phys...

Page 540: ...d and disabled in the Main Clock module and the default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section in MCLK Main Clock The PORT is fed by two different clocks a CPU main...

Page 541: ...d the I O pads using analog buses However selecting an analog peripheral function for a given pin will disable the corresponding digital features of the pad 29 5 10 CPU Local Bus The CPU local bus IOB...

Page 542: ...gisters in PORT are duplicated for each PORT group with increasing base addresses The number of PORT groups may depend on the package number of pins Figure 29 3 Overview of the peripheral functions mu...

Page 543: ...2 1 Initialization After reset all standard function device I O pads are connected to the PORT with outputs tri stated and input buffers disabled even if there is no clock running However specific pin...

Page 544: ...e set in a totem pole open drain or pull configuration As pull configuration is done through the Pin Configuration register all intermediate PORT states during switching of pin direction and pin value...

Page 545: ...her than what the pin is capable of If the pin is configured for input the pin will float if no external pull is connected Note Enabling the output driver will automatically disable pull Figure 29 6 I...

Page 546: ...bles the corresponding action on input event Writing 0 to this bit disables the corresponding action on input event Note that several actions can be enabled for incoming events If several events are c...

Page 547: ...CPU through the ARM single cycle I O port IOBUS The ARM CPU through the high speed matrix and the AHB APB bridge APB EVSYS through four asynchronous input events The following priority is adopted 1 A...

Page 548: ...LR 7 0 OUTCLR 7 0 0x15 15 8 OUTCLR 15 8 0x16 23 16 OUTCLR 23 16 0x17 31 24 OUTCLR 31 24 0x18 OUTSET 7 0 OUTSET 7 0 0x19 15 8 OUTSET 15 8 0x1A 23 16 OUTSET 23 16 0x1B 31 24 OUTSET 31 24 0x1C OUTTGL 7 0...

Page 549: ...VSTR SLEWLIM ODRAIN PULLEN INEN PMUXEN 0x47 PINCFG7 7 0 DRVSTR SLEWLIM ODRAIN PULLEN INEN PMUXEN 0x48 PINCFG8 7 0 DRVSTR SLEWLIM ODRAIN PULLEN INEN PMUXEN 0x49 PINCFG9 7 0 DRVSTR SLEWLIM ODRAIN PULLEN...

Page 550: ...e 8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition the 8 bit quarters and 16 bit halves of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed dir...

Page 551: ...it 23 22 21 20 19 18 17 16 DIR 23 16 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIR 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7...

Page 552: ...s R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRCLR 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRCLR 7 0 Access R W R W...

Page 553: ...ess R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRSET 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRSET 7 0 Access R W R...

Page 554: ...3 16 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DIRTGL 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DIRTGL 7 0 Acce...

Page 555: ...15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 OUT 31 0 Port Data Output Value Fo...

Page 556: ...W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTCLR 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 OUTCLR 31 0 PORT Data Output Value Clear Writing 0 to a bit has no eff...

Page 557: ...R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTSET 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 OUTSET 31 0 PORT Data Output Value Set Writing 0 to a bit has no ef...

Page 558: ...15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OUTTGL 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 OUTTGL 31 0 PORT Data Output Val...

Page 559: ...s R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 IN 7 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31 0 IN 31 0 PORT Data Input Value These bits are cleared when the corresponding I...

Page 560: ...R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 SAMPLING 31 0 Input Sampling Mode Configures the input sampling functionality of the I O pin input samplers for pins configured as input...

Page 561: ...W W W W W Reset 0 0 0 0 0 0 0 0 Bit 31 HWSEL Half Word Select This bit selects the half word field of a 32 PORT group to be reconfigured in the atomic write operation This bit will always read as zero...

Page 562: ...on This bit determines the new value written to PINCFGy DRVSTR for all pins selected by the WRCONFIG PINMASK and WRCONFIG HWSEL bits when the WRCONFIG WRPINCFG bit is set This bit will always read as...

Page 563: ...ASK 15 0 Pin Mask for Multiple Pin Configuration These bits select the pins to be configured within the half word group selected by the WRCONFIG HWSEL bit These bits will always read as zero Value Des...

Page 564: ...R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 23 15 7 PORTEIx PORT Event Input x Enable x 3 0 Value Description 0 The event action x EVACTx will not be triggered on any incoming event 1 The event act...

Page 565: ...vent Table 29 5 PORT Event x Pin Identifier x 3 0 Value Name Description 0x0 PIN0 Event action to be executed on PIN 0 0x1 PIN1 Event action to be executed on PIN 1 0x31 PIN31 Event action to be execu...

Page 566: ...escription 0x0 A Peripheral function A selected 0x1 B Peripheral function B selected 0x2 C Peripheral function C selected 0x3 D Peripheral function D selected 0x4 E Peripheral function E selected 0x5...

Page 567: ...unction E selected 0x5 F Peripheral function F selected 0x6 G Peripheral function G selected 0x7 H Peripheral function H selected 0x8 I Peripheral function I selected 0x9 0xF Reserved Atmel SAM L22G L...

Page 568: ...input is driven to a defined logic level in the absence of external input Bit 1 INEN Input Enable This bit controls the input buffer of an I O pin configured as either an input or output Writing a zer...

Page 569: ...r IN if PINCFGn INEN is set Value Description 0 The peripheral multiplexer selection is disabled and the PORT registers control the direction and output drive value 1 The peripheral multiplexer select...

Page 570: ...eatures 8 configurable event channels where each channel can Be connected to any event generator Provide a pure asynchronous resynchronized or synchronous path 69 event generators 31 event users Confi...

Page 571: ...ock module and the default state of CLK_EVSYS_APB can be found in Peripheral Clock Masking Each EVSYS channel has a dedicated generic clock GCLK_EVSYS_CHANNEL_n These are used for event detection and...

Page 572: ...ode of operation must be selected based on the requirements of the application When using synchronous or resynchronized path the Event System includes options to transfer events to users when rising f...

Page 573: ...h There are three different ways to propagate the event from an event generator Asynchronous path Synchronous path Resynchronized path The path is decided by writing to the Path Selection bit group of...

Page 574: ...ndent Synchronous Path The maximum routing latency of an external event is one GCLK_EVSYS_CHANNEL_n clock cycle Resynchronized Path The maximum routing latency of an external event is three GCLK_EVSYS...

Page 575: ...bit in the Interrupt Enable Set INTENSET register and disabled by setting a 1 to the corresponding bit in the Interrupt Enable Clear INTENCLR register An interrupt event is generated when the interrup...

Page 576: ...isters Offset Name Bit Pos 0x00 CTRLA 7 0 SWRST 0x01 0x0B Reserved 0x0C CHSTATUS 7 0 USRRDY7 USRRDY6 USRRDY5 USRRDY4 USRRDY3 USRRDY2 USRRDY1 USRRDY0 0x0D 15 8 0x0E 23 16 CHBUSY7 CHBUSY6 CHBUSY5 CHBUSY...

Page 577: ...d 32 bit accesses are supported In addition the 8 bit quarters and 16 bit halves of a 32 bit register and the 8 bit halves of a 16 bit register can be accessed directly Optional write protection by th...

Page 578: ...t 0 SWRST Software Reset Writing 0 to this bit has no effect Writing 1 to this bit resets all registers in the EVSYS to their initial state Note Before applying a Software Reset it is recommended to d...

Page 579: ...ess R R R R R R R R Reset 0 0 0 0 0 0 0 1 Bits 23 16 CHBUSYn Channel Busy n n 7 0 This bit is cleared when channel n is idle This bit is set if an event on channel n has not been handled by all event...

Page 580: ...Reset 0 0 0 0 0 0 0 0 Bits 23 16 EVDn Event Detected Channel n Interrupt Enable n 7 0 Writing 0 to this bit has no effect Writing 1 to this bit will clear the Event Detected Channel n Interrupt Enable...

Page 581: ...eset 0 0 0 0 0 0 0 Bits 23 16 EVDn Event Detected Channel n Interrupt Enable n 7 0 Writing 0 to this bit has no effect Writing 1 to this bit will set the Event Detected Channel n Interrupt Enable bit...

Page 582: ...nd an interrupt request will be generated if INTENCLR SET EVDn is 1 When the event channel path is asynchronous the EVDn interrupt flag will not be set Writing 0 to this bit has no effect Writing 1 to...

Page 583: ...HANNEL7 CHANNEL6 CHANNEL5 CHANNEL4 CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 7 0 CHANNELn Channel n Software n 7 0 Selection Writing 0 to th...

Page 584: ...Clock On Demand Value Description 0 Generic clock for a channel is always on if the channel is configured and generic clock source is enabled 1 Generic clock is requested on demand while an event is h...

Page 585: ...SYNCHRONOUS Synchronous path 0x1 RESYNCHRONIZED Resynchronized path 0x2 ASYNCHRONOUS Asynchronous path 0x3 Reserved Bits 6 0 EVGEN 6 0 Event Generator These bits are used to choose the event generato...

Page 586: ...2 External Interrupt 12 0x1C EIC EXTINT13 External Interrupt 13 0x1D EIC EXTINT14 External Interrupt 14 0x1E EIC EXTINT15 External Interrupt 15 0x1F DMAC CH0 Channel 0 0x20 DMAC CH1 Channel 1 0x21 DMA...

Page 587: ...9 AC COMP1 Comparator 1 0x3A AC WIN0 Window 0 0x3B PTC EOC End of Conversion 0x3C PTC WCOMP Window Comparator 0x3D SLCD_FC0 Frame Counter 0 overflow 0x3E SCLD_FC1 Frame Counter 1 overflow 0x3F SLCD_FC...

Page 588: ...W R W R W R W R W Reset 0 0 0 0 0 0 Bits 5 0 CHANNEL 5 0 Channel Event Selection These bits are used to select the channel to connect to the event user Note that to select channel m the value m 1 mus...

Page 589: ...ous and resynchronized paths m 6 DMAC CH1 Channel 1 Synchronous and resynchronized paths m 7 DMAC CH2 Channel 2 Synchronous and resynchronized paths m 8 DMAC CH3 Channel 3 Synchronous and resynchroniz...

Page 590: ...onous and resynchronized paths m 21 AC COMP0 Start comparator 0 Asynchronous synchronous and resynchronized paths m 22 AC COMP1 Start comparator 1 Asynchronous synchronous and resynchronized paths m 2...

Page 591: ...RT Tracing start Asynchronous synchronous and resynchronized paths m 30 MTB STOP Tracing stop Asynchronous synchronous and resynchronized paths others Reserved Atmel SAM L22G L22J L22N DATASHEET Atmel...

Page 592: ...RCOM Inter Integrated Circuit on page 678 SERCOM USART and I2C Configurations on page 30 31 2 Features Interface for configuring into one of the following I2C Two wire serial interface SMBus compatibl...

Page 593: ...O pins to be configured using port configuration PORT From USART Block Diagram one can see that the SERCOM has four internal pads PAD 3 0 The signals from I2C SPI and USART are routed through these SE...

Page 594: ...AC The DMAC must be configured before the SERCOM DMA requests are used Related Links DMAC Direct Memory Access Controller on page 432 31 5 5 Interrupts The interrupt request line is connected to the I...

Page 595: ...nal clock Figure 31 2 SERCOM Serial Engine Transmitter Baud Rate Generator Selectable Internal Clk GCLK Ext Clk Receiver Address Match baud rate generator tx shift register rx shift register rx buffer...

Page 596: ...egister CTRLA SWRST will reset all registers of this peripheral to their initial states except the DBGCTRL register and the peripheral is disabled Refer to the CTRLA register description for details 3...

Page 597: ...ndition Baud Rate Bits Per Second BAUD Register Value Calculation Asynchronous Arithmetic S S 1 65536 65536 1 Asynchronous Fractional S S 8 8 Synchronous 2 2 1 2 1 S Number of samples per bit Can be 1...

Page 598: ...capable of matching either one address two unique addresses or a range of addresses with a mask based on the mode selected The match uses seven or eight bits depending on the mode Address With Mask An...

Page 599: ...ponding bit in the Interrupt Enable Clear register INTENCLR An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled The interrupt request remains ac...

Page 600: ...k domains some registers need to be synchronized when written or read Required write synchronization is denoted by the Write Synchronized property in the register description Required read synchroniza...

Page 601: ...d Links SERCOM Serial Communication Interface on page 592 SERCOM USART and I2C Configurations on page 30 32 2 USART Features Full duplex operation Asynchronous with clock reconstruction or synchronous...

Page 602: ...es requires the I O pins to be configured using the I O Pin Controller PORT When the SERCOM is used in USART mode the SERCOM controls the direction and value of the I O pins according to the table bel...

Page 603: ...In order to use DMA requests with this peripheral the DMAC must be configured first Refer to DMAC Direct Memory Access Controller for details Related Links DMAC Direct Memory Access Controller on pag...

Page 604: ...it From 5 to 9 data bits MSB or LSB first No even or odd parity bit 1 or 2 stop bits A frame starts with the start bit followed by one character of data bits If enabled the parity bit is inserted afte...

Page 605: ...iting the Receive Data Pinout value in the CTRLA register CTRLA RXPO 4 Select pads for the transmitter and external clock by writing the Transmit Data Pinout bit in the CTRLA register CTRLA TXPO 5 Con...

Page 606: ...e Figure 32 3 Clock Generation XCK CTRLA MODE 0 1 0 XCKInternal Clk GCLK Baud Rate Generator Base Period 2 8 2 8 1 1 0 1 0 0 1 Tx Clk Rx Clk CTRLA CMODE Related Links Clock Generation Baud Rate Genera...

Page 607: ...pt will be generated The Data Register Empty flag in the Interrupt Flag Status and Clear register INTFLAG DRE indicates that the register is empty and ready for new data The DATA register should only...

Page 608: ...es a low pass filter to each incoming bit thereby improving the noise immunity of the receiver Asynchronous Operational Range The operational range of the asynchronous reception depends on the accurac...

Page 609: ...Rx Error The recommendation values in the table above accommodate errors of the clock source and the baud generator The following figure gives an example for a baud rate of 3Mbps Figure 32 6 USART Rx...

Page 610: ...us mode CTRLA CMODE 0 and Flow control pinout CTRLA TXPO 2 When the receiver is disabled or the receive FIFO is full the receiver will drive the RTS pin high This notifies the remote device to stop tr...

Page 611: ...t is accepted as a 0 the second bit is a 1 and the third bit is also a 1 A low pulse is rejected since it does not meet the minimum requirement of 2 16 baud clock Figure 32 11 IrDA Receive Decoding Ir...

Page 612: ...en the transmitter is active Figure 32 13 RS485 Bus Connection TXD TE USART RXD Differential Bus The TE pin will remain high for the complete frame including stop bit s If a Guard Time is programmed i...

Page 613: ...TRLA RXINV 1 and CTRLA TXINV 1 Protocol T 0 In T 0 protocol a character is made up of one start bit eight data bits one parity bit and one guard time which lasts two bit times The transfer is synchron...

Page 614: ...mmed value in CTRLC MAXITER the STATUS ITER bit is set and the internal iteration counter is reset If the repetition of the character is acknowledged by the receiver before the maximum iteration is re...

Page 615: ...ugh the pad so the signal is also available externally 32 6 3 9 Start of Frame Detection The USART start of frame detector can wake up the CPU when it detects a start bit In standby sleep mode the int...

Page 616: ...when DATA is read Data transmit TX The request is set when the transmit buffer TX DATA is empty The request is cleared when DATA is written 32 6 4 2 Interrupts The USART has the following interrupt so...

Page 617: ...device Internal clocking CTRLA RUNSTDBY 0 Internal clock will be disabled after any ongoing transfer was completed The Receive Complete interrupt s can wake up the device External clocking CTRLA RUNST...

Page 618: ...15 8 0x0E RXPL 7 0 RXPL 7 0 0x0F 0x13 Reserved 0x14 INTENCLR 7 0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7 0 ERROR RXBRK CTSIC RXS RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7 0 ERRO...

Page 619: ...Read Synchronized and or Write Synchronized property in each individual register description Optional write protection by the Peripheral Access Controller PAC is denoted by the PAC Write Protection p...

Page 620: ...R W Reset 0 0 0 0 0 0 Bit 30 DORD Data Order This bit selects the data order when a character is shifted out from the Data register This bit is not synchronized Value Description 0 MSB is transmitted...

Page 621: ...MPA 1 0 16x Over sampling CTRLA SAMPR 0 or 1 8x Over sampling CTRLA SAMPR 2 or 3 0x0 7 8 9 3 4 5 0x1 9 10 11 4 5 6 0x2 11 12 13 5 6 7 0x3 13 14 15 6 7 8 Bits 21 20 RXPO 1 0 Receive Data Pinout These b...

Page 622: ...ling using arithmetic baud rate generation 0x5 0x7 Reserved Bit 10 RXINV Receive Data Invert This bit controls whether the receive data RxD is inverted or not Note Start parity and stop bit s are unch...

Page 623: ...nabled disabled The value written to CTRLA ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register SYNCBUSY ENABLE will be set SYNCBUSY ENABLE is...

Page 624: ...Value Description 0 There is no reset operation ongoing 1 The reset operation is ongoing Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 624...

Page 625: ...receiver is enabled When the receiver is enabled CTRLB RXEN will read back as 1 Writing 1 to CTRLB RXEN when the USART is enabled will set SYNCBUSY CTRLB which will remain set until the receiver is en...

Page 626: ...d Value Description 0 Even parity 1 Odd parity Bit 10 ENC Encoding Format This bit selects the data encoding format This bit is not synchronized Value Description 0 Data is not encoded 1 Data is IrDA...

Page 627: ...ted This bit is not synchronized Value Description 0 One stop bit 1 Two stop bits Bits 2 0 CHSIZE 2 0 Character Size These bits select the number of bits in a character These bits are not synchronized...

Page 628: ...e transmitter when CTRLC DSNACK is set This field is only valid when using ISO7816 T 0 mode CTRLA MODE 0x7 and CTRLA CMODE 0 Value Description 0 NACK is sent on the ISO line for every parity error rec...

Page 629: ...received Bits 2 0 GTIME 2 0 Guard Time These bits define the guard time when using RS485 mode CTRLA TXPO 0x3 or ISO7816 mode CTRLA MODE 0x7 ISO7816 mode CTRLA TXPO 0x7 RS485 mode CTRLA TXPO 0x3 For RS...

Page 630: ...ontrol the clock generation as described in the SERCOM Baud Rate section If Fractional Baud Rate Generation CTRLA SAMPR 0 1 bit positions 15 to 13 are replaced by FP 2 0 Fractional Part Bits 15 13 FP...

Page 631: ...et 0 0 0 0 0 0 0 0 Bits 7 0 RXPL 7 0 Receive Pulse Length When the encoding format is set to IrDA CTRLB ENC 1 these bits control the minimum pulse length that is required for a pulse to be accepted by...

Page 632: ...Writing 0 to this bit has no effect Writing 1 to this bit will clear the Receive Break Interrupt Enable bit which disables the Receive Break interrupt Value Description 0 Receive Break interrupt is d...

Page 633: ...bit has no effect Writing 1 to this bit will clear the Transmit Complete Interrupt Enable bit which disables the Receive Complete interrupt Value Description 0 Transmit Complete interrupt is disabled...

Page 634: ...ble Writing 0 to this bit has no effect Writing 1 to this bit will set the Receive Break Interrupt Enable bit which enables the Receive Break interrupt Value Description 0 Receive Break interrupt is d...

Page 635: ...s bit has no effect Writing 1 to this bit will set the Transmit Complete Interrupt Enable bit which enables the Transmit Complete interrupt Value Description 0 Transmit Complete interrupt is disabled...

Page 636: ...has no effect Writing 1 to this bit will clear the flag Bit 4 CTSIC Clear to Send Input Change This flag is cleared by writing a 1 to it This flag is set when a change is detected on the CTS pin Writi...

Page 637: ...o new data in DATA Writing 0 to this bit has no effect Writing 1 to this bit will clear the flag Bit 0 DRE Data Register Empty This flag is cleared by writing new data to DATA This flag is set when DA...

Page 638: ...it has no effect Writing 1 to this bit will clear it Bit 4 ISF Inconsistent Sync Field This bit is cleared by writing 1 to the bit or by disabling the receiver This bit is set when the frame format is...

Page 639: ...abling the receiver This bit is set if the received character had a frame error i e when the first stop bit is zero Writing 0 to this bit has no effect Writing 1 to this bit will clear it Bit 0 PERR P...

Page 640: ...chronization is not busy 1 RXERRCNT synchronization is busy Bit 2 CTRLB CTRLB Synchronization Busy Writing to the CTRLB register when the SERCOM is enabled requires synchronization When writing to CTR...

Page 641: ...Synchronization Busy Resetting the SERCOM CTRLA SWRST requires synchronization When written the SYNCBUSY SWRST bit will be set until synchronization is complete Writes to any register while synchroniz...

Page 642: ...R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7 0 RXERRCNT 7 0 Receive Error Count This register records the total number of parity errors and NACK errors combined in ISO7816 mode CTRLA FORM 0x7 This regis...

Page 643: ...when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register INTFLAG RXC is set The status bits in STATUS should be read before reading the DATA value in order to get a...

Page 644: ...the baud rate generator functionality when the CPU is halted by an external debugger Value Description 0 The baud rate generator continues normal operation when the CPU is halted by an external debugg...

Page 645: ...ERCOM Serial Communication Interface on page 592 33 2 Features SERCOM SPI includes the following features Full duplex four wire interface MISO MOSI SCK SS Single buffered transmitter double buffered r...

Page 646: ...Pin Controller PORT When the SERCOM is configured for SPI operation the SERCOM controls the direction and value of the I O pins according to the table below Both PORT control bits PINCFGn PULLEN and...

Page 647: ...figured first Refer to DMAC Direct Memory Access Controller for details Related Links DMAC Direct Memory Access Controller on page 432 33 5 5 Interrupts The interrupt request line is connected to the...

Page 648: ...is ready for a new character The SPI transaction format is shown in SPI Transaction Format Each transaction can contain one or more characters The character size is configurable and can be either 8 or...

Page 649: ...1 Select the desired baud rate by writing to the Baud register BAUD 8 2 If Hardware SS control is required write 1 to the Master Slave Select Enable bit in CTRLB register CTRLB MSSEN 9 Enable the rec...

Page 650: ...e is configured by the Clock Phase bit in the CTRLA register CTRLA CPHA SCK polarity is programmed by the Clock Polarity bit in the CTRLA register CTRLA CPOL Data bits are shifted out and latched in o...

Page 651: ...SS can be assigned to any general purpose I O pin When the SPI is ready for a data transaction software must pull the SS line low When writing a character to the Data register DATA the character will...

Page 652: ...loaded into the shift register on the next character boundary As a consequence the first character transferred in a SPI transaction will not be the content of DATA This can be avoided by using the pre...

Page 653: ...the shift register will be shifted out Only one data character will be preloaded into the shift register while the synchronized SS signal is high If the next character is written to DATA before SS is...

Page 654: ...ter SPI Master SPI Slave 0 SPI Slave n 1 33 6 3 4 Loop Back Mode For loop back mode configure the Data In Pinout CTRLA DIPO and Data Out Pinout CTRLA DOPO to use the same data pins for transmit and re...

Page 655: ...NA Yes Slave Select low SSL NA Yes Error ERROR NA Yes 33 6 4 1 DMA Operation The SPI generates the following DMA requests Data received RX The request is set when data is available in the receive FIF...

Page 656: ...Control A register CTRLA RUNSTDBY Master operation CTRLA RUNSTDBY 1 The peripheral clock GCLK_SERCOM_CORE will continue to run in idle sleep mode and in standby sleep mode Any interrupt can wake up th...

Page 657: ...TENCLR 7 0 ERROR SSL RXC TXC DRE 0x15 Reserved 0x16 INTENSET 7 0 ERROR SSL RXC TXC DRE 0x17 Reserved 0x18 INTFLAG 7 0 ERROR SSL RXC TXC DRE 0x19 Reserved 0x1A STATUS 7 0 BUFOVF 0x1B 15 8 0x1C SYNCBUSY...

Page 658: ...Synchronized property in each individual register description Refer to Synchronization Some registers are enable protected meaning they can only be written when the module is disabled Enable protecti...

Page 659: ...ifted out from the shift register This bit is not synchronized Value Description 0 MSB is transferred first 1 LSB is transferred first Bit 29 CPOL Clock Polarity In combination with the Clock Phase bi...

Page 660: ...DR SPI frame with address 0x3 0xF Reserved Bits 21 20 DIPO 1 0 Data In Pinout These bits define the data in DI pad configurations In master operation DI is MISO In slave operation DI is MOSI These bit...

Page 661: ...l interrupts can wake up the device 0x1 Ongoing transaction continues wake on Receive Complete interrupt Generic clock is enabled while in sleep modes All interrupts can wake up the device Bits 4 2 MO...

Page 662: ...ter write access during the ongoing reset will result in an APB error Reading any register will return the reset value of the register Due to synchronization there is a delay from writing CTRLA SWRST...

Page 663: ...sabled will set CTRLB RXEN immediately When the SPI is enabled CTRLB RXEN will be cleared SYNCBUSY CTRLB will be set and remain set until the receiver is enabled When the receiver is enabled CTRLB RXE...

Page 664: ...abled Bit 9 SSDE Slave Select Low Detect Enable This bit enables wake up when the slave select SS pin transitions from high to low Value Description 0 SS low detector is disabled 1 SS low detector is...

Page 665: ...2 1 0 BAUD 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 7 0 BAUD 7 0 Baud Register These bits control the clock generation as described in the SERCOM Clock Generation Baud Ra...

Page 666: ...terrupt Enable bit which disables the Slave Select Low interrupt Value Description 0 Slave Select Low interrupt is disabled 1 Slave Select Low interrupt is enabled Bit 2 RXC Receive Complete Interrupt...

Page 667: ...to this bit has no effect Writing 1 to this bit will clear the Data Register Empty Interrupt Enable bit which disables the Data Register Empty interrupt Value Description 0 Data Register Empty interr...

Page 668: ...terrupt Enable bit which enables the Slave Select Low interrupt Value Description 0 Slave Select Low interrupt is disabled 1 Slave Select Low interrupt is enabled Bit 2 RXC Receive Complete Interrupt...

Page 669: ...0 to this bit has no effect Writing 1 to this bit will set the Data Register Empty Interrupt Enable bit which enables the Data Register Empty interrupt Value Description 0 Data Register Empty interru...

Page 670: ...2 RXC Receive Complete This flag is cleared by reading the Data DATA register or by disabling the receiver This flag is set when there are unread data in the receive buffer If address matching is enab...

Page 671: ...n DATA is empty and ready for new data to transmit Writing 0 to this bit has no effect Writing 1 to this bit has no effect Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_...

Page 672: ...his bit is cleared by writing 1 to the bit or by disabling the receiver This bit is set when a buffer overflow condition is detected See also CTRLA IBON for overflow handling When set the correspondin...

Page 673: ...tten while SYNCBUSY CTRLB 1 an APB error will be generated Value Description 0 CTRLB synchronization is not busy 1 CTRLB synchronization is busy Bit 1 ENABLE SERCOM Enable Synchronization Busy Enablin...

Page 674: ...SYNCBUSY SWRST 1 until synchronization is complete Writes to any register while synchronization is on going will be discarded and an APB error will be generated Value Description 0 SWRST synchronizat...

Page 675: ...Access Reset Bit 7 6 5 4 3 2 1 0 ADDR 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 23 16 ADDRMASK 7 0 Address Mask These bits hold the address mask when the transaction forma...

Page 676: ...he receive data buffer The register should be read only when the Receive Complete Interrupt Flag bit in the Interrupt Flag Status and Clear register INTFLAG RXC is set Writing these bits will write th...

Page 677: ...controls the functionality when the CPU is halted by an external debugger Value Description 0 The baud rate generator continues normal operation when the CPU is halted by an external debugger 1 The b...

Page 678: ...lated Links SERCOM Serial Communication Interface on page 592 SERCOM USART and I2C Configurations on page 30 34 2 Features SERCOM I2C includes the following features Master or slave operation Can be u...

Page 679: ...other parts of the system must be configured correctly as described below 34 5 1 I O Lines In order to use the I O lines of this peripheral the I O pins must be configured using the I O Pin Controlle...

Page 680: ...st Refer to DMAC Direct Memory Access Controller for details Related Links DMAC Direct Memory Access Controller on page 432 34 5 5 Interrupts The interrupt request line is connected to the Interrupt C...

Page 681: ...lave will then acknowledge ACK the address and data packet transactions can begin Every 9 bit data packet consists of 8 data bits followed by a one bit reply indicating whether the data was acknowledg...

Page 682: ...will be discarded If the I2C is being disabled writing to these registers will be completed after the disabling Enable protection is denoted by the Enable Protection property in the register descript...

Page 683: ...TATE in the figure is shown in binary Figure 34 3 Bus State Diagram RESET Write ADDR to generate Start Condition IDLE 0b01 Start Condition BUSY 0b11 Timeout or Stop Condition UNKNOWN 0b00 OWNER 0b10 L...

Page 684: ...length Note Violating the protocol may cause the I2C to hang If this happens it is possible to recover from this state by a software reset CTRLA SWRST 1 Related Links CTRLA on page 722 34 6 2 4 I2C Ma...

Page 685: ...Software interaction A A R W BUSY M4 The master provides data on the bus Addressed slave provides data on the bus In the second strategy CTRLA SCLSM 1 interrupts only occur after the ACK bit as in Mas...

Page 686: ...z The Master clock configuration for Sm Fm and Fm are described in Clock Generation Standard Mode Fast Mode and Fast Mode Plus For Hs refer to Master Clock Generation High Speed Mode Clock Generation...

Page 687: ...s Refer to Electrical Characteristics TFALL is determined by the open drain current limit and bus impedance can typically be regarded as zero Refer to Electrical Characteristics for details The SCL fr...

Page 688: ...rise according to arbitration and transfer direction Case 1 Arbitration lost or bus error during address packet transmission If arbitration was lost during transmission of the address packet the Maste...

Page 689: ...cket Terminate the transaction by issuing a stop condition Note An ACK or NACK will be automatically transmitted if smart mode is enabled The Acknowledge Action bit in the Control B register CTRLB ACK...

Page 690: ...ting in High speed mode requires the I2C master to be configured in High speed mode CTRLA SPEED 0x2 and the SCL clock stretch mode CTRLA SCLSM bit set to 1 10 Bit Addressing When 10 bit addressing is...

Page 691: ...interaction This diagram is used as reference for the description of the I2C slave operation throughout the document Figure 34 9 I2C Slave Behavioral Diagram SCLSM 0 S S3 ADDRESS S2 A S1 R W DATA A A...

Page 692: ...on bit in the Status register STATUS DIR This bit will be updated only when a valid address packet is received If the Transmit Collision bit in the Status register STATUS COLL is set this indicates th...

Page 693: ...will be stretched until the I2C slave clears INTFLAG AMATCH As the I2C slave holds the clock by forcing SCL low the software is given unlimited time to respond to the address The direction of a transa...

Page 694: ...the second address interrupt will be received with the DIR bit set The slave matches on the second address as it it was addressed by the previous 10 bit address Figure 34 11 10 bit Addressing S A W ad...

Page 695: ...e of 25 ms Measured as the cumulative SCL low extend time by a slave device in a single message from the initial START to the STOP It is enabled by CTRLA SEXTTOEN TLOW MEXT Cumulative clock low extend...

Page 696: ...ss At this point the software can either issue a stop command or a repeated start by writing CTRLB CMD or ADDR ADDR 34 6 4 DMA Interrupts and Events Table 34 1 Module Request for SERCOM I2C Slave Cond...

Page 697: ...C master with DMA the ADDR register must be written with the desired address ADDR ADDR transaction length ADDR LEN and transaction length enable ADDR LENEN When ADDR LENEN is written to 1 along with A...

Page 698: ...o Nested Vector Interrupt Controller for details Related Links Nested Vector Interrupt Controller on page 44 34 6 4 3 Events Not applicable 34 6 5 Sleep Mode Operation I2C Master Operation The generic...

Page 699: ...master operation Required write synchronization is denoted by the Write Synchronized property in the register description Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_C...

Page 700: ...MASK 6 0 0x27 31 24 ADDRMASK 9 7 0x28 DATA 7 0 DATA 7 0 0x29 15 8 34 8 Register Description I2C Slave Registers can be 8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition th...

Page 701: ...an only be written when the peripheral is disabled Enable protection is denoted by the Enable Protected property in each individual register description Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E...

Page 702: ...L low time out If SCL is held low for 25ms 35ms the slave will release its clock hold if enabled and reset the internal state machine Any interrupt flags set at the time of time out will remain set Va...

Page 703: ...Description 0 Time out disabled 1 Time out enabled Bits 21 20 SDAHOLD 1 0 SDA Hold Time These bits define the SDA hold time with respect to the negative edge of SCL These bits are not synchronized Val...

Page 704: ...0 SWRST Software Reset Writing 0 to this bit has no effect Writing 1 to this bit resets all registers in the SERCOM except DBGCTRL to their initial state and the SERCOM will be disabled Writing 1 to...

Page 705: ...is executed when a command is written to the CMD bits If smart mode is enabled CTRLB SMEN 1 the acknowledge action is performed when the DATA register is read This bit is not enable protected Value D...

Page 706: ...ion 0x0 MASK The slave responds to the address written in ADDR ADDR masked by the value in ADDR ADDRMASK See SERCOM Serial Communication Interface for additional information 0x1 2_ADDRS The slave resp...

Page 707: ...8 SMEN Smart Mode Enable When smart mode is enabled data is acknowledged automatically when DATA DATA is read This bit is not write synchronized Value Description 0 Smart mode is disabled 1 Smart mod...

Page 708: ...Ready Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will clear the Data Ready bit which disables the Data Ready interrupt Value Description 0 The Data Ready interrupt is d...

Page 709: ...Value Description 0 The Stop Received interrupt is disabled 1 The Stop Received interrupt is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 709...

Page 710: ...a Ready Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will set the Data Ready bit which enables the Data Ready interrupt Value Description 0 The Data Ready interrupt is di...

Page 711: ...Value Description 0 The Stop Received interrupt is disabled 1 The Stop Received interrupt is enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 711...

Page 712: ...to this bit will clear the Data Ready interrupt flag Bit 1 AMATCH Address Match This flag is set when the I2C slave address match logic detects that a valid address has been received The flag is clea...

Page 713: ...transmission Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the status However this flag is automatically cleared when a STOP is received Bit 9 SEXTTOUT Slave SCL Low Extend...

Page 714: ...received from a master Value Description 0 Master write operation is in progress 1 Master read operation is in progress Bit 2 RXNACK Received Not Acknowledge This bit indicates whether the last data p...

Page 715: ...op is detected on the I2C bus lines A start condition directly followed by a stop condition is one example of a protocol violation If a time out occurs during a frame this is also considered a protoco...

Page 716: ...ept for CTRLA SWRST while enable synchronization is on going will be discarded and an APB error will be generated Value Description 0 Enable synchronization is not busy 1 Enable synchronization is bus...

Page 717: ...15 TENBITEN Ten Bit Addressing Enable Value Description 0 10 bit address recognition disabled 1 10 bit address recognition enabled Bits 10 1 ADDR 9 0 Address These bits contain the I2C slave address u...

Page 718: ...alue Description 0 General call address recognition disabled 1 General call address recognition enabled Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 71...

Page 719: ...lid data or writing data to be transmitted can be successfully done only when SCL is held low by the slave STATUS CLKHOLD is set An exception occurs when reading the last data byte after the stop cond...

Page 720: ...0 0x10 0x13 Reserved 0x14 INTENCLR 7 0 ERROR SB MB 0x15 Reserved 0x16 INTENSET 7 0 ERROR SB MB 0x17 Reserved 0x18 INTFLAG 7 0 ERROR SB MB 0x18 DATA 7 0 DATA 7 0 0x19 15 8 0x1A STATUS 7 0 CLKHOLD LOWT...

Page 721: ...operty in each individual register description For details refer to Register Access Protection Some registers are synchronized when read and or written Synchronization is denoted by the Write Synchron...

Page 722: ...current transaction A stop condition will automatically be transmitted INTFLAG SB or INTFLAG MB will be set as normal but the clock hold will be released The STATUS LOWTOUT and STATUS BUSERR status bi...

Page 723: ...ut If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP the master will release its clock hold if enabled and complete the current transaction A STOP will automatical...

Page 724: ...synchronized Value Description 0 GCLK_SERCOMx_CORE is disabled and the I2C master will not operate in standby sleep mode 1 GCLK_SERCOMx_CORE is enabled in all sleep modes Bits 4 2 MODE 2 0 Operating M...

Page 725: ...ame write operation will be discarded Any register write access during the ongoing reset will result in an APB error Reading any register will return the reset value of the register Due to synchroniza...

Page 726: ...when DATA DATA is read This bit is not enable protected This bit is not write synchronized Value Description 0 Send ACK 1 Send NACK Bits 17 16 CMD 1 0 Command Writing these bits triggers a master oper...

Page 727: ...ction succeeded by repeated Start 0x2 0 Write No operation 1 Read Execute acknowledge action succeeded by a byte read operation 0x3 X Execute acknowledge action succeeded by issuing a stop condition T...

Page 728: ...to time TLOW THIGH TSU STO THD STA and TSU STA TBUF is timed by the BAUD register Bits 23 16 HSBAUD 7 0 High Speed Master Baud Rate This bit field indicates the SCL high time in High speed mode accord...

Page 729: ...For more information on how to calculate the frequency see SERCOM Clock Generation Baud Rate Generator Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 729...

Page 730: ...on 0 Error interrupt is disabled 1 Error interrupt is enabled Bit 1 SB Slave on Bus Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will clear the Slave on Bus Interrupt Ena...

Page 731: ...tion 0 Error interrupt is disabled 1 Error interrupt is enabled Bit 1 SB Slave on Bus Interrupt Enable Writing 0 to this bit has no effect Writing 1 to this bit will set the Slave on Bus Interrupt Ena...

Page 732: ...N Writing a valid command to CTRLB CMD Writing 1 to this bit location will clear the SB flag The transaction will not continue or be terminated until one of the above actions is performed Writing 0 to...

Page 733: ...Writing 0 to this bit has no effect Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 733...

Page 734: ...rs This bit is automatically cleared when writing to the ADDR register Writing 1 to this bit location will clear SEXTTOUT Normal use of the I2C interface does not require the SEXTTOUT flag to be clear...

Page 735: ...0x1 IDLE The bus state is waiting for a transaction to be initialized 0x2 OWNER The I2C master is the current owner of the bus 0x3 BUSY Some other I2C master owns the bus Bit 2 RXNACK Received Not Ac...

Page 736: ...otocol violation If a time out occurs during a frame this is also considered a protocol violation and will set BUSERR If the I2C master is the bus owner at the time a bus error occurs STATUS ARBLOST a...

Page 737: ...1 System operation synchronization is busy Bit 1 ENABLE SERCOM Enable Synchronization Busy Enabling and disabling the SERCOM CTRLA ENABLE requires synchronization When written the SYNCBUSY ENABLE bit...

Page 738: ...on going will be discarded and an APB error will be generated Value Description 0 SWRST synchronization is not busy 1 SWRST synchronization is busy Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM...

Page 739: ...LENEN bit must be written to 1 in order to use DMA Bit 15 TENBITEN Ten Bit Addressing Enable This bit enables 10 bit addressing This bit can be written simultaneously with ADDR to indicate a 10 bit o...

Page 740: ...ed start sequence will be performed If the previous transaction was a read the acknowledge action is sent before the repeated start bus condition is issued on the bus Writing ADDR to issue a repeated...

Page 741: ...ng valid data or writing data to be transmitted can be successfully done only when SCL is held low by the master STATUS CLKHOLD is set An exception is reading the last data byte after the stop conditi...

Page 742: ...it controls functionality when the CPU is halted by an external debugger Value Description 0 The baud rate generator continues normal operation when the CPU is halted by an external debugger 1 The bau...

Page 743: ...ration and pulse width modulation 35 2 Features Selectable configuration 8 16 or 32 bit TC operation with compare capture channels 2 compare capture channels CC with Double buffered timer period setti...

Page 744: ...er BUFV 0 Event System Waveform Generation Control Logic COUNT CCx CCBUFx 35 4 Signal Description Table 35 1 Signal Description for TC Signal Name Type Description WO 1 0 Digital output Waveform outpu...

Page 745: ...ock CLK_TCx_APB Due to this asynchronicity accessing certain registers will require synchronization between the clock domains Refer to Synchronization for further details Note that TC0 and TC1 share a...

Page 746: ...through an external debugger 35 5 9 Analog Connections Not applicable 35 6 Functional Description 35 6 1 Principle of Operation The following definitions are used throughout the documentation Table 35...

Page 747: ...hese comparisons are used to set the waveform period or pulse width Capture operation can be enabled to perform input signal period and pulse width measurements or to capture selectable edges from an...

Page 748: ...tionally executed on the next GCLK_TCx clock pulse or the next prescaled clock pulse For further details refer to Prescaler CTRLA PRESCALER and Counter Synchronization CTRLA PRESYNC description Presca...

Page 749: ...it in the Control B register is set CTRLBSET ONESHOT It is possible to change the counter value by writing directly in the COUNT register even when the counter is running When starting the TC the COUN...

Page 750: ...RL EVACT 0x3 START 35 6 2 6 Compare Operations By default the Compare Capture channel is configured for compare operations When using the TC and the Compare Capture Value registers CCx for compare ope...

Page 751: ...is toggled on each compare match between COUNT and CCx and the corresponding Match or Capture Channel x Interrupt Flag INTFLAG MCx will be set Figure 35 4 Normal Frequency Operation COUNT MAX TOP ZER...

Page 752: ...event interrupt generation conditions in different operation modes Table 35 3 Counter Update and Overflow Event interrupt Conditions in TC Name Operation TOP Update Output Waveform OVFIF Event On Mat...

Page 753: ...ng CCBUFVx UPDATE write enable data write COUNT match EN EN CCBUFx CCx Both the registers PER CCx and corresponding buffer registers PERBUF CCBUFx are available in the I O register map and the double...

Page 754: ...ritten to TOP COUNT will wrap before a compare match Figure 35 9 Unbuffered Single Slope Down Counting Operation COUNT MAX New TOP written to PER that is higher than current COUNT New TOP written to P...

Page 755: ...from the Event System By default a capture operation is done when a rising edge is detected on the input signal Capture on falling edge is available its activation is depending on the input source Wh...

Page 756: ...ollowing figure shows four capture events for one capture channel Figure 35 12 Input Capture Timing events COUNT TOP ZERO Capture 0 Capture 1 Capture 2 Capture 3 The TC can detect capture overflow of...

Page 757: ...ct capture overflow of the input capture channels When a new capture event is detected while the Capture Interrupt flag INTFLAG MCx is still set the new timestamp will not be stored and INTFLAG ERR wi...

Page 758: ...ting operation The one shot operation can be restarted by a re trigger software command a re trigger event or a start event When the counter restarts its operation STATUS STOP is automatically cleared...

Page 759: ...rupt condition occurs Each interrupt can be individually enabled by writing a 1 to the corresponding bit in the Interrupt Enable Set register INTENSET and disabled by writing a 1 to the corresponding...

Page 760: ...On Demand bit in the Control A register CTRLA ONDEMAND is written to 1 the module stops requesting its peripheral clock when the STOP bit in STATUS register STATUS STOP is set to 1 When a re trigger o...

Page 761: ...VF 0x09 INTENSET 7 0 MC1 MC0 ERR OVF 0x0A INTFLAG 7 0 MC1 MC0 ERR OVF 0x0B STATUS 7 0 CCBUFV1 CCBUFV0 PERBUFV SLAVE STOP 0x0C WAVE 7 0 WAVEGEN 1 0 0x0D DRVCTRL 7 0 INVEN1 INVEN0 0x0E Reserved 0x0F DBG...

Page 762: ...ESHOT LUPD DIR 0x06 EVCTRL 7 0 TCEI TCINV EVACT 2 0 0x07 15 8 MCEO1 MCEO0 OVFEO 0x08 INTENCLR 7 0 MC1 MC0 ERR OVF 0x09 INTENSET 7 0 MC1 MC0 ERR OVF 0x0A INTFLAG 7 0 MC1 MC0 ERR OVF 0x0B STATUS 7 0 CCB...

Page 763: ...SYNC 1 0 MODE 1 0 ENABLE SWRST 0x01 15 8 ALOCK PRESCALER 2 0 0x02 23 16 COPEN1 COPEN0 CAPTEN1 CAPTEN0 0x03 31 24 0x04 CTRLBCLR 7 0 CMD 2 0 ONESHOT LUPD DIR 0x05 CTRLBSET 7 0 CMD 2 0 ONESHOT LUPD DIR 0...

Page 764: ...eserved 0x26 Reserved 0x27 Reserved 0x28 Reserved 0x29 Reserved 0x2A Reserved 0x2B Reserved 0x2C Reserved 0x2D Reserved 0x2E Reserved 0x2F Reserved 0x30 CCBUF0 7 0 CCBUF 7 0 0x31 15 8 CCBUF 15 8 0x32...

Page 765: ...in each individual register description For details refer to Register Access Protection Some registers are synchronized when read and or written Synchronization is denoted by the Write Synchronized o...

Page 766: ...LOCK Auto Lock When this bit is set Lock bit update LUPD is set to 1 on each overflow underflow or re trigger event This bit is not synchronized Value Description 0 The LUPD bit is not affected on ove...

Page 767: ...to keep the TC running in standby mode This bit is not synchronized Value Description 0 The TC is halted in standby 1 The TC continues to run in standby Bits 5 4 PRESCSYNC 1 0 Prescaler and Counter S...

Page 768: ...will be discarded Due to synchronization there is a delay from writing CTRLA SWRST until the reset is complete CTRLA SWRST and SYNCBUSY SWRST will both be cleared when the reset is complete Value Desc...

Page 769: ...hot operation Value Description 0 The TC will wrap around and continue counting on an overflow underflow condition 1 The TC will wrap around and stop on the next underflow overflow condition Bit 1 LUP...

Page 770: ...bit has no effect Writing a 1 to this bit will clear the bit and make the counter count up Value Description 0 The timer counter is counting up incrementing 1 The timer counter is counting down decrem...

Page 771: ...r retrigger 0x2 STOP Force a stop 0x3 UPDATE Force update of double buffered registers 0x4 READSYNC Force a read synchronization of COUNT Bit 2 ONESHOT One Shot on Counter This bit controls one shot o...

Page 772: ...lue are not copied into CCx and PER registers on hardware update condition Bit 0 DIR Counter Direction This bit is used to change the direction of the counter Writing a 0 to this bit has no effect Wri...

Page 773: ...enabled and will be generated for every counter overflow underflow Bit 5 TCEI TC Event Enable This bit is used to enable asynchronous input events to the TC Value Description 0 Incoming events are di...

Page 774: ...x Match or Capture Channel x Event Output Enable x 1 0 These bits enable the generation of an event for every match or capture on channel x Value Description 0 Match Capture event on channel x is disa...

Page 775: ...he Error interrupt is enabled Bit 0 OVF Overflow Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the Overflow Interrupt Enable bit which disables the Overflow...

Page 776: ...The Error interrupt is enabled Bit 0 OVF Overflow Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will set the Overflow Interrupt Enable bit which enables the Overflow i...

Page 777: ...NTENCLR OVF or INTENSET OVF is 1 Writing a 0 to this bit has no effect Writing a 1 to this bit clears the Overflow interrupt flag Bits 5 4 MCx Match or Capture Channel x x 1 0 This flag is set on a co...

Page 778: ...C2 respectively is set to run in 32 bit mode Bit 0 STOP Stop Status Flag This bit is set when the TC is disabled on a Stop command or on an overflow underflow condition when the One Shot bit in the Co...

Page 779: ...d The waveform generation operations are explained in Waveform Output Operations These bits are not synchronized Value Name Operation Top Value Output Waveform on Match Output Waveform on Wraparound 0...

Page 780: ...1 0 INVENx Output Waveform x Invert Enable x 1 0 These bits are used to select inversion of the output or capture trigger input of channel x Value Description 0 Disable inversion of the WO x output a...

Page 781: ...e This bit is not affected by a software reset and should not be changed by software while the TC is enabled Value Description 0 The TC is halted when the device is halted in debug mode 1 The TC conti...

Page 782: ...cleared when the synchronization of COUNT between the clock domains is complete This bit is set when the synchronization of COUNT between clock domains is started Bit 3 STATUS STATUS Synchronization...

Page 783: ...en clock domains is started Bits 7 6 CCx Compare Capture Channel x Synchronization Busy For details on CC channels number refer to each TC feature list This bit is set when the synchronization of CCx...

Page 784: ...ET CMD READSYNC Name COUNT Offset 0x14 Reset 0x00 Property PAC Write Protection Write Synchronized Read Synchronized Bit 7 6 5 4 3 2 1 0 COUNT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0...

Page 785: ...Property PAC Write Protection Write Synchronized Read Synchronized Bit 15 14 13 12 11 10 9 8 COUNT 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT 7 0 Acce...

Page 786: ...31 24 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT 23 16 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT...

Page 787: ...R 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 1 Bits 7 0 PER 7 0 Period Value These bits hold the value of the Period Buffer register PERBUF The value is copied to PER register on U...

Page 788: ...R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 7 0 CC 7 0 Channel x Compare Capture Value These bits contain the compare capture value in 8 bit TC mode In Match frequency MFRQ or Match PWM MPWM wavefo...

Page 789: ...Bit 7 6 5 4 3 2 1 0 CC 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 CC 15 0 Channel x Compare Capture Value These bits contain the compare capture value in 16 bit TC mod...

Page 790: ...0 0 0 Bit 15 14 13 12 11 10 9 8 CC 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CC 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 C...

Page 791: ...PERBUF 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 1 Bits 7 0 PERBUF 7 0 Period Buffer Value These bits hold the value of the period buffer register The value is copied to PER regis...

Page 792: ...Channel x Compare Buffer Value These bits hold the value of the Channel x Compare Buffer Value When the buffer valid flag is 1 and double buffering is enabled CTRLBCLR LUPD 1 the data from buffer reg...

Page 793: ...W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 CCBUF 15 0 Channel x Compare Buffer Value These bits hold the value of the Channel x Compare Buffer Value When the buffer valid flag is 1 and double buffering...

Page 794: ...W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CCBUF 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 CCBUF 31 0 Channel x Compare Buffer Value These bits ho...

Page 795: ...sabling and or shut down of external drivers 36 2 Features Up to four compare capture channels CC with Double buffered period setting Double buffered compare or capture channel Circular buffer on peri...

Page 796: ...e Faults Output Matrix Dead Time Insertion SWAP Pattern Generation Non recoverable Faults WO 0 WO 1 WO 2 WO 3 WO 4 WO 5 WO 6 WO 7 Event System TCCx_EV0 TCE0 TCCx_EV1 TCE1 TCCx_MCx event PERBUFx 36 4 S...

Page 797: ...GCLK_TCCx are asynchronous to the bus clock CLK_TCCx_APB Due to this asynchronicity writing certain registers will require synchronization between the clock domains Refer to Synchronization for furthe...

Page 798: ...s through an external debugger 36 5 9 Analog Connections Not applicable 36 6 Functional Description 36 6 1 Principle of Operation The following definitions are used throughout the documentation Table...

Page 799: ...ults In addition six optional independent and successive units primarily intended for use with different types of motor control ballast LED H bridge power converter and other types of power switching...

Page 800: ...elect the Waveform Output Polarity in the WAVE register WAVE POL 6 The waveform output can be inverted for the individual channels using the Waveform Output Invert Enable bit group in the Driver regis...

Page 801: ...rigger an interrupt or an event An overflow underflow occurrence i e a compare match with TOP ZERO will stop counting if the One Shot bit in the Control B register is set CTRLBSET ONESHOT Figure 36 3...

Page 802: ...register EVCTRL EVACTn 0x1 RETRIGGER enabling the counter will not start the counter The counter will start on the next incoming event and restart on corresponding following event Start Event Action...

Page 803: ...lity The double buffering synchronizes the update of the CCx register with the buffer value at the UPDATE condition or a force update command CTRLBSET CMD 0x3 UPDATE For further details refer to Doubl...

Page 804: ...Name Operation TOP Update Output Waveform OVFIF Event On Match On Update Up Down NFRQ Normal Frequency PER TOP ZERO Toggle Stable TOP ZERO MFRQ Match Frequency CC0 TOP ZERO Toggle Stable TOP ZERO NPW...

Page 805: ...neration the period time T is controlled by Top value and CCx controls the duty cycle of the generated waveform output When up counting the WO x is set at start or compare match between the COUNT and...

Page 806: ...COUNT CCx ZERO CCx CCx TOP WO x ZERO TOP MAX match update Using dual slope PWM results in a lower maximum operation frequency compared to single slope PWM generation The period TOP defines the PWM res...

Page 807: ...and dual slope PWM operation it is possible to invert the pulse edge alignment individually on start or end of a PWM cycle for each compare channels The table below shows the waveform output set clear...

Page 808: ...egister is double buffered as in the following figure Figure 36 9 Compare Channel Double Buffering EN EN APB write enable data write UPDATE COUNT match CCBUFx CCx BV Both the registers PATT PER CCx an...

Page 809: ...6 10 COUNT and TOP are continuously compared so when a new value that is lower than the current COUNT is written to TOP COUNT will wrap before a compare match Figure 36 12 Unbuffered Dual Slope Operat...

Page 810: ...rmed Event Capture Action The compare capture channels can be used as input capture channels to capture events from the Event System and give them a timestamp The following figure shows four capture e...

Page 811: ...OUNT MAX ZERO capture CC0 CC0 CC1 CC1 Selecting PWP or PPW in the Timer Counter Event Input 1 Action bit group in the Event Control register EVCTRL EVACT1 enables the TCC to perform one capture action...

Page 812: ...underflow condition When the counter is stopped the Stop bit in the Status register STATUS STOP is set and the waveform outputs are set to the value defined by DRVCTRL NREx and DRVCTRL NRVx One shot o...

Page 813: ...NT PER CCx define the compare value itself The pseudo code giving the extra cycles insertion regarding the cycle is int extra_cycle resolution dithercy cycle int MASK int value switch resolution DITH4...

Page 814: ...odd channel output is disabled and in cycle B even channel output is disabled The ramp index changes after each update but can be software modified using the Ramp index command bits in Control B Set...

Page 815: ...M mode Fault Filtering There are three filters available for each input Fault A and Fault B They are configured by the corresponding Recoverable Fault n Configuration registers FCTRLA and FCTRLB The t...

Page 816: ...0 FCTRLA BLANKVAL 0 FCTRLA BLANKVAL 0 FaultA Blanking x x x x Fault input enabled Fault input disabled x Fault discarded Fault Qualification This is enabled by writing a 1 to the Fault n Qualification...

Page 817: ...ger present see next Figure Figure 36 23 Waveform Generation with Fault Qualification and Keep Action KEEP KEEP COUNT MAX TOP ZERO Fault Input A CC0 Fault A Input Qual x x x x WO 0 match clear update...

Page 818: ...fault occurs These capture operations are available CAPT the equivalent to a standard capture operation for further details refer to Capture Operations CAPTMIN gets the minimum time stamped value on...

Page 819: ...ted DERIV0 is equivalent to an OR function of LOCMIN LOCMAX In CAPT operation capture is performed on each capture event The MCx interrupt flag is set on each new capture In CAPTMIN and CAPTMAX operat...

Page 820: ...er counter resumes the counting operation as soon as the fault condition is no longer present As the restart action is enabled in this example the timer counter is restarted after the fault condition...

Page 821: ...rt x x WO 0 36 6 3 6 Non Recoverable Faults The non recoverable fault action will force all the compare outputs to a pre defined level programmed into the Driver Control register DRVCTRL NRE and DRVCT...

Page 822: ...rupt Flag INTFLAG MCx is set The timer counter can detect capture overflow of the input capture channels When a new capture event is detected while the Capture Channel interrupt flag INTFLAG MCx is st...

Page 823: ...el 1 to OTMX CC_NUM 1 and so on Configuration 0x1 distributes the channels on output modulo half the number of channels This assigns twice the number of output locations to the lower channels than the...

Page 824: ...Dead Time Generator Block Diagram Dead Time Generator Edge Detect D Q 0 DTLS To PORT DTHS To PORT Counter EN LOAD OTMX output DTLS DTHS As shown in Figure 36 34 the 8 bit dead time counter is decreme...

Page 825: ...operation If synchronization is not required by the application the software can simply access directly the PATT PGE PATT PGV bits registers 36 6 4 DMA Interrupts and Events Table 36 6 Module Requests...

Page 826: ...trigger on the cycle following the DMA One Shot Command written to the Control B register CTRLBSET CMD DMAOS In both cases the request is cleared by hardware on DMA acknowledge Channel Match MCx A DMA...

Page 827: ...channel is selected as a circular buffer the related DMA request is not set on a compare match detection but on start of down counting phase If at least one circular buffer is enabled the DMA overflo...

Page 828: ...reset See INTFLAG for details on how to clear interrupt flags The TCC has one common interrupt request line for all the interrupt sources The user must read the INTFLAG register to determine which in...

Page 829: ...how to configure the event system Related Links EVSYS Event System on page 570 36 6 5 Sleep Mode Operation The TCC can be configured to operate in any sleep mode To be able to run in standby the RUNS...

Page 830: ...Buffer Value registers CCx and CCBUFx Required write synchronization is denoted by the Write Synchronized property in the register description Required read synchronization is denoted by the Read Syn...

Page 831: ...0 CHSEL 1 0 HALT 1 0 0x12 23 16 BLANKVAL 7 0 0x13 31 24 FILTERVAL 3 0 0x14 WEXCTRL 7 0 OTMX 1 0 0x15 15 8 DTIEN3 DTIEN2 DTIEN1 DTIEN0 0x16 23 16 DTLS 7 0 0x17 31 24 DTHS 7 0 0x18 DRVCTRL 7 0 NRE7 NRE6...

Page 832: ...PGE2 PGE1 PGE0 0x39 15 8 PGV7 PGV6 PGV5 PGV4 PGV3 PGV2 PGV1 PGV0 0x3A 0x3B Reserved 0x3C WAVE 7 0 CIPEREN RAMP 1 0 WAVEGEN 2 0 0x3D 15 8 CICCEN3 CICCEN2 CICCEN1 CICCEN0 0x3E 23 16 POL3 POL2 POL1 POL0...

Page 833: ...CCBUF 25 18 36 8 Register Description Registers can be 8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition the 8 bit quarters and 16 bit halves of a 32 bit register and the...

Page 834: ...The Lock Update bit in the Control B register CTRLB LUPD is not affected by overflow underflow and re trigger events 1 CTRLB LUPD is set to 1 on each overflow underflow or re trigger event Bits 13 12...

Page 835: ...DIV1 Prescaler GCLK_TCC 0x1 DIV2 Prescaler GCLK_TCC 2 0x2 DIV4 Prescaler GCLK_TCC 4 0x3 DIV8 Prescaler GCLK_TCC 8 0x4 DIV16 Prescaler GCLK_TCC 16 0x5 DIV64 Prescaler GCLK_TCC 64 0x6 DIV256 Prescaler G...

Page 836: ...his bit has no effect Writing a 1 to this bit resets all registers in the TCC except DBGCTRL to their initial state and the TCC will be disabled Writing a 1 to CTRLA SWRST will always take precedence...

Page 837: ...or retrigger 0x2 STOP Force stop 0x3 UPDATE Force update of double buffered registers 0x4 READSYNC Force COUNT read synchronization Bits 4 3 IDXCMD 1 0 Ramp Index Command These bits can be used to for...

Page 838: ...This bit has no effect when input capture operation is enabled Writing a 0 to this bit has no effect Writing a 1 to this bit will enable updating Value Description 0 The CCBx PERB PGVB PGOB and SWAPB...

Page 839: ...e start restart or retrigger 0x2 STOP Force stop 0x3 UPDATE Force update of double buffered registers 0x4 READSYNC Force a read synchronization of COUNT Bits 4 3 IDXCMD 1 0 Ramp Index Command These bi...

Page 840: ...ct when input capture operation is enabled Writing a 0 to this bit has no effect Writing a 1 to this bit will lock updating Value Description 0 The CCBx PERB PGVB PGOB and SWAPBx buffer registers valu...

Page 841: ...mplete This bit is set when the synchronization of WAVE register between clock domains is started Bit 5 PATT PATT Synchronization Busy This bit is cleared when the synchronization of PATTERN register...

Page 842: ...ST bit between the clock domains is complete This bit is set when the synchronization of SWRST bit between clock domains is started Bits 8 9 10 11 CCn Compare Capture Channel x Synchronization Busy Th...

Page 843: ...x event is used as synchronous event Bits 23 16 BLANKVAL 7 0 Recoverable Fault n Blanking Value These bits determine the duration of the blanking of the fault input source Activation and edge selectio...

Page 844: ...LTn flag rises on each local maximun detection 0x6 DERIV0 On rising edge of a valid recoverable Fault n capture counter value on channel selected by CHSEL 1 0 INTFLAG FAULTn flag rises on each local m...

Page 845: ...ition 1 The recoverable Fault n input is disabled when output signal is at inactive level CMPx 0 Bit 3 KEEP Recoverable Fault n Keep Setting this bit enables the Fault n keep action Value Description...

Page 846: ...Bits 23 16 DTLS 7 0 Dead time Low Side Outputs Value This register holds the number of GCLK_TCC clock cycles for the dead time low side Bits 1 0 OTMX 1 0 Output Matrix These bits define the matrix rou...

Page 847: ...t input line is configured as a synchronous event this value must be 0x0 Bits 27 24 FILTERVAL0 3 0 Non Recoverable Fault Input 0 Filter Value These bits define the filter value applied on TCE0 event i...

Page 848: ...escription 0 Non recoverable fault tri state the output 1 Non recoverable faults set the output to NRVx level Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2...

Page 849: ...n this bit is set OCD fault protection is disabled and OCD break request will not trigger a fault Value Description 0 No faults are generated when TCC is halted in debug mode 1 A non recoverable fault...

Page 850: ...or end of counter cycle depending of CNTSEL 1 0 settings Value Description 0 Counter cycle output event is disabled and will not be generated 1 Counter cycle output event is enabled and will be gener...

Page 851: ...These bits define the action the TCC will perform on TCE1 event input Value Name Description 0x0 OFF Event action disabled 0x1 RETRIGGER Start restart or re trigger TC on event 0x2 DIR asynch Directi...

Page 852: ...h capture x incoming event is enabled These bits are used to enable match or capture input events to the CCx channel of TCC Value Description 0 Incoming events are disabled 1 Incoming events are enabl...

Page 853: ...r the Recoverable Fault B Interrupt Disable Enable bit which disables the Recoverable Fault B interrupt Value Description 0 The Recoverable Fault B interrupt is disabled 1 The Recoverable Fault B inte...

Page 854: ...a 0 to this bit has no effect Writing a 1 to this bit will clear the Retrigger Interrupt Disable Enable bit which disables the Retrigger interrupt Value Description 0 The Retrigger interrupt is disab...

Page 855: ...a 0 to this bit has no effect Writing a 1 to this bit will clear the Non Recoverable Fault x Interrupt Disable Enable bit which disables the Non Recoverable Fault x interrupt Value Description 0 The N...

Page 856: ...set the Recoverable Fault B Interrupt Disable Enable bit which enables the Recoverable Fault B interrupt Value Description 0 The Recoverable Fault B interrupt is disabled 1 The Recoverable Fault B int...

Page 857: ...ing a 0 to this bit has no effect Writing a 1 to this bit will set the Retrigger Interrupt Disable Enable bit which enables the Retrigger interrupt Value Description 0 The Retrigger interrupt is disab...

Page 858: ...g a 0 to this bit has no effect Writing a 1 to this bit will set the Non Recoverable Fault x Interrupt Disable Enable bit which enables the Non Recoverable Fault x interrupt Value Description 0 The No...

Page 859: ...lt B occurs Writing a 0 to this bit has no effect Writing a 1 to this bit clears the Recoverable Fault B interrupt flag Bit 11 DFS Debug Fault State Interrupt Flag This flag is set on the next CLK_TCC...

Page 860: ...rupt Flag This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx register contain a valid capture value Writing a 0 to one of these bits has no effect Wr...

Page 861: ...N bit is low If software halt command is enabled FAULTB HALT SW clearing this bit will release the timer counter Bit 12 FAULTA Recoverable Fault A State This bit is set by hardware as soon as recovera...

Page 862: ...ns Bit 0 STOP Stop This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One Shot operation mode is enabled CTRLBSET ONESHOT 1 This bit is clear on the next...

Page 863: ...r from BOTTOM the timer counter restart command must be executed before clearing the corresponding STATEx bit For further details on timer counter commands refer to available commands description CTRL...

Page 864: ...Bit 15 14 13 12 11 10 9 8 COUNT 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0...

Page 865: ...R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 8 9 10 11 12 13 14 15 PGVn Pattern Generation Output Value This register holds the values of pattern for each waveform output Bits 0 1 2 3 4 5 6 7 PGEn Patte...

Page 866: ...able the period circular buffer option When the bit is set the PER register value is copied back into the PERB register on UPDATE condition Bits 5 4 RAMP 1 0 Ramp Operation These bits select Ramp oper...

Page 867: ...8 19 POLn Channel Polarity x Setting these bits enables the output polarity in single slope and dual slope PWM operations Value Name Description 0 single slope PWM waveform generation Compare output i...

Page 868: ...he value of the period register Note When the TCC is configured as 16 or 24 bit timer counter the excess bits are read zero Note This bit field occupies the MSB of the register m is dependent on the R...

Page 869: ...CTRLA RESOLUTION Bits n 0 0x0 NONE 0x1 DITH4 3 0 0x2 DITH5 4 0 0x3 DITH6 5 0 depicted Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 869...

Page 870: ...Read Synchronized Bit 31 30 29 28 27 26 25 24 CC 25 18 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CC 17 10 Access R W R W R W R W R W R W R W R W Reset 0...

Page 871: ...PWM pulse width every 64 PWM frames Note This bit field consists of the n LSB of the register n is dependent on the value of the Resolution bits in the Control A register CTRLA RESOLUTION CTRLA RESOL...

Page 872: ...0 0 0 Bits 8 9 10 11 12 13 14 15 PGVBn Pattern Generation Output Value Buffer This register is the buffer for the PGV register If double buffering is used valid content in this register is copied to t...

Page 873: ...ied to PER register on UPDATE condition Note When the TCC is configured as 16 or 24 bit timer counter the excess bits are read zero Note This bit field occupies the MSB of the register 31 m m is depen...

Page 874: ...CTRLA RESOLUTION Bits n 0 0x0 NONE 0x1 DITH4 3 0 0x2 DITH5 4 0 0x3 DITH6 5 0 depicted Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 874...

Page 875: ...ves as the buffer for the associated compare or capture registers CCx Accessing this register using the CPU or DMA will affect the corresponding CCBUFVx status bit Note When the TCC is configured as 1...

Page 876: ...CTRLA RESOLUTION Bits n 0 0x0 NONE 0x1 DITH4 3 0 0x2 DITH5 4 0 0x3 DITH6 5 0 depicted Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 876...

Page 877: ...140 3 Provides a 32 bit random number every 84 clock cycles 37 3 Block Diagram Figure 37 1 TRNG Block Diagram MCLK User Interface Entropy Source Control Logic TRNG Interrupt Controller APB Event Cont...

Page 878: ...he CPU is halted in debug mode the TRNG continues normal operation If the TRNG is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar improper ope...

Page 879: ...INTFLAG register is set when the interrupt condition occurs Each interrupt can be individually enabled by writing a 1 to the corresponding bit in the Interrupt Enable Set INTENSET register and disabl...

Page 880: ...elated Links EVSYS Event System on page 570 37 6 5 Sleep Mode Operation The Run in Standby bit in Control A register CTRLA RUNSTDBY controls the behavior of the TRNG during standby sleep mode When thi...

Page 881: ...e registers require synchronization when read and or written Synchronization is denoted by the Read Synchronized and or Write Synchronized property in each individual register description Optional wri...

Page 882: ...tandby This bit controls how the ADC behaves during standby sleep mode Value Description 0 The TRNG is halted during standby sleep mode 1 The TRNG is not stopped in standby sleep mode Bit 1 ENABLE Ena...

Page 883: ...it indicates whether the Data Ready event output is enabled or not and an output event will be generated when a new random value is completed Value Description 0 Data Ready event output is disabled an...

Page 884: ...0x08 Reset 0x00 Property PAC Write Protection Bit 7 6 5 4 3 2 1 0 DATARDY Access R W Reset 0 Bit 0 DATARDY Data Ready Interrupt Enable Writing a 1 to this bit will clear the Data Ready Interrupt Enabl...

Page 885: ...0x09 Reset 0x00 Property PAC Write Protection Bit 7 6 5 4 3 2 1 0 DATARDY Access R W Reset 0 Bit 0 DATARDY Data Ready Interrupt Enable Writing a 1 to this bit will set the Data Ready Interrupt Enable...

Page 886: ...Y Data Ready This flag is set when a new random value is generated and an interrupt will be generated if INTENCLR SET DATARDY 1 This flag is cleared by writing a 1 to the flag or by reading the DATA r...

Page 887: ...Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA 15 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA 7 0 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0...

Page 888: ...of repetition for 192 bit keys 14 rounds of repetition for 256 bit keys 38 2 Features Compliant with FIPS Publication 197 Advanced Encryption Standard AES 128 192 256 bit cryptographic key supported E...

Page 889: ...nds ENCRYPTION ROUND PLAINTEXT FINAL ROUND CIPHERTEXT ENCRYPTION Nr 1 rounds ADD ROUND KEY INV SHIFT ROWS INV SUBBYTES ADD ROUND KEY INV MIX COLUMNS INV SHIFT ROWS INV SUBBYTES ADD ROUND KEY DE CRYPTI...

Page 890: ...equest lines one for input data and one for output data They are both connected to the DMA Controller DMAC These DMA request triggers will be acknowledged by the DMAC ACK signals Using the AES DMA req...

Page 891: ...byte of the state is combined with the round key using bitwise XOR Rounds SubBytes A non linear substitution step where each byte is replaced with another according to a lookup table ShiftRows A tran...

Page 892: ...28 bit authentication data needs to be programmed The Initialization Vector is used in the initial step in the encryption of a message and in the corresponding decryption of the message The Initializa...

Page 893: ...n Complete bit in the Interrupt Flag Register INTFLAG ENCCMP raises If Encryption Complete interrupt has been enabled the interrupt line of the AES is activated 1 7 When the software reads one of the...

Page 894: ...vailable unless AES module has performed at least one encryption process prior to operating in the decryption mode In general the last Nk words of the expanded key must be available before decryption...

Page 895: ...ine processes data packets after the AES operation GCM provides assurance of the confidentiality of data through the AES Counter mode of operation for encryption Authenticity of the confidential data...

Page 896: ...IPH K Ciphertext1 Ciphertext2 Plaintext1 Plaintext2 Encryption Authentication GF128Mult H GF128Mult H Auth Data1 GF128Mult H Len A Len C GF128Mult H Auth Tag Atmel SAM L22G L22J L22N DATASHEET Atmel 4...

Page 897: ...on Header Processing Configure CTRLA register as follows 1 1 CTRLA STARTMODE as Manual 1 2 CTRLA CIPHER as Encryption 1 3 CTRLA KEYSIZE as per the key used 1 4 CTRLA AESMODE as GCM 1 5 CTRLA CTYPE as...

Page 898: ...Continue 3 to 6 till the input of plain text to get the cipher text and the Hash keys At the last input set CTRLB EOM Write last indata to DATA reg Set CTRLB START as 1 Wait for INTFLAG ENCCMP to be s...

Page 899: ...set CTRLB GFMUL and CTRLB START as 1 Wait for INTFLAG GFMCMP to be set AES Hardware generates final GHASH value in GHASHx register Tag Generation Configure CTRLA 1 1 Set CTRLA ENABLE to 0 1 2 Set CTRL...

Page 900: ...31 24 10 KEYWORDx1 7 0 KEYWORD 7 0 11 15 8 KEYWORD 15 8 12 23 16 KEYWORD 23 16 13 31 24 KEYWORD 31 24 14 KEYWORDx2 7 0 KEYWORD 7 0 15 15 8 KEYWORD 15 8 16 23 16 KEYWORD 23 16 17 31 24 KEYWORD 31 24 18...

Page 901: ...INTVECT 23 16 47 31 24 INTVECT 31 24 48 INTVECTx3 7 0 INTVECT 7 0 49 15 8 INTVECT 15 8 4A 23 16 INTVECT 23 16 4B 31 24 INTVECT 31 24 0x4C 0x5B Reserved 0x5C HASHKEYx0 7 0 HASHKEY 7 0 0x5D 15 8 HASHKEY...

Page 902: ...31 24 38 8 Register Description Registers can be 8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition the 8 bit quarters and 16 bit halves of a 32 bit register and the 8 bit...

Page 903: ...0 0 0 0 Bits 19 16 CTYPE 3 0 Countermeasure type Value Name Description XXX0 CTYPE1 disabled Countermeasure1 disabled XXX1 CTYPE1 enabled Countermeasure1 enabled XX0X CTYPE2 disabled Countermeasure2 d...

Page 904: ...tion Decryption 1 192 bit Key 192 bit Key for Encryption Decryption 2 256 bit Key 256 bit Key for Encryption Decryption 3 Reserved Reserved Bits 7 5 CFBS 2 0 Cipher Feedback Block Size Value Name Desc...

Page 905: ...0 The peripheral is disabled 1 The peripheral is enabled Bit 0 SWRST Software Reset Writing a 0 to this bit has no effect Writing a 1 to this bit resets all registers in the AES module to their initi...

Page 906: ...Value Description 0 No action 1 Setting this bit generates final GHASH value for the message Bit 1 NEWMSG New Message This bit is used in cipher block chaining CBC cipher feedback CFB and output feedb...

Page 907: ...Complete interrupt Value Description 0 The GF Multiplication Complete interrupt is disabled 1 The GF Multiplication Complete interrupt is enabled Bit 0 ENCCMP Encryption Complete Interrupt Enable Wri...

Page 908: ...Complete interrupt Value Description 0 The GF Multiplication Complete interrupt is disabled 1 The GF Multiplication Complete interrupt is enabled Bit 0 ENCCMP Encryption Complete Interrupt Enable Writ...

Page 909: ...rom the GHASHx register Bit 0 ENCCMP Encryption Complete This flag is cleared by writing a 1 to it This flag is set when encryption decryption is complete and valid data is available on the Data Regis...

Page 910: ...0 0 Bits 1 0 INDATAPTR 1 0 Input Data Pointer Writing to this field changes the value of the input data pointer which determines which of the four data registers is written to read from when the next...

Page 911: ...eset 0 Bit 0 DBGRUN Debug Run Writing a 0 to this bit causes the AES to halt during debug mode Writing a 1 to this bit allows the AES to continue normal operation during debug mode This bit can only b...

Page 912: ...0 KEYWORD 7 0 Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 31 0 KEYWORD 31 0 Key Word Value The four six eight 32 bit Key Word registers set the 128 bit 192 bit 256 bit cryptographic key used fo...

Page 913: ...R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 DATA 31 0 Data Value A write to or read from this register corresponds to a write to or read from one of the four data registers The four 3...

Page 914: ...NTVECT 31 0 Initialization Vector Value The four 32 bit Initialization Vector registers INTVECTx set the 128 bit Initialization Vector data block that is used by some modes of operation as an addition...

Page 915: ...0 0 Bit 15 14 13 12 11 10 9 8 HASHKEY 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 HASHKEY 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit...

Page 916: ...11 10 9 8 GHASH 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GHASH 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 GHASH 31 0 Galois...

Page 917: ...et 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CIPLEN 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CIPLEN 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0...

Page 918: ...W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RANDSEED 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RANDSEED 7 0 Access R W R W R W R W R W...

Page 919: ...the same address are used in the same direction The CPU or DMA Controller can then read write one data buffer while the USB module writes reads from the other buffer This gives double buffered communi...

Page 920: ...mode where its source clock is running The interrupts can wake up the device from sleep modes Events connected to the event system can trigger other operations in the system without exiting sleep mode...

Page 921: ...odically serviced by the CPU through interrupts or similar improper operation or data loss may result during debugging 39 5 8 Register Access Protection Registers with write access can be optionally w...

Page 922: ...sic operation of the device mode Related Links NVM Software Calibration Area Mapping on page 41 39 6 2 USB Device Operations This section gives an overview of the USB module device operation during no...

Page 923: ...r of interrupts and software intervention required to manage higher level USB transfers Multi packet transfer is identical to the IN and OUT transactions described below unless otherwise noted in this...

Page 924: ...is successfully received an ACK handshake is returned to the host and the number of received data bytes excluding the CRC is written to the Byte Count PCKSIZE BYTE_COUNT If the number of received data...

Page 925: ...ved an ACK handshake is returned to the host if the endpoint is not isochronous and the number of received data bytes excluding CRC is written to PCKSIZE BYTE_COUNT If the number of received data byte...

Page 926: ...times the USB module returns to idle and waits for the next token packet If an ACK handshake is successfully received EPSTATUS BK1RDY is cleared EPINTFLAG TRCPT1 is set and EPSTATUS DTGLIN is toggled...

Page 927: ...Endpoint n OUT EPCFG EPTYPE0 Isochronous OUT PCKSIZE SIZE 512 39 6 2 13 Suspend State and Pad Behavior The following figure Pad Behavior illustrates the behavior of the USB pad in device mode In Idle...

Page 928: ...wer Management Interrupt bit in INTFLAG INTFLAG LPMSUSP bit which indicates that the USB transceiver is suspended reducing power consumption This suspend occurs 9 microseconds after the LPM transactio...

Page 929: ...SC INTFLAG LPMNYET INTENSET UPRSM INTFLAG UPRSM INTENSET EORSM INTFLAG EORSM INTENSET WAKEUP INTFLAG WAKEUP INTFLAG INTENSET EORST INTFLAG EORST INTENSET SOF INTFLAG SOF INTENSET MSOF INTFLAGA MSOF US...

Page 930: ...D 31 24 0x28 PADCAL 7 0 TRANSN 1 0 TRANSP 4 0 0x29 15 8 TRIM 2 0 TRANSN 4 2 39 7 2 Device Summary Table 39 1 General Device Registers Offset Name Bit Pos 0x04 Reserved 0x05 Reserved 0x06 Reserved 0x07...

Page 931: ...0x03 31 24 ADD 31 24 0x04 PCKSIZE 7 0 BYTE_COUNT 7 0 0x05 15 8 MULTI_PACKET_SIZE 1 0 BYTE_COUNT 13 8 0x06 23 16 MULTI_PACKET_SIZE 9 2 0x07 31 24 AUTO_ZLP SIZE 2 0 MULTI_PACKET_SIZE 13 10 0x08 EXTREG...

Page 932: ...r Write Synchronized property in each individual register description Optional write protection by the Peripheral Access Controller PAC is denoted by the PAC Write Protection property in each individu...

Page 933: ...n the operation is complete This bit is Write Synchronized Value Description 0 The peripheral is disabled or being disabled 1 The peripheral is enabled or being enabled Bit 0 SWRST Software Reset Writ...

Page 934: ...k domains is complete This bit is set when the synchronization of ENABLE register between clock domains is started Bit 0 SWRST Synchronization Software Reset status bit This bit is cleared when the sy...

Page 935: ...s define the memory priority access during the endpoint or pipe read write data operation Refer to SRAM Quality of Service Bits 1 0 CQOS 1 0 Configuration Quality of Service These bits define the memo...

Page 936: ...state of the finite state machine of the USB controller Value Name Description 0x01 OFF L3 Corresponds to the powered off disconnected and disabled state 0x02 ON L0 Corresponds to the Idle and Active...

Page 937: ...Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DESCADD 15 8 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DESCADD 7 0 Access R W R W R W R W R W R W R W R W Reset 0...

Page 938: ...N 4 2 Access R W R W R W R W R W R W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TRANSN 1 0 TRANSP 4 0 Access R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 Bits 14 12 TRIM 2 0 Trim bits for DP DM These bi...

Page 939: ...mode of the NAK This bit is not synchronized Value Description 0 The handshake packet reports the status of the USB transaction 1 A NAK handshake is answered for each USB transaction regardless of the...

Page 940: ...e Description 0 Writing a zero to this bit has no effect 1 Writing a one to this bit will generate an upstream resume to the host for a remote wakeup Bit 0 DETACH Detach Value Description 0 The device...

Page 941: ...a USB reset is received Value Description 0 Writing a zero will deactivate the DADD field USB device address and return the device to default address 0 1 Writing a one will activate the DADD field US...

Page 942: ...define the current line state DP DM LINESTATE 1 0 USB Line Status 0x0 SE0 RESET 0x1 FS J or LS K State 0x2 FS K or LS J State Bits 3 2 SPEED 1 0 Speed Status These bits define the current speed used...

Page 943: ...SOF interrupt bit are updated at the same time Bits 13 3 FNUM 10 0 Frame Number These bits are cleared upon receiving a USB reset These bits are updated with the frame number information as provided f...

Page 944: ...t Suspend interrupt is disabled 1 The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated when the Link Power Management Suspend interrupt Flag is set Bit 8 L...

Page 945: ...d Of Resume interrupt is disabled 1 The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of Resume interrupt Flag is set Bit 4 WAKEUP Wake Up Interrupt Enable...

Page 946: ...st will be generated when the Start of Frame interrupt Flag is set Bit 0 SUSPEND Suspend Interrupt Enable Writing a zero to this bit has no effect Writing a one to this bit will clear the Suspend Inte...

Page 947: ...nterrupt request Value Description 0 The Link Power Management Suspend interrupt is disabled 1 The Link Power Management Suspend interrupt is enabled Bit 8 LPMNYET Link Power Management Not Yet Interr...

Page 948: ...ne to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt request Value Description 0 The Wake Up interrupt is disabled 1 The Wake Up interrupt is enabled Bit 3 E...

Page 949: ...ne to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request Value Description 0 The Suspend interrupt is disabled 1 The Suspend interrupt is enabled Atmel S...

Page 950: ...lag is cleared by writing a one to the flag This flag is set when the USB module acknowledges a Link Power Management Transaction handshake is NYET and will generate an interrupt if INTENCLR SET LPMNY...

Page 951: ...t when a USB End of Reset has been detected and will generate an interrupt if INTENCLR SET EORST is one Writing a zero to this bit has no effect Bit 2 SOF Start of Frame Interrupt Flag This flag is cl...

Page 952: ...R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15 0 EPINT 15 0 EndPoint Interrupt The flag EPINT n is set when an interrupt is triggered by the EndPoint n See EPINTFLAGn register in the device EndPoint se...

Page 953: ...nfigured as Interrupt IN 0x5 Bank1 is enabled and configured as Dual Bank OUT Endpoint type is the same as the one defined in EPTYPE0 0x6 0x7 Reserved Bits 2 0 EPTYPE0 2 0 Endpoint Type for OUT direct...

Page 954: ...uest Writing a zero to this bit has no effect Writing a one to this bit will clear EPSTATUS STALLRQ1 bit Bit 4 STALLRQ0 STALL bank 0 Request Writing a zero to this bit has no effect Writing a one to t...

Page 955: ...bank 1 Writing a zero to this bit has no effect Writing a one to this bit will set EPSTATUS STALLRQ1 bit Bit 4 STALLRQ0 STALL Request bank 0 Writing a zero to this bit has no effect Writing a one to...

Page 956: ...Y will set this bit Value Description 0 The bank number 0 is not ready For IN direction Endpoints the bank is not yet filled in For Control OUT direction Endpoints the bank is empty 1 The bank number...

Page 957: ...ng a zero to the bit EPSTATUSCLR DTGLINCLR will clear this bit Writing a one to the bit EPSTATUSSET DTGLINSET will set this bit Value Description 0 The PID of the next expected IN transaction will be...

Page 958: ...d will generate an interrupt if EPINTENCLR SET STALL0 is one EPINTFLAG STALL0 is set for a single bank OUT endpoint or double bank IN OUT endpoint when current bank is 0 Writing a zero to this bit has...

Page 959: ...s set when a Transfer Complete occurs and will generate an interrupt if EPINTENCLR SET TRCPT1 is one EPINTFLAG TRCPT1 is set for a single bank IN endpoint or double bank IN OUT endpoint when current b...

Page 960: ...L0 Transmit STALL 0 Interrupt Enable Writing a zero to this bit has no effect Writing a one to this bit will clear the Transmit Stall 0 Interrupt Enable bit and disable the corresponding interrupt req...

Page 961: ...quest will be generated when the Transfer Fail 0 Interrupt Flag is set Bit 1 TRCPT1 Transfer Complete 1 Interrupt Enable Writing a zero to this bit has no effect Writing a one to this bit will clear t...

Page 962: ...bled 1 The Transmit Stall 1 interrupt is enabled Bit 5 STALL0 Transmit Stall 0 Interrupt Enable Writing a zero to this bit has no effect Writing a one to this bit will enable the Transmit bank 0 Stall...

Page 963: ...nable the Transfer Complete 0 interrupt Value Description 0 The Transfer Complete bank 1 interrupt is disabled 1 The Transfer Complete bank 1 interrupt is enabled Bit 0 TRCPT0 Transfer Complete bank 0...

Page 964: ...es Descriptor E0 STATUS_BK Reserved Bank0 0x000 0x004 0x008 0x00A 0x00B Reserved PCKSIZE ADDR STATUS_BK Reserved Bank1 0x010 0x014 0x018 0x01A 0x01B EXTREG PCKSIZE ADDR Descriptor En STATUS_BK Reserve...

Page 965: ...14 13 12 11 10 9 8 ADDR 15 8 Access R W R W R W R W R W R W R W R W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 ADDR 7 0 Access R W R W R W R W R W R W R W R W Reset x x x x x x x x Bits 31 0 ADDR 31 0...

Page 966: ...R W R W R W R W Reset 0 0 0 0 0 0 0 x Bit 31 AUTO_ZLP Automatic Zero Length Packet This bit defines the automatic Zero Length Packet mode of the endpoint When enabled the USB module will manage the ZL...

Page 967: ...For OUT endpoints MULTI_PACKET_SIZE holds the total data size for the complete transfer This value must be a multiple of the maximum packet size Bits 13 0 BYTE_COUNT 13 0 Byte Count These bits define...

Page 968: ...LES Description VARIABLE 3 0 bLinkState 1 VARIABLE 7 4 BESL 2 VARIABLE 8 bRemoteWake 1 VARIABLE 10 9 Reserved 1 For a definition of LPM Token bRemoteWake and bLinkState fields refer to Table 2 3 in th...

Page 969: ...chronous OUT transfer an overrun condition has occurred For IN transfer this bit is not valid EPSTATUS TRFAIL0 and EPSTATUS TRFAIL1 should reflect the flow errors Value Description 0 No Error Flow det...

Page 970: ...be filtered to remove spikes An optional sequential module can be enabled The inputs of the sequential module are individually controlled by two independent adjacent LUT LUT0 LUT1 LUT2 LUT3 etc outpu...

Page 971: ...tal input Input to lookup table Refer to I O Multiplexing and Considerations for details on the pin mapping for this peripheral One signal can be mapped on several pins Related Links I O Multiplexing...

Page 972: ...ug Operation When the CPU is halted in debug mode the CCL continues normal operation If the CCL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or sim...

Page 973: ...CCL is enabled by writing a 1 to the Enable bit in the Control register CTRL ENABLE The CCL is disabled by writing a 0 to CTRL ENABLE Each LUT is enabled by writing a 1 to the Enable bit in the LUT C...

Page 974: ...s MASK When a LUT input is masked LUTCTRLx INSELy MASK the corresponding TRUTH input IN is internally tied to zero as shown in this figure Figure 40 3 Masked Input Selection Internal Feedback Inputs F...

Page 975: ...rom the Event System can be used as input selection as shown in Figure 40 6 For each LUT one event input line is available and can be selected on each LUT input Before enabling the event selection by...

Page 976: ...ed to the pin as shown in the figure below Figure 40 7 I O Pin Input Selection Analog Comparator Inputs AC The AC outputs can be used as input source for the LUT LUTCTRLx INSELy AC The analog comparat...

Page 977: ...stance_Number IN 1 TC_Instance_Number Where N represents the LUT number and i represents the LUT input index i 0 1 2 Before selecting the waveform outputs the TC must be configured first Figure 40 9 T...

Page 978: ...r on page 538 GCLK Generic Clock Controller on page 121 AC Analog Comparators on page 1030 TC Timer Counter on page 743 TCC Timer Counter for Control Applications on page 795 SERCOM Serial Communicati...

Page 979: ...responding internal Edge Detector logic is cleared one APB clock cycle later Figure 40 13 Edge Detector 40 6 2 7 Sequential Logic Each LUT pair can be connected to internal sequential logic D flip flo...

Page 980: ...e 40 15 Figure 40 15 JK Flip Flop When the even LUT is disabled LUTCTRL2x ENABLE 0 the flip flop is asynchronously cleared The reset command R is kept enabled for one APB clock cycle In all other case...

Page 981: ...refreshed as shown in Table 40 5 Table 40 5 RS latch Characteristics S R OUT 0 0 Hold state no change 0 1 Clear 1 0 Set 1 1 Forbidden state 40 6 3 Events The CCL can generate the following output even...

Page 982: ...nabled in all sleep modes If CTRL RUNSTDBY 0 the GCLK_CCL will be disabled If the Filter Edge Detector or Sequential logic are enabled the LUT output will be forced to zero in STANDBY mode In all othe...

Page 983: ...0 0x16 23 16 LUTEO LUTEI INVEI INSEL2 3 0 0x17 31 24 TRUTH 7 0 40 8 Register Description Registers can be 8 16 or 32 bits wide Atomic 8 16 and 32 bit accesses are supported In addition the 8 bit quart...

Page 984: ...p Mode Operation Value Description 0 Generic clock is not required in standby sleep mode 1 Generic clock is required in standby sleep mode Bit 1 ENABLE Enable Value Description 0 The peripheral is dis...

Page 985: ...W Reset 0 0 0 0 Bits 3 0 SEQSEL 3 0 Sequential Selection These bits select the sequential configuration Sequential Selection Value Name Description 0x0 DISABLE Sequential logic is disabled 0x1 DFF D f...

Page 986: ...0 0 0 Bit 7 6 5 4 3 2 1 0 EDGESEL FILTSEL 1 0 ENABLE Access R W R W R W R W Reset 0 0 0 0 Bits 31 24 TRUTH 7 0 Truth Table These bits define the value of truth logic as a function of inputs IN 2 0 Bit...

Page 987: ...0 The LUT is disabled 1 The LUT is enabled Bits 19 16 15 12 11 8 INSELx LUT Input x Source Selection These bits select the LUT input x source Value Name Description 0x0 MASK Masked input 0x1 FEEDBACK...

Page 988: ...igured for 8 10 or 12 bit results ADC conversion results are provided left or right adjusted which eases calculation when the result is represented as a signed value It is possible to use DMA to move...

Page 989: ...pe VREFA Analog input External reference voltage A VREFB Analog input External reference voltage B AIN 19 0 Analog input Analog input channels Note One signal can be mapped on several pins Related Lin...

Page 990: ...registers will require synchronization between the clock domains Refer to Synchronization for further details Related Links Synchronization on page 999 Peripheral Clock Masking on page 145 GCLK Generi...

Page 991: ...er to reduce the conversion time see Conversion Timing and Sampling Rate The ADC has an oversampling with decimation option that can extend the resolution to 16 bits The input values can be either int...

Page 992: ...N bit in the Interrupt Flag Status and Clear register INTFLAG OVERRUN To enable one of the available interrupts sources the corresponding bit in the Interrupt Enable Set register INTENSET must be writ...

Page 993: ...starts after the software or event start are synchronized with the GCLK_ADC clock The input channel is sampled in the first half CLK_ADC period Figure 41 3 ADC Timing for One Conversion in 12 bit Reso...

Page 994: ...be 1MSPS 4 12 16MHz As the minimal division factor of the prescaler is 2 GCLK_ADC must be 32MHz 41 6 2 9 Accumulation The result from multiple consecutive conversions can be accumulated The number of...

Page 995: ...ht shift described above and an additional right shift that must be specified by writing to the Adjusting Result Division Coefficient field in AVGCTRL AVGCTRL ADJRES as described in Table 41 2 Note To...

Page 996: ...64 0x6 2 0x1 16 bits 44 256 0x8 4 0x0 41 6 2 12 Automatic Sequences The ADC has the ability to automatically sequence a series of conversions This means that each time the ADC receives a start of conv...

Page 997: ...error is defined as the deviation of the actual ADC transfer function from an ideal straight line at zero input voltage The offset error cancellation is handled by the Offset Correction register OFFSE...

Page 998: ...esent Note that interrupts must be globally enabled for interrupt requests to be generated Refer to Nested Vector Interrupt Controller for details Related Links Nested Vector Interrupt Controller on p...

Page 999: ...STANDBY 0 1 1 Run in all sleep modes on request except STANDBY 1 0 1 Run in all sleep modes 1 1 1 Run in all sleep modes on request 41 6 7 Synchronization Due to asynchronicity between the main clock...

Page 1000: ...Register Synchronization on page 116 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 1000...

Page 1001: ...DE 2 0 0x0C AVGCTRL 7 0 ADJRES 2 0 SAMPLENUM 3 0 0x0D SAMPCTRL 7 0 OFFCOMP SAMPLEN 5 0 0x0E WINLT 7 0 WINLT 7 0 0x0F 15 8 WINLT 15 8 0x10 WINUT 7 0 WINUT 7 0 0x11 15 8 WINUT 15 8 0x12 GAINCORR 7 0 GAI...

Page 1002: ...accessed directly Some registers are optionally write protected by the Peripheral Access Controller PAC Optional PAC write protection is denoted by the PAC Write Protection property in each individual...

Page 1003: ...Description 0 The ADC is always on if enabled 1 The ADC is enabled when a peripheral is requesting the ADC conversion The ADC is disabled if no peripheral is requesting it Bit 6 RUNSTDBY Run in Stand...

Page 1004: ...SWRST will always take precedence meaning that all other writes in the same write operation will be discarded Due to synchronization there is a delay from writing CTRLA SWRST until the reset is comple...

Page 1005: ...ipheral clock Value Name Description 0x0 DIV2 Peripheral clock divided by 2 0x1 DIV4 Peripheral clock divided by 4 0x2 DIV8 Peripheral clock divided by 8 0x3 DIV16 Peripheral clock divided by 16 0x4 D...

Page 1006: ...increase the start up time of the reference Value Description 0 Reference buffer offset compensation is disabled 1 Reference buffer offset compensation is enabled Bits 3 0 REFSEL 3 0 Reference Selecti...

Page 1007: ...t is enabled or not and an output event will be generated when the conversion result is available Value Description 0 Result Ready event output is disabled and an event will not be generated 1 Result...

Page 1008: ...nd new conversion will not be triggered on any incoming event 1 A flush and new conversion will be triggered on any incoming event Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Da...

Page 1009: ...erated when the Window Monitor interrupt flag is set Bit 1 OVERRUN Overrun Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to this bit will clear the Overrun Interrupt Enable bit wh...

Page 1010: ...pt Value Description 0 The Window Monitor interrupt is disabled 1 The Window Monitor interrupt is enabled Bit 1 OVERRUN Overrun Interrupt Enable Writing a 0 to this bit has no effect Writing a 1 to th...

Page 1011: ...OVERRUN Overrun This flag is cleared by writing a 1 to the flag This flag is set if RESULT is written before the previous value has been read by CPU and an interrupt request will be generated if INTEN...

Page 1012: ...Sequence busy This bit is set when the sequence start This bit is clear when the last conversion in a sequence is done Bits 4 0 SEQSTATE 4 0 Sequence State These bit fields are the pointer of sequence...

Page 1013: ...AIN2 ADC AIN2 pin 0x03 AIN3 ADC AIN3 pin 0x04 AIN4 ADC AIN4 pin 0x05 AIN5 ADC AIN5 pin 0x06 AIN6 ADC AIN6 pin 0x07 AIN7 ADC AIN7 pin 0x08 0x17 Reserved 0x18 GND Internal ground 0x19 0x1F Reserved Bit...

Page 1014: ...13 ADC AIN13 pin 0x0E AIN14 ADC AIN14 pin 0x0F AIN15 ADC AIN15 pin 0x10 AIN16 ADC AIN16 pin 0x11 AIN17 ADC AIN17 pin 0x12 AIN18 ADC AIN18 pin 0x13 AIN19 ADC AIN19 pin 0x14 0x17 Reserved 0x18 Reserved...

Page 1015: ...version Result Resolution These bits define whether the ADC completes the conversion 12 10 or 8 bit result resolution Value Name Description 0x0 12BIT 12 bit result 0x1 16BIT For averaging mode output...

Page 1016: ...s left adjusted in the RESULT register The high byte of the 12 bit result will be present in the upper part of the result register Writing this bit to zero default will right adjust the value in the R...

Page 1017: ...3 0 SAMPLENUM 3 0 Number of Samples to be Collected These bits define how many samples are added together The result will be available in the Result register RESULT Note if the result width increases...

Page 1018: ...to temperature or voltage drift This compensation increases the sampling time by three clock cycles This bit must be set to zero to validate the SAMPLEN value It s not possible to use OFFCOMP 1 and S...

Page 1019: ...s R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINLT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 WINLT 15 0 Window Lower Threshold If the wi...

Page 1020: ...s R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 WINUT 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 15 0 WINUT 15 0 Window Upper Threshold If the wi...

Page 1021: ...0 0 0 0 0 0 0 0 Bits 11 0 GAINCORR 11 0 Gain Correction Value If CTRLC CORREN 1 these bits define how the ADC conversion result is compensated for gain error before being written to the result regist...

Page 1022: ...FSETCORR 7 0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 11 0 OFFSETCORR 11 0 Offset Correction Value If CTRLC CORREN 1 these bits define how the ADC conversion result is compens...

Page 1023: ...fect Writing a 0 to this bit will have no effect Bit 0 FLUSH ADC Conversion Flush Writing a 1 to this bit will flush the ADC pipeline A flush will restart the ADC clock on the next peripheral clock ed...

Page 1024: ...controls the functionality when the CPU is halted by an external debugger This bit should be written only while a conversion is not ongoing Value Description 0 The ADC is halted when the CPU is halted...

Page 1025: ...s complete This bit is set when the synchronization of GAINCORR register between clock domains is started Bit 7 WINUT Window Monitor Lower Threshold Synchronization Busy This bit is cleared when the s...

Page 1026: ...is complete This bit is set when the synchronization of INPUTCTRL register between clock domains is started Bit 1 ENABLE ENABLE Synchronization Busy This bit is cleared when the synchronization of ENA...

Page 1027: ...of CTRLC LEFTADJ If the result is left adjusted CTRLC LEFTADJ the high byte of the result will be in bit position 15 8 while the remaining 4 bits of the result will be placed in bit locations 7 4 This...

Page 1028: ...R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SEQEN7 SEQEN6 SEQEN5 SEQEN4 SEQEN3 SEQEN2 SEQEN1 SEQEN0 Access R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 31 0 SEQENn Ena...

Page 1029: ...st be loaded from the NVM software calibration row into the CALIB register by software to achieve the specified accuracy The value must be copied only and must not be changed Bits 2 0 BIASCOMP 2 0 Bia...

Page 1030: ...These are called Comparator 0 COMP0 and Comparator 1 COMP1 They have identical behaviors but separate control registers The pair can be set in window mode to compare a signal to a voltage range instea...

Page 1031: ...1 0 Digital output Comparator outputs Refer to I O Multiplexing and Considerations for details on the pin mapping for this peripheral One signal can be mapped on several pins Related Links I O Multip...

Page 1032: ...inks PM Power Manager on page 188 42 5 4 DMA Not applicable 42 5 5 Interrupts The interrupt request lines are connected to the interrupt controller Using the AC interrupts requires the interrupt contr...

Page 1033: ...the negative input voltage is positive and 0 otherwise The individual comparators can be used independently normal mode or paired to form a window comparison window mode 42 6 2 Basic Operation 42 6 2...

Page 1034: ...to generate interrupts when the output toggles when the output changes from 0 to 1 rising edge when the output changes from 1 to 0 falling edge or at the end of the comparison An end of comparison int...

Page 1035: ...ted A single shot measurement can also be triggered by the Event System Setting the Comparator x Event Input bit in the Event Control Register EVCTRL COMPEIx enables triggering on incoming peripheral...

Page 1036: ...setting in their respective Comparator Control Registers COMPCTRLx SINGLE To physically configure the pair of comparators for window mode the same I O pin must be chosen as positive input for each co...

Page 1037: ...els One independent voltage channel is dedicated for each comparator The scaler of a comparator is enabled when the Negative Input Mux bit field in the respective Comparator Control register COMPCTRLx...

Page 1038: ...rol x register COMPCTRLx FLEN and is independent for each comparator Filtering is selectable from none 3 bit majority N 3 or 5 bit majority N 5 functions Any change in the comparator output is conside...

Page 1039: ...omparator interrupts are generated based on the conditions selected by the Interrupt Selection bit group in the Comparator Control registers COMPCTRLx INTSEL Window interrupts are generated based on t...

Page 1040: ...tandby sleep mode Each RUNSTDBY bit controls one comparator When the bit is zero the comparator is disabled during sleep but maintains its current configuration When the bit is one the comparator cont...

Page 1041: ...ly unless configured to wake the system from sleep Filtering is allowed with this configuration Figure 42 10 Single Shot SleepWalking GCLK_AC Comparator Output or Event Input Event tSTARTUP tSTARTUP 4...

Page 1042: ...TEN SPEED 1 0 0x17 31 24 OUT 1 0 FLEN 2 0 0x18 0x1F Reserved 0x20 SYNCBUSY 7 0 COMPCTRL1 COMPCTRL0 WINCTRL ENABLE SWRST 0x21 15 8 0x22 23 16 0x23 31 24 42 8 Register Description Registers can be 8 16...

Page 1043: ...n only be written when the peripheral is disabled Enable protection is denoted by the Enable Protected property in each individual register description Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E...

Page 1044: ...ator must also be enabled individually by the Enable bit in the Comparator Control register COMPCTRLn ENABLE Bit 0 SWRST Software Reset Writing a 0 to this bit has no effect Writing a 1 to this bit re...

Page 1045: ...has no effect Writing a 1 to STARTx starts a single shot comparison on COMPx if both the Single Shot and Enable bits in the Comparator x Control Register are 1 COMPCTRLx SINGLE and COMPCTRLx ENABLE If...

Page 1046: ...comparator x Bits 9 8 COMPEIx Comparator x Event Input Note that several actions can be enabled for incoming events If several events are connected to the peripheral the enabled action will be taken f...

Page 1047: ...f the Window 0 interrupt enable Writing a 0 to this bit has no effect Writing a 1 to this bit disables the Window 0 interrupt Value Description 0 The Window 0 interrupt is disabled 1 The Window 0 inte...

Page 1048: ...interrupt enable Writing a 0 to this bit has no effect Writing a 1 to this bit enables the Window 0 interrupt Value Description 0 The Window 0 interrupt is disabled 1 The Window 0 interrupt is enable...

Page 1049: ...a 1 to this bit clears the Window 0 interrupt flag Bits 1 0 COMPx Comparator x Reading this bit returns the status of the Comparator x interrupt flag If comparator x is not implemented COMPx always r...

Page 1050: ...signal if the window 0 mode is enabled Value Name Description 0x0 ABOVE Signal is above window 0x1 INSIDE Signal is inside window 0x2 BELOW Signal is below window 0x3 Reserved Bits 1 0 STATEx Comparat...

Page 1051: ...0 READY1 READY0 Access R R Reset 0 0 Bits 1 0 READYx Comparator x Ready This bit is cleared when the comparator x output is not ready This bit is set when the comparator x output is ready Atmel SAM L...

Page 1052: ...eset This bits controls the functionality when the CPU is halted by an external debugger Value Description 0 The AC is halted when the CPU is halted by an external debugger Any on going comparison wil...

Page 1053: ...comparator window 0 mode Value Name Description 0x0 ABOVE Interrupt on signal above window 0x1 INSIDE Interrupt on signal inside window 0x2 BELOW Interrupt on signal below window 0x3 OUTSIDE Interrup...

Page 1054: ...VALUE 5 0 Access R W R W R W R W R W R W Reset 0 0 0 0 0 0 Bits 5 0 VALUE 5 0 Scaler Value These bits define the scaling factor for channel n of the VDD voltage scaler The output voltage VSCALE is SCA...

Page 1055: ...e output selection for comparator n COMPCTRLn OUT can be written only while COMPCTRLn ENABLE is zero Note For internal use of the comparison results by the CCL this bit must be 0x1 or 0x2 These bits a...

Page 1056: ...for continuous mode COMPCTRLn SINGLE 0 COMPCTRLn HYST can be written only while COMPCTRLn ENABLE is zero This bit is not synchronized Value Description 0 Hysteresis is disabled 1 Hysteresis is enable...

Page 1057: ...x1 PIN1 I O pin 1 0x2 PIN2 I O pin 2 0x3 PIN3 I O pin 3 0x4 VSCALE VDD scaler 0x5 0x7 Reserved Bits 10 8 MUXNEG 2 0 Negative Input Mux Selection These bits select which input will be connected to the...

Page 1058: ...nly while COMPCTRLn ENABLE is zero These bits are not synchronized Value Description 0 Comparator n operates in continuous measurement mode 1 Comparator n operates in single shot mode Bit 1 ENABLE Ena...

Page 1059: ...is cleared when the synchronization of the CTRLA ENABLE bit between the clock domains is complete This bit is set when the synchronization of the CTRLA ENABLE bit between clock domains is started Bit...

Page 1060: ...ce CPU load and power consumption Figure 43 1 LCD Panel Segment Common Terminals Connections s e g m e n t 0 s e g m e n t 1 s e g m e n t 2 s e g m e n t 4 2 s e g m e n t 4 1 s e g m e n t 4 0 COM0...

Page 1061: ...face 43 4 Signal Description Signal Description Type LPx LCD Pin x COM or SEG terminal Analog output VLCD LCD Voltage Analog input or output One signal can be mapped to one of several pins Related Lin...

Page 1062: ...64 Synchronous and Asynchronous Clocks on page 116 43 5 4 DMA The DMA request lines are connected to the DMA Controller DMAC Using the SLCD DMA requests requires the DMA Controller to be configured fi...

Page 1063: ...signal Reference refresh signal Resistor String BIAS1 BIAS2 BIAS3 LCD Power Supply Macro VLCD Buffer Array BIAS1 BIAS2 BIAS3 43 6 Functional Description 43 6 1 Basic Operation 43 6 1 1 Initialization...

Page 1064: ...ry is accessible through APB and should be filled before the next frame starts A start of a new frame triggers copying the display memory into the shadow display memory A display memory refresh is thu...

Page 1065: ...their DC component is null By default the low power waveforms mode is enabled To select frame inversion mode write a zero in the Waveform Mode bit in Control A register CTRLA WMOD To select bit invers...

Page 1066: ...elect Waveform V0 V1 V2 Pixel Pixel V0 V1 V2 V2 V1 PixelOn V0 V1 V2 V2 V1 PixelOff V0 V1 V2 V2 V1 PixelOff V0 V1 V2 V2 V1 PixelOff COM Waveform Template SEG Waveform Template Voltage Level Definition...

Page 1067: ...Template SEG Pixel On Waveform V0 V1 V2 V3 Standard Waveform Template Template for even subframeTemplate for odd subframe Low power Waveform Template Figure 43 9 1 2 Bias 1 2 Duty Low Power Waveform...

Page 1068: ...V1 V3 PixelOff V0 V1 V2 V2 V3 V1 V3 Pixel Off V0 V1 V2 V2 V3 V1 V3 PixelOff COM Waveform Template SEG Waveform Template Voltage Level Definition V3 VLCD V2 VLCD 2 3 V1 VLCD 1 3 V0 0 Figure 43 11 1 3...

Page 1069: ...xel Select Waveform V0 V1 V2 V3 SEG Pixel On Waveform V0 V1 V2 V3 SEG Pixel Off Waveform V0 V1 V2 V3 COM Pixel Deselect Waveform V0 V1 V2 V3 Pixel Pixel V0 V1 V2 V2 V3 V1 V3 Pixel On V0 V1 V2 V2 V3 V1...

Page 1070: ...zed per second The optimal frame frequency should be in range from 30Hz up to 100Hz to avoid flickering and ghosting effect The 32KHz oscillator clock CLK_SLCD_OSC is the base clock to define the LCD...

Page 1071: ...3 Hz 32 0x4 5 6 34 1 Hz 16 0x3 4 6 85 3 Hz 16 0x7 8 8 32 Hz 16 0x2 3 8 85 3 Hz 43 6 1 6 LCD Pins Selection Selection of maximum 48 segment common lines from 52 LCD pins There are 52 LCD pins LPx of wh...

Page 1072: ...EG lines enabled is thus the number of LCD pins enabled minus the number of COM lines assigned limited to the maximum SEG lines supported according duty selection COM and SEG lines are always assigned...

Page 1073: ...ect Segments Data Access register ISDATA This register allows to write up to 8 contiguous bits in a single write operation to the display memory SDATA 7 0 segments data value see the figure above SDMA...

Page 1074: ...to the Contrast bits in the Control B register CTRLB CTST see also the according Electrical Characteristics section The contrast value can be written at any time even if SLCD is enabled and running Re...

Page 1075: ...ent and reference voltage start to drift slowly due to parasitic effects A high frequency refresh rate can tolerate higher leakage at cost of higher power consumption User can configure the reference...

Page 1076: ...nfigured to blink all or selected LCD segments Segments will alternate between on and off state at the frequency given by the selected frame counter The blinking feature is configured in the Blink Con...

Page 1077: ...y an internal circular shift register Up to sixteen states are then defined e g to make a running wheel The size of the animation can be configured by writing the number of segments to use to the Size...

Page 1078: ...C CSREN Animation is disabled by writing a 0 to CTRLC CSREN The initial value is shifted each time the selected frame counter overflows The CSRCFG register cannot be written when circular shift regist...

Page 1079: ...2 9 SEGn 3 17 3 10 SEGn 4 18 4 11 SEGn 5 19 5 12 SEGn 6 20 6 13 6 SEGn SEGn 1 SEGn 2 12 18 19 14 20 0 6 1 7 13 2 8 SEGn 3 15 21 3 9 SEGn 4 16 22 4 10 SEGn 5 17 23 5 11 5 SEGn SEGn 1 SEGn 2 10 15 20 16...

Page 1080: ...INDEX also have different coordinate under different DEC configuration Refer to figure below for illustration Figure 43 24 Character Mapping Order COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 21 22 SEGn SE...

Page 1081: ...string in ACM mode Figure 43 25 Examples of Digits Chains Mapped in Display Memory SEGn SEGn 1 SEGn 2 SEGn 3 SEGn 4 SEGn 5 Digit 0 Digit 1 SEGn 6 SEGn 7 SEGn 8 Digit 2 Digit 3 Digit 4 COM0 COM1 COM2...

Page 1082: ...ays characters of a string on a digits chain on the LCD panel The characters string is split in several sub strings which are to be displayed sequentially at a selected frequency frame counter basis I...

Page 1083: ...ntroller to transfer the character string To use this mode character mapping must be configured first see Character Mapping then additional configuration must be done to specify the scrolling display...

Page 1084: ...crolling Examples NDIG 3 String HELLO string length 5 STEPS 3 H E L E L L String HELLO string length 8 STEPS 6 L L O L O O H E L H E L E L L L L O H E L 1 2 3 1 2 3 1 step 1 2 3 4 5 6 1 E L L L L O H...

Page 1085: ...animation frame To make an automated animation of N states with M contiguous segment values in display memory the DMA controller must be configured to transfer N x M 8 words 8 contiguous segments are...

Page 1086: ...source has an interrupt flag associated with it The interrupt flag in the Interrupt Flag Status and Clear INTFLAG register is set when the interrupt condition occurs Each interrupt can be individuall...

Page 1087: ...opped The SLCD can wake up the device from any sleep mode using interrupts 43 6 7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains some registers ne...

Page 1088: ...INTFLAG 7 0 PRST VLCDST VLCDRT FC2O FC1O FC0O 0x10 STATUS 7 0 ABMBUSY ACMBUSY CMWRBUSY VLCDS PRUN VLCDR 0x11 0x13 Reserved 0x14 SYNCBUSY 7 0 CTRLD ENABLE SWRST 0x15 15 8 0x16 23 16 0x17 31 24 0x18 FC0...

Page 1089: ...16 0x3F 31 24 SDATA 31 24 0x40 SDATAH3 7 0 SDATA 7 0 0x41 15 8 SDATA 11 8 0x42 23 16 0x43 31 24 0x44 SDATAL4 7 0 SDATA 7 0 0x45 15 8 SDATA 15 8 0x46 23 16 SDATA 23 16 0x47 31 24 SDATA 31 24 0x48 SDAT...

Page 1090: ...7 0 SIZE 3 0 FCS 1 0 DIR 0x6D 15 8 DATA 7 0 0x6E 23 16 DATA 15 8 0x6F 31 24 0x70 CMCFG 7 0 DEC NSEG 2 0 0x71 0x73 Reserved 0x74 ACMCFG 7 0 NDIG 3 0 NCOM 2 0 0x75 15 8 STEPS 7 0 0x76 23 16 MODE NDROW 5...

Page 1091: ...l Access Controller PAC Optional PAC write protection is denoted by the PAC Write Protection property in each individual register description For details refer to Register Access Protection Some regis...

Page 1092: ...DBY WMOD DUTY 2 0 ENABLE SWRST Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 Bits 26 24 RRF 2 0 Reference Refresh Frequency These bits define the bias reference refresh frequency These bits are not...

Page 1093: ...ternal VLCD generation 1 External VLCD generation Bits 17 16 BIAS 1 0 Bias Setting These bits configure the bias setting These bits are not synchronized Value Name Description 0 STATIC Static 1 HALF 1...

Page 1094: ...te These bits are not synchronized Value Name Description 0x0 STATIC NB_COM 1 0x1 HALF NB_COM 2 0x2 THIRD NB_COM 3 0x3 FOURTH NB_COM 4 0x4 SIXTH NB_COM 6 0x5 EIGHT NB_COM 8 Bit 1 ENABLE Enable Due to...

Page 1095: ...ites in the same write operation will be discarded Due to synchronization there is delay from writing CTRLA SWRST until the reset is complete CTRLA SWRST and SYNCBUSY SWRST will both be cleared when t...

Page 1096: ...d Bits 11 8 LRD 3 0 Low Resistance Enable Duration These bits configure the enable duration of the low resistance network Enable duration LRD 1 x period of CLK_SLCD_OSC These bits are not synchronized...

Page 1097: ...e Value Description 0 Automated character mapping is disabled 1 Automated character mapping is enabled Bit 2 ABMEN Automated Bit Mapping Enable This bit enables the automated bit mapping mode Value De...

Page 1098: ...s enabled Bit 5 FC1EN Frame Counter 1 Enable This bit enables the frame counter 1 Value Description 0 Frame counter 1 is disabled 1 Frame counter 1 is enabled Bit 4 FC0EN Frame Counter 0 Enable This b...

Page 1099: ...Blank LCD This bit allows user to blank all LCD segments transparent Value Description 0 The state of the LCD segments is defined by shadow display memory 1 Blank all LCD segments Atmel SAM L22G L22J...

Page 1100: ...Frame Counter 1 Overflow Event Output Enable This bit enables the Frame Counter 1 Overflow event Value Description 0 Frame Counter 1 Overflow event is disabled and no event is generated 1 Frame Count...

Page 1101: ...VLCD Status Toggle Interrupt Disable Enable bit which disables the VLCD Status Toggle interrupt Value Description 0 The VLCD Status Toggle interrupt is disabled 1 The VLCD Status Toggle interrupt is e...

Page 1102: ...iption 0 The Frame Counter 1 Overflow interrupt is disabled 1 The Frame Counter 1 Overflow interrupt is enabled Bit 0 FC0O Frame Counter 0 Overflow Interrupt Disable Writing a 0 to this bit has no eff...

Page 1103: ...VLCD Status Toggle Interrupt Disable Enable bit which enables the VLCD Status Toggle interrupt Value Description 0 The VLCD Status Toggle interrupt is disabled 1 The VLCD Status Toggle interrupt is en...

Page 1104: ...iption 0 The Frame Counter 1 Overflow interrupt is disabled 1 The Frame Counter 1 Overflow interrupt is enabled Bit 0 FC0O Frame Counter 0 Overflow Interrupt Enable Writing a 0 to this bit has no effe...

Page 1105: ...unter 2 Overflow This flag is set when the frame counter 2 overflows and will generate an interrupt request if the Frame Counter 2 Overflow Enable bit in Interrupt Enable Set register INTENSET FC2O is...

Page 1106: ...Writing a 1 to this bit clears the Frame Counter 0 Overflow interrupt flag Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Complete 07 2016 1106...

Page 1107: ...RBUSY Character mapping write busy This bit indicates the status of character writing function This flag will be set to one after user write CMDATA register and clear automatically when character data...

Page 1108: ...the regulated status of VLCD Value Description 0 VLCD is not well regulated to the target value 1 VLCD is well regulated to the target value Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L...

Page 1109: ...e synchronization of Control D register between the clock domains is started Bit 1 ENABLE Enable This bit is cleared when the synchronization of Enable bit between the clock domains is complete This b...

Page 1110: ...PB Prescaler Bypass This bit enables the bypass of the frame counter 0 prescaler 0 Prescaler is not bypassed 1 Prescaler is bypassed Bits 4 0 OVF 4 0 Frame Counter Overflow Value These bits define the...

Page 1111: ...PB Prescaler Bypass This bit enables the bypass of the frame counter 1 prescaler 0 Prescaler is not bypassed 1 Prescaler is bypassed Bits 4 0 OVF 4 0 Frame Counter Overflow Value These bits define the...

Page 1112: ...PB Prescaler Bypass This bit enables the bypass of the frame counter 2 prescaler 0 Prescaler is not bypassed 1 Prescaler is bypassed Bits 4 0 OVF 4 0 Frame Counter Overflow Value These bits define the...

Page 1113: ...W RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LPEN 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LPEN 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0...

Page 1114: ...W RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LPEN 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LPEN 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0...

Page 1115: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1116: ...W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 11 0 SDATA 11 0 Segments Data Each bit defines the segment value from SEG32 to SEG43 to write in...

Page 1117: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1118: ...W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 11 0 SDATA 11 0 Segments Data Each bit defines the segment value from SEG32 to SEG43 to write in...

Page 1119: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1120: ...W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 11 0 SDATA 11 0 Segments Data Each bit defines the segment value from SEG32 to SEG43 to write in...

Page 1121: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1122: ...W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 11 0 SDATA 11 0 Segments Data Each bit defines the segment value from SEG32 to SEG43 to write in...

Page 1123: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1124: ...W Reset 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 9 0 SDATA 9 0 Segments Data Each bit defines the segment value from SEG32 to SEG41 to write in displ...

Page 1125: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1126: ...W Reset 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 9 0 SDATA 9 0 Segments Data Each bit defines the segment value from SEG32 to SEG41 to write in displ...

Page 1127: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1128: ...t Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 7 0 SDATA 7 0 Segments Data Each bit defines the segment value from SEG32 to SEG39 to write in display memory...

Page 1129: ...12 11 10 9 8 SDATA 15 8 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 31 0 SDATA 31 0 Segments Data Each...

Page 1130: ...t Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 7 0 SDATA 7 0 Segments Data Each bit defines the segment value from SEG32 to SEG39 to write in display memory...

Page 1131: ...te offset in display memory refer to Display Memory Mapping Bits 15 8 SDMASK 7 0 Segments Data Mask Each bit defines the mask for corresponding SDATA bit Value Description 0 The corresponding bit is n...

Page 1132: ...BSS1 7 0 Blink Segment Selection 1 Each bit enables the segment 1 SEG1 connected to COM0 up to COM7 to blink Value Description 0 Segment 1 is not enabled to blink 1 Segment 1 is enabled to blink Bits...

Page 1133: ...MODE Blinking Mode This bit determines if all or a sub set of segments are selected to blink Value Name Description 0 BLINKALL Blink all segments 1 BLINKSEL Blink segments selected by BSS0 BSS1 Atmel...

Page 1134: ...15 0 Circular Shift Register Value These bits defines the initial value of circular shift register Bits 7 4 SIZE 3 0 Circular Shift Register Size These bits defines the size of the circular shift reg...

Page 1135: ...6 5 4 3 2 1 0 DEC NSEG 2 0 Access RW RW RW RW Reset 0 0 0 0 Bit 3 DEC Decrement SEG Line Index Bits 2 0 NSEG 2 0 Number of SEG lines These bits define the number of SEG line per digit NSEG number of...

Page 1136: ...RW RW Reset 0 0 0 0 0 0 0 Bits 31 30 FCS 1 0 Frame Counter Selection These bits select the frame counter to use for automated character mapping Value Name Description 0 FC0 Frame Counter 0 1 FC1 Frame...

Page 1137: ...th NDIG 1 Bits 7 4 NDIG 3 0 Number of Digit These bits define the number of digit used must be greater than 1 Bits 2 0 NCOM 2 0 COM Lines per Row These bits define the number of COM line per row NCOM...

Page 1138: ...E 5 0 Size These bits define the number of DMA writes to ISDATA register to transfer the state of a symbol must be greater than 1 Bits 1 0 FCS 1 0 Frame Counter Selection These bits select the frame c...

Page 1139: ...3 12 11 10 9 8 SDATA 15 8 Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDATA 7 0 Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 23 0 SDATA 23 0 Segments Data Each bit defines th...

Page 1140: ...RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SDMASK 7 0 Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 Bits 23 0 SDMASK 23 0 Segments Data Mask Each bit defines the mask for correspond...

Page 1141: ...7 6 5 4 3 2 1 0 SINDEX 5 0 Access RW RW RW RW RW RW Reset 0 0 0 0 0 0 Bits 10 8 CINDEX 2 0 COM Line Index These bits define COM line index of the character to be updated Bits 5 0 SINDEX 5 0 SEG Line...

Page 1142: ...power high sensitivity environmentally robust capacitive touch buttons sliders wheels and proximity sensing Supports wake up on touch from standby sleep mode Supports mutual capacitance and self capac...

Page 1143: ...Result Y0 Y1 Ym X0 X1 Xn X Line Driver Input Control 10 CX0Y0 CXnYm Figure 44 2 PTC Block Diagram Self Capacitance Compensation Circuit Acquisition Module Gain control ADC Filtering RS IRQ Result Y0 Y...

Page 1144: ...used for analog X lines and Y lines must be connected to external capacitive touch sensor electrodes External components are not required for normal operation However to improve the EMC performance a...

Page 1145: ...clock sources can be selected as the source for the asynchronous GCLK_PTC The clock source is selected by configuring the Generic Clock Selection ID in the Generic Clock Control register For more inf...

Page 1146: ...Link Application Atmel QTouch Library For more information about QTouch Library refer to the Atmel QTouch Library Peripheral Touch Controller User Guide Atmel SAM L22G L22J L22N DATASHEET Atmel 42402...

Page 1147: ...ge with respect to GND and VDD GND 0 6 VDD 0 6V V Tstorage Storage temperature 60 150 C Note Maximum source current is 46mA and maximum sink current is 65mA per cluster A cluster is a group of GPIOs a...

Page 1148: ...ation at supply voltages below specified minimum can cause corruption of NVM areas that are mandatory for correct device behavior Related Links Junction Temperature on page 1183 45 4 Supply Characteri...

Page 1149: ...FDPLL96M 32k Reference clock frequency 32 32 KHz fGCLK_EIC EIC input clock frequency 12 48 MHz fGCLK_FREQM_MSR FREQM Measure 12 48 MHz fGCLK_FREQM_REF FREQM Reference 12 48 MHz fGCLK_USB USB input cl...

Page 1150: ...nput clock frequency fGCLK_CCL CCL input clock frequency fGCLKin External GCLK clock input 45 6 Power Consumption The values in this section are measured values of power consumption under the followin...

Page 1151: ...C 4MHz 1 8V 62 116 3 3V 49 84 PL2 OSC 12MHz 1 8V 79 110 3 3V 52 76 FDPLL 32MHz 1 8V 63 75 3 3V 46 53 ACTIVE FIBO LDO Mode PL0 OSC 8MHz 1 8V 69 111 A MHz 3 3V 71 113 OSC 4MHz 1 8V 78 166 3 3V 81 170 PL...

Page 1152: ...MHz 1 8V 14 31 A MHz 3 3V 12 23 Table 45 8 Current Consumption Standby Mode 1 Mode conditions Regulator Mode VDD Ta Typ Max Units STANDBY No interface running LPEFF Disable 1 8V 25 C 1 8 7 6 A 85 C 43...

Page 1153: ...on OSCULP32K VBAT consumption 1 8V 25 C 0 000 0 00 85 C 0 008 0 009 3 3V 25 C 0 000 0 00 85 C 0 015 0 018 BACKUP powered by VBAT VDDANA VDDIO consumption 1 8V 25 C 0 08 0 09 A 85 C 2 0 2 2 3 3V 25 C...

Page 1154: ...t the set of the IO is done by the first executed instructions after reset For OFF mode the exit of mode is done through reset pin the time is measured between the rising edge of the RESETN signal and...

Page 1155: ...6V IOL max 0 1 VDD 0 2 VDD VOH Output high level voltage VDD 1 6V IOH max 0 8 VDD 0 9 VDD RPULL Pull up Pull down resistance All pins excepted PA24 PA25 20 40 60 k PA24 PA25 1 50 100 150 ILEAK Input...

Page 1156: ...s than normal pins PA12 PA13 PA22 PA23 PA27 PA31 PB30 PB31 4 The following pins are Backups pins and have different properties than normal pins PA00 PA01 PB00 PB01 PB02 PB03 PC00 PC01 5 The following...

Page 1157: ...ristics 45 10 1 1 Buck Converter Table 45 15 Buck converter Electrical Characteristics Symbol Parameter Conditions Typ Units PEFF 2 Power Efficiency IOUT 5mA 86 IOUT 50mA 85 VREGSCAL 1 Voltage scaling...

Page 1158: ...nF 45 10 2 APWS Table 45 19 Automatic Power Switch Characteristics Symbol Parameters Typ Unit CD Decoupling capacitor on VDDIN 4 7 F THUP VDD threshold 1 84 V THDWN 1 75 V THHYS VDD hysteresis 90 mV...

Page 1159: ...1 VDD level Bod setting 39 2 65 2 87 2 95 VBAT level Bod setting 63 3 02 3 14 3 26 VDD level Bod setting 48 3 12 3 20 3 29 VBOD VBOD BOD33 low threshold Level VBAT level Bod setting 15 1 60 1 66 1 72...

Page 1160: ...ation 45 10 5 Analog to Digital ADC Characteristics Table 45 23 Operating Conditions Symbol Parameters Conditions Min Typ Max Unit RES Resolution 12 bits RS Sampling rate 10 1000 kSPS fs Sampling cloc...

Page 1161: ...6000 kHz TS Sampling time 250 SAMPLEN 1 fadc 25000 ns Conversion range Differential mode VREF VREF V Single Ended mode 0 VREF VREF Reference input REFCOMP 1 1 VDDANA 0 6 V REFCOMP 0 VDDANA VDDANA VIN...

Page 1162: ...FBUF 111 BIASREFCOMP 111 VDDANA 1 6V VREF 1 0V 175 231 A VDDANA 3 0V VREF 2 0V 300 374 VDDANA 3 6V VREF 3 0V 356 438 fs 10 kSPS Reference buffer disabled BIASREFBUF 111 BIASREFCOMP 111 VDDANA VREF 1 6...

Page 1163: ...IASREFCOMP 111 VDDANA 1 6V VREF 1 0V 109 157 A VDDANA 3 0V VREF 2 0V 138 211 VDDANA 3 6V VREF 3 0V 148 228 Note 1 These are based on characterization Table 45 25 Differential Mode 1 Symbol Parameters...

Page 1164: ...tion ratio 60 65 66 SNR Signal to Noise ratio 61 66 67 THD Total Harmonic Distortion 74 73 67 Noise RMS External Reference voltage 1 0 2 5 mV Note 1 These are based on characterization Table 45 26 Sin...

Page 1165: ...1 VDDANA 1 6 6 3 13 SFDR Spurious Free Dynamic Range Fs 1MHz Fin 13 kHz Full range Input signal VDDANA 3 0V Vref 2 0V 65 71 78 dB SINAD Signal to Noise and Distortion ratio 53 59 61 SNR Signal to Nois...

Page 1166: ...7 90 116 COMPCTRLn HYST 0x3 49 105 131 Tpd 2 Propagation Delay Vcm Vddana 2 Vin 100mV overdrive from Vcm COMPCTRLn SPEED 0x0 4 0 12 3 s COMPCTRLn SPEED 0x1 0 97 2 59 COMPCTRLn SPEED 0x2 0 56 1 41 COMP...

Page 1167: ...67 1 0 1 017 V nom 1 1V VDDANA 3 0V T 25 C 1 069 1 1 1 120 V nom 1 2V VDDANA 3 0V T 25 C 1 167 1 2 1 227 V nom 1 25V VDDANA 3 0V T 25 C 1 214 1 3 1 280 V nom 2 0V VDDANA 3 0V T 25 C 1 935 2 0 2 032 V...

Page 1168: ...RetNVM25k Retention after up to 25k Average ambient 55 C 10 50 Years RetNVM2 5k Retention after up to 2 5k Average ambient 55 C 20 100 Years RetNVM100 Retention after up to 100 Average ambient 55 C 25...

Page 1169: ...ion test limits or characterization 45 12 1 2 Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT F...

Page 1170: ...XOSC GAIN 1 6 8k 19 5k F 8MHz CL 20pF XOSC GAIN 2 5 6k 13k F 16MHz CL 20 pF XOSC GAIN 3 6 8k 14 5k F 32MHz CL 20pF XOSC GAIN 4 5 3K 9 6k Note 1 These values are based on characterization Table 45 37 P...

Page 1171: ...ator when a crystal is connected between XIN32 and XOUT32 Figure 45 3 Oscillator Connection CSHUNT LM RM CM CSTRAY CLEXT CLEXT Xin32 Crystal Xout32 The user must choose a crystal oscillator where the...

Page 1172: ...ption VDD 3 3V Max 85 C Typ 25 C 311 723 nA Note These are based on characterization 45 12 3 OSCULP32K Table 45 41 Ultra Low Power Internal 32KHz RC Oscillator Electrical Characteristics Symbol Parame...

Page 1173: ...er Conditions Ta Min Typ Max Units IDD Current consumption FOUT 4MHz VDD 3 3V Max 85 C Typ 25 C 64 96 A FOUT 8MHz VDD 3 3V 91 122 FOUT 12MHz VDD 3 3V 114 144 FOUT 16MHz VDD 3 3V 141 169 Note These are...

Page 1174: ...FLLMUL FSTEP 10 200 700 s Note 1 These are based on characterization 2 To ensure that the device stays within the maximum allowed clock frequency any reference clock for DFLL in close loop must be wit...

Page 1175: ...are based on simulation They are not covered by production test limits or characterization 2 These are based on characterization Table 45 48 Power Consumption 1 Symbol Parameter Conditions Ta Min Typ...

Page 1176: ...ency source is high 1 MHz Thus FDPLL and external OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB wakeup time See TDRSMDN in USB specification 45 14 SLCD Character...

Page 1177: ...justment CTST 0xF Iload 10 A 3 32 3 44 3 55 Iload 20 A 3 17 3 36 3 53 VDD 2V Contrast Adjustment CTST 0xF Iload 10 A 3 32 3 48 3 71 Iload 20 A 3 28 3 45 3 69 CVLCD External VLCD capacitor 1 F Fframe L...

Page 1178: ...3 6V 1 63 6 61 VDD 2 4V 2 28 16 86 Nb COM 1 Nb SEG 44 Static Bias VDD 3 6V 1 20 5 97 VDD 2 4V 1 25 15 24 External VLCD generation VLCD 3 0V Nb COM 8 Nb SEG 40 1 4 Bias VDD 3 6V 1 03 5 76 VDD 2 4V 1 25...

Page 1179: ...8 22 VDD 2 4V 3 84 17 64 Nb COM 1 Nb SEG 44 Static Bias VDD 3 6V 1 78 6 86 VDD 2 4V 1 99 15 23 External VLCD generation VLCD 3 0V Nb COM 8 Nb SEG 40 1 4 Bias VDD 3 6V Max 85 C Typ 25 C 1 09 5 96 VDD 2...

Page 1180: ...7 2 91 0x8 2 98 0x9 3 04 0xA 3 11 0xB 3 18 0xC 3 25 0xD 3 31 0xE 3 38 0xF 3 45 45 15 External Reset Pin Table 45 52 External Reset Characteristics 1 Symbol Parameter Conditions Min Typ Max Units tEXT...

Page 1181: ...l BOD33 is disabled Figure 46 1 Power Consumption over Temperature in STANDBY Sleep Mode with RTC 40 20 0 20 40 60 80 0 10 20 30 40 Temperature in C I CC in A VDD 3 3V VDD 1 8V Power Consumption in BA...

Page 1182: ...er Temperature in Standby Sleep Mode with RTC 40 20 0 20 40 60 80 0 0 5 1 1 5 2 2 5 3 Temperature in C I CC in A VBAT 3 3V VBAT 1 8V Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_...

Page 1183: ...Package thermal resistance Junction to ambient C W see Thermal Resistance Data JC Package thermal resistance Junction to case thermal resistance C W see Thermal Resistance Data HEATSINK Thermal resist...

Page 1184: ...m Weight 520 mg Table 47 3 Package Characteristics Moisture Sensitivity Level MSL3 Table 47 4 Package Reference JEDEC Drawing Reference MS 026 variant AED JESD97 Classification e3 Atmel SAM L22G L22J...

Page 1185: ...Table 47 5 Device and Package Maximum Weight 300 mg Table 47 6 Package Characteristics Moisture Sensitivity Level MSL3 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_Com...

Page 1186: ...g Reference MS 026 JESD97 Classification E3 47 2 3 64 pin QFN Note The exposed die attach pad is not connected electrically inside the device Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L...

Page 1187: ...Table 47 9 Package Charateristics Moisture Sensitivity Level MSL3 Table 47 10 Package Reference JEDEC Drawing Reference MO 220 JESD97 Classification E3 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E...

Page 1188: ...Table 47 11 Device and Package Maximum Weight 8 45 mg Table 47 12 Package Characteristics Moisture Sensitivity Level MSL1 Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datasheet_C...

Page 1189: ...ce JEDEC Drawing Reference N A JESD97 Classification E1 47 2 5 48 pin TQFP Table 47 14 Device and Package Maximum Weight 140 mg Atmel SAM L22G L22J L22N DATASHEET Atmel 42402E SAM L22G L22J L22N_Datas...

Page 1190: ...7 16 Package Reference JEDEC Drawing Reference MS 026 JESD97 Classification E3 47 2 6 48 pin QFN Note The exposed die attach pad is not connected electrically inside the device Atmel SAM L22G L22J L22...

Page 1191: ...file from J STD 20 Table 47 20 Profile Feature Green Package Average Ramp up Rate 217 C to peak 3 C s max Preheat Temperature 175 C 25 C 150 200 C Time Maintained Above 217 C 60 150s Time within 5 C o...

Page 1192: ...in order to avoid that it reaches supply pins I O pins and crystals 48 2 Power Supply The SAM L22 supports a single or dual power supply from 1 62V to 3 63V The same voltage must be applied to both VD...

Page 1193: ...E GND GNDANA 100nF 1 F Main Supply VDDOUT 10 F VLCD 1 F Figure 48 2 Power Supply Connection for Linear Mode Only VDDIO VDDANA SAM L22 VBAT PB03 100nF 100nF 10 F Close to device for every pin VDDCORE G...

Page 1194: ...g filtering capacitors 100nF 1 2 and 10 F 1 Ferrite bead 4 prevents the VDD noise interfering with VDDANA Analog supply voltage VVDDOUT Switching regulator mode 10 H inductor with saturation current a...

Page 1195: ...n The bead should provide enough impedance e g 50 at 20MHz and 220 at 100MHz to separate the digital and analog power domains Make sure to select a ferrite bead designed for filtering applications wit...

Page 1196: ...vice for every pin Table 48 2 External Analog Reference Connections Signal Name Recommended Pin Connection Description VREFA VREFB 1 0V to VDDANA 0 6V for ADC Decoupling capacitors 100nF 1 2 and 4 7 F...

Page 1197: ...al to add any external pull up resistor Figure 48 6 External Reset Circuit Schematic GND RESET 100nF 10k VDD 330 A pull up resistor makes sure that the reset does not go low and unintentionally causin...

Page 1198: ...unused pins in order to lower the power consumption 48 6 Clocks and Crystal Oscillators The SAM L22 can be run from internal or external clock sources or a mix of internal and external sources An exam...

Page 1199: ...ng crystals load capacitance and the crystal s Equivalent Series Resistance ESR must be taken into consideration Both values are specified by the crystal vendor SAM L22 oscillator is optimized for ver...

Page 1200: ...possible For neighboring pin details refer to the Oscillator Pinout section Related Links Oscillator Pinout on page 29 Oscillators Characteristics on page 1169 48 6 4 Calculating the Correct Crystal...

Page 1201: ...ogramming and or debugging the SAM L22 the device should be connected using the Serial Wire Debug SWD interface Currently the SWD interface is supported by several Atmel and third party programmers an...

Page 1202: ...n VDD VTref GND GND NC NC NC NC SWDCLK SWDIO RESET RESET SWDIO SWCLK GND Table 48 8 Cortex Debug Connector 10 pin Header Signal Name Description SWDCLK Serial wire clock pin SWDIO Serial wire bidirect...

Page 1203: ...ure 48 14 10 pin JTAGICE3 Compatible Serial Wire Debug Interface 1 10 pin JTAGICE3 Compatible Serial Wire Debug Header VDD SWDCLK NC SWDIO NC NC GND VTG RESET NC NC SWCLK RESET SWDIO GND Table 48 9 10...

Page 1204: ...Target voltage sense should be connected to the device VDD GND Ground GND These pins are reserved for firmware extension purposes They can be left unconnected or connected to GND in normal debug envi...

Page 1205: ...educe the potential discharge path and reduce discharge propagation within the entire system The USB FS cable includes a dedicated shield wire that should be connected to the board with caution Specia...

Page 1206: ...ics Note The electrical characteristics differ based on the type of the IO pin such as standard normal I O pins high sink current I O pins LCD pins in I O configuration etc Related Links I O Multiplex...

Page 1207: ...nable the main voltage regulator in standby mode SUPC VREG RUNSTDBY 1 and set the Standby in PL0 bit to one SUPC VREG STDBYPL0 1 49 1 3 TC 1 When clearing STATUS xxBUFV flag SYNCBUSY is released befor...

Page 1208: ...detection The result is that the DMA may trigger frequently from the same mismatch compared to the interrupt which will only trigger once Errata reference 14692 Fix Workaround If no other tamper conf...

Page 1209: ...abled during sleep it could still continue to operate resulting in over consumption 50uA in standby mode Errata reference 14827 Fix Workaround Disable the TRNG before entering standby mode 49 1 6 Devi...

Page 1210: ...ches the maximum or minimum COARSE or FINE calibration values during the locking sequence an out of bounds interrupt will be generated These interrupts will be generated even if the final calibration...

Page 1211: ...All capture will be done as expected 49 1 11 DMAC 1 A write from DMAC to a register in a module to disable a trigger from the module to DMAC does not work in standby mode For example DAC SLCD SERCOM i...

Page 1212: ...US CHBUSYn bit before this information is fully propagated in the EVSYS one GCLK_EVSYS_CHANNEL_n clock cycle later As a consequence any generator event occurring on that channel before that extra GCLK...

Page 1213: ...e tamper interrupt INTEN TAMPER 1 To disable the RTC first disable the Tamper interrupts before disabling the RTC Disable Tamper interrupts INTEN TAMPER 0 Disable the RTC CTRLA ENABLE 0 2 Issue a CPU...

Page 1214: ...be configured for active layer with DMA 2 Tamper input 4 can be configured with DMA for any mode other than active layer 3 If Tamper input 4 is to be used in active layer do not enable the DMA to prev...

Page 1215: ...LB SFDE 1 if there is a parity error receive start INTFLAG RXS can be erroneously set This is because the transmitted parity low is also seen by the receiver and looks like a start of frame Errata ref...

Page 1216: ...er 16 bits This will write upper 16 bits also but does not impact the application 2 When the EIC is configured to generate an interrupt on a low level or rising edge or both edges CONFIGn SENSEx with...

Page 1217: ...a software event 2 Using synchronous spurious overrun can appear with generic clock for the channel always on Errata reference 14532 Fix Workaround Request the generic clock on demand by setting the C...

Page 1218: ...0 2 Memory Size and Type Table 50 2 Memory Size and Bit Rate Symbol Description KB kbyte kilobyte 210 1024 MB Mbyte megabyte 220 1024 1024 GB Gbyte gigabyte 230 1024 1024 1024 b bit binary 0 or 1 B by...

Page 1219: ...o when read PERIPHERALi If several instances of a peripheral exist the peripheral name is followed by a number to indicate the number of the instance in the range 0 n PERIPHERAL0 denotes one specific...

Page 1220: ...Lock Bit BOD Brown out detector CAL Calibration CC Compare Capture CCL Configurable Custom Logic CLK Clock CRC Cyclic Redundancy Check CTRL Control DAP Debug Access Port DFLL Digital Frequency Locked...

Page 1221: ...PTC Peripheral Touch Controller PWM Pulse Width Modulation RAM Random Access Memory REF Reference RTC Real Time Counter RX Receiver Receive SERCOM Serial Communication Interface SLCD Segmented Liquid...

Page 1222: ...ransmitter USB Universal Serial Bus VDD Common voltage to be applied to VDDIO and VDDANA VDDIO Digital supply voltage VDDANA Analog supply voltage VREF Voltage reference WDT Watchdog Timer XOSC Crysta...

Page 1223: ...cteristics Absolute Maximum Ratings Vpin increased Section Injection Current added Schematic Checklist Editorial updates 52 2 Rev D 05 2016 Section Changes Device WLCSP49 Package added Device SUPC Sup...

Page 1224: ...r Counter for Control Applications In CAPTMIN mode value 0 can be captured only in down counting mode In Counter Operation Section Stop Command and Event Action split into Stop Command and Pause Event...

Page 1225: ...r FCloseOUT updated DPLL Characteristics Period Jitter values added for different conditions OSC16M Characteristics Table Multi RC Oscillator Electrical Characteristics symbols TempCo SupplyCo replace...

Page 1226: ...added to Asynchronous Operational Range SLCD Segment Liquid Crystal Display Controller Editorial updates PTC Peripheral Touch Controller Editorial updates Electrical Characteristics General VDDIO and...

Page 1227: ...s added Schematic Checklist 1k pull up resistor for SWCLK pin recommended Editorial updates Errata Changed Erratum 15010 moved from Device to RTC category Errata 14417 14431 14819 14827 15010 editoria...

Page 1228: ...eference clock drift will make run the compensation out of bounds voltage and temperature swings are compensated for USB Clock recovery mode enabled by writing to DFLLCTRL USBCRM and DFLLCTRL MODE STA...

Page 1229: ...temperature sensor available Signal Description Updated signal name from ADC to AIN AREFA B naming updated to VREFA B Editorial updates SLCD Segment Liquid Crystal Display Controller Contrast VLCD val...

Page 1230: ...ON ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy...

Page 1231: ...Lifecycle Information Atmel ATSAML22G18A AUT ATSAML22G16A AUT ATSAML22N17A AUT ATSAML22N16A AUT ATSAML22J16A MUT ATSAML22J17A AUT ATSAML22J18A AUT ATSAML22G16A MUT ATSAML22J18A MUT ATSAML22J17A MUT AT...

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