74
6174B–ATARM–07-Nov-05
AT91FR40162S Preliminary
13. AIC: Advanced Interrupt Controller
The AT91FR40162S has an 8-level priority, individually maskable, vectored interrupt controller.
This feature substantially reduces the software and real-time overhead in handling internal and
external interrupts.
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard
interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be
asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the
interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to
IRQ2.
The 8-level priority encoder allows the customer to define the priority between the different NIRQ
interrupt sources.
Internal sources are programmed to be level sensitive or edge triggered. External sources can
be programmed to be positive or negative edge triggered or high- or low-level sensitive.
The interrupt sources are listed in
and the AIC programmable registers in
.
13.1
Block Diagram
Figure 13-1. Advanced Interrupt Controller Block Diagram
Note:
After a hardware reset, the AIC pins are controlled by the PIO Controller. They must be configured to be controlled by the
peripheral before being used.
Control
Logic
Memorization
Memorization
Priority
Controller
NIRQ
Manager
NFIQ
Manager
FIQ Source
Advanced Peripheral
Bus (APB)
Internal Interrupt Sources
External Interrupt Sources
ARM7TDMI
Core
NFIQ
NIRQ
