AT91EB40A Evaluation Board User Guide
4-3
2635C–ATARM–13-May-05
4.6.2
JTAG Interface
An ARM-standard 20-pin box header (P5) is provided to enable connection of an ICE to
the JTAG inputs on the AT91. This allows code to be debugged on the board without
using system resources, such as memory and serial ports.
4.7
Layout Drawing
The layout diagram (Figure 6-1 on page 6-2 in Section 6, “Appendix B – Schematics”)
shows an approximate floorplan for the board. This has been designed to give the low-
est board area, while still providing access to all test points, jumpers and switches on
the board.
The board is provided with four mounting holes, one at each corner, into which feet are
attached. The board has two signal layers and two power planes.
Summary of Contents for AT91EB40A
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