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6320B–ATARM–05-Nov-07
Application Note
Figure 4-4.
ECC Calculation During Page Write Sequence with Random Write Spare Area
4.3.2
Page Read Sequence
The ECC controller is automatically reset as soon as the first read command (00h) is performed
to the NAND Flash or the SmartMedia device.
The ECC calculation starts only once the required address cycles (the number of address cycles
depends on the device type) and the second read command (30h) is performed to the NAND
Flash or the SmartMedia device.
The ECC is refreshed at each read access of the page until the last byte or half word of the main
area is read.
Once the whole main area has been read, the next four data read accesses must be performed
to the spare area locations where ECC has been previously stored by the software application. If
this condition is not respected, the ECC controller will not be able to check data integrity.
Since Parity ECC and NParity has been previously stored in locations of the spare area which
are not contiguous to the main area, it is useful to perform a random read command sequence
before performing the four ECC data accesses.
Please note that apart from data accesses (ALE = CLE = 0), the ECC controller ignores any
other command which is performed to the NAND Flash or the SmartMedia device.
The ECC controller performs error detection automatically by applying an XOR operation
between the calculated ECC and the ECC stored in the spare area.
In order to determine if an error has been detected by the ECC controller, the software applica-
tion must check the MULERR, ECCERR and RECERR fields in the ECC Status Register
(ECC_SR).
4.3.2.1
No Error
MULERR, ECCERR and RECERR fields in the ECC Status Register (ECC_SR) are all cleared.
XOR between the calculated ECC computation and the ECC code stored in the spare area is
equal to 0.
4.3.2.2
Recoverable Error
Only the RECERR field in the ECC Status register (ECC_SR) is set. The corrupted word offset
in the read page is defined by the WORDADDR field in the ECC Parity Register (ECC_PR). The
corrupted bit position in the concerned word is defined in the BITADDR field in the ECC Parity
Register (ECC_PR).
Write
Command 2
Spare Area ECC locations
Write Accesses
10h
ECC
ECC
ECC
ECC
I/Ox
Address
Write
Command 1
Address cycles
ECC Controller
Reset
Main Area Write Accesses
Accesses Allowing ECC calculation
Start of ECC
Calculation
ECC Result
Ready in and Locked
Accesses Ignored by the ECC Controller
for ECC calculation
80h
1st
2nd
...
n th
Main Area Size
Address
Random
Write
Command
Column Address
cycles
85h
