4-58
AT90S8414
Preliminary
Bit 3 - ACIE : Analog Comparator Interrupt Enable:
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is
activated. When cleared (zero), the interrupt is disabled. For details on the comparator, refer to Page 4-57.
Bit 2 - ACIC : Analog Comparator Input Capture enable:
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator.
The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator
utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no
connection between the analog comparator and the Input Capture function is given. To make the comparator trigger the
Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
Bits 1,0 - ACIS1, ACIS0 : Analog Comparator Interrupt Mode Select:
These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are
shown in Table 15.
Table 15: ACIS1/ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
0
0
Comparator Interrupt on Output Toggle
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge
1
1
Comparator Interrupt on Rising Output Edge
Note: When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be disabled by clearing its Interrupt
Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.
I/O-Ports
Port A
PORT A is an 8-bit bi-directional I/O port.
Three data memory address locations are allocated for the Port A, one each for the Data Register - PORTA ($1B), Data
Direction Register - DDRA ($1A) and the Port A Input Pins - PINA ($19). The Port A Input Pins address is read only,
while the Data Register and the Data Direction Register are read/write.
All port pins have individually selectable pullups. The PORT A output buffers can sink 20mA and thus drive LED
displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current (IIL) if
the internal pullups are activated.
The PORT A pins have alternate functions related to the optional external data SRAM. PORT A can be configured to be
the multiplexed low-order address/data bus during accesses to the external data memory. In this mode, PORT A has
internal pullups.
PORT A also receives the code bytes during Flash programming and outputs the code bytes during program verification.
External pullups are required during program verification.
When PORT A is set to the alternate function by the SRE - External SRAM Enable - bit in the MCUCR - MCU Control
Register, the alternate settings override the data direction register.
