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AT90S8414
Preliminary
The Serial Peripheral Interface - SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8414 and
peripheral devices or between several AT90S8414 devices. The AT90S8414 SPI features include the following:
·
Full-Duplex, 3-Wire Synchronous Data Transfer
·
Master or Slave Operation
·
5 Mbit/s Bit Frequency (max.)
·
LSB First or MSB First Data Transfer
·
Four Programmable Bit Rates
·
End of Transmission Interrupt Flag
·
Write Collision Flag Protection
·
Wakeup from Idle Mode (Slave Mode Only)
Figure 38: SPI Block Diagram
The interconnection between master and slave CPUs with SPI is shown in Figure 39. The PB7(SCK) pin is the clock
output in the master mode and is the clock input in the slave mode. Writing to the SPI data register of the master CPU
starts the SPI clock generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the
slave CPU. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI
interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is requested. The Slave Select input, PB4( SS ), is set
