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AT90S8414
Preliminary
These bits are reserved bits in the AT90S8414 and always read zero.
THE TIMER COUNTER 0 - TCNT0
Bit
7
6
5
4
3
2
1
0
$32
MSB
LSB
TCNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock
source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.
THE OUTPUT COMPARE REGISTER 0 - OCR0
Bit
7
6
5
4
3
2
1
0
$31
MSB
LSB
OCR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
The Output Compare Register 0 is the source register for the Timer/Counter0 compare match functions.
The 16-Bit Timer/Counter1
Figure 33 shows the block diagram for Timer/Counter1.