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Atmel AT90S8414, Manual

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Atmel AT90S8414 Manual Download Page 25

AT90S8414

Preliminary

4-25

Address

Labels

Code

Comments

$000

rjmp

RESET

; Reset Handle

$001

rjmp

EXT_INT0

; IRQ0 Handle

$002

rjmp

EXT_INT1

; IRQ1 Handle

$003

rjmp

TIM1_CAPT

; Timer1 capture Handle

$004

rjmp

TIM1_COMPA

; Timer1 compareA Handle

$005

rjmp

TIM1_COMPB

; Timer1 compareB Handle

$006

rjmp

TIM1_OVF

; Timer1 overflow Handle

$007

rjmp

TIM0_COMP

; Timer0 compare Handle

$008

rjmp

TIM0_OVF

; Timer0 overflow Handle

$009

rjmp

SPI_HANDLE

; SPI TX Handle

$00a

rjmp

UART_RXC

; UART RX Complete Handle

$00b

rjmp

UART_DRE

; UDR Empty Handle

$00c

rjmp

UART_TXC

; UART TX Complete Handle

$00d

rjmp

ANA_COMP

; Analog Comparator Handle

;
$00e

MAIN:

<instr>  xxx

; Main program start

  …

 …

   

   …

    …

RESET SOURCES

The AT90S2312 has three sources of reset:

· 

Power-On Reset. The MCU is reset when a supply voltage is applied to the VCC and GND pins.

· 

External Reset. The MCU is reset when a low level is present on the  RESET  pin for more than two XTAL cycles

· 

Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The
instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the
program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 25 shows the reset logic. Table 3 defines the timing and electrical
parameters of the reset circuitry.

Figure 25: Reset Logic

Table 3: Reset Characteristics

Symbol

Parameter

Min

Typ

Max

Units

V

POT

Power-On Reset Threshold Voltage

1.8

2

2.2

V

V

RST

RESET Pin Threshold Voltage

VCC/2

V

T

POR

Power-On Reset Period

2

3

4

ms

T

TOUT

Reset Delay Time-Out Period

11

16

21

ms

Summary of Contents for AT90S8414

Page 1: ...ROGRAM ADDRESS JMP AND CALL 4 18 INDIRECT PROGRAM ADDRESSING IJMP AND ICALL 4 18 RELATIVE PROGRAM ADDRESSING RJMP AND RCALL 4 19 The EEPROM Data Memory 4 19 Memory Access Times and Instruction Executi...

Page 2: ...ONTROL REGISTER UCR 4 54 THE BAUD RATE GENERATOR 4 55 THE UART BAUD RATE REGISTER UBRR 4 56 THE ANALOG COMPARATOR 4 57 THE ANALOG COMPARATOR CONTROL AND STATUS REGISTER ACSR 4 57 I O PORTS 4 58 Port A...

Page 3: ...ING ALGORITHM 4 75 Programming Characteristics 4 79 ABSOLUTE MAXIMUM RATINGS 4 79 D C CHARACTERISTICS 4 80 A C CHARACTERISTICS 4 81 EXTERNAL DATA MEMORY READ CYCLE 4 81 EXTERNAL MEMORY WRITE CYCLE 4 8...

Page 4: ...4 4 AT90S8414 Preliminary...

Page 5: ...ce 100 000 Write Erase Cycles 256 bytes Internal RAM 32 x 8 General Purpose Working Registers 32 Programmable I O Lines Programmable Serial UART SPI Serial Interface VCC Min 2 7 V Fully Static Operati...

Page 6: ...4 6 AT90S8414 Preliminary Block Diagram Figure 1 The AT90S8414 Block Diagram...

Page 7: ...56 bytes SRAM 32 general purpose I O lines 32 general purpose working registers flexible timer counters with compare modes internal and external interrupts a programmable serial UART programmable Watc...

Page 8: ...ternal pullups The Port C output buffers can sink 20 mA As inputs Port C pins that are externally pulled low will source current IIL if the pullups are activated Port C also serves as Address output w...

Page 9: ...parallel programming mode this pin is pulsed to write data Crystal Oscillator XTAL1 and XTAL2 are input and output respectively of an inverting amplifier which can be configured for use as an on chip...

Page 10: ...uted Two operands are output from the register file the operation is executed and the result is stored back in the register file in one clock cycle Six of the 32 registers can be used as three 16 bits...

Page 11: ...the return address program counter PC is stored on the stack The stack is effectively allocated in the general data SRAM and consequently the stack size is only limited by the total SRAM size and the...

Page 12: ...ic and logic instructions SBCI SUBI CPI ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data These instructions apply to the second half of the regis...

Page 13: ...connection with all the 32 general purpose working registers Within a single clock cycle ALU operations between registers in the register file are executed The ALU operations are divided into three m...

Page 14: ...SRAM locations the external data SRAM is accessed using the same instructions as for the internal data SRAM access When the internal data SRAM is accessed the read and write strobe pins RD and WR are...

Page 15: ...ficient addressing modes for access to the program memory Flash and data memory SRAM This section describes the different addressing modes supported by the AVR architecture In the figures OP means the...

Page 16: ...SRAM DIRECT Figure 11 Direct SRAM Addressing A 16 bit SRAM or Register Address is contained in the 16 LSBs of a two word instruction Rd Rr specify the destination or source register SRAM DIRECT WITH...

Page 17: ...ct Addressing With Pre Decrement The X Y or the Z register is decremented before the operation Operand address is the decremented contents of the X Y or the Z register SRAM REGISTER INDIRECT WITH POST...

Page 18: ...ect low byte if cleared LSB 0 or high byte if set LSB 1 DIRECT PROGRAM ADDRESS JMP AND CALL Figure 17 Direct Program Memory Addressing Program execution continues at the address immediate in the instr...

Page 19: ...Instruction Execution Timing This section describes the general access timing concepts for instruction execution and internal memory access The AVR CPU is driven by the System Clock directly generate...

Page 20: ...Register Operands Fetch ALU Operation Execute Store Result in Register Figure 21 Single Cycle ALU Operation The internal data SRAM access is performed in two System Clock cycles as described in Figure...

Page 21: ...rnal Data SRAM Memory Cycles without Wait State The external data SRAM memory access cycle with the Wait State bit enabled Wait State active is shown in Figure 24 System Clock T1 T2 T3 T4 External Add...

Page 22: ...t Capture Register High Byte 24 ICR1L T C 1 Input Capture Register Low Byte 21 WDTCR Watchdog Timer Control Register 1E EEAR EEPROM Address Register 1D EEDR EEPROM Data Register 1C EECR EEPROM Control...

Page 23: ...uctions BLD Bit LoaD and BST Bit STore use the T bit as source and destination for the operated bit A bit from a register in the register file can be copied into T by the BST instruction and a bit in...

Page 24: ...t interrupt sources These interrupts and the separate reset vector each have a separate program vector in the program memory space All interrupts are assigned individual enable bits which must be set...

Page 25: ...ns External Reset The MCU is reset when a low level is present on the RESET pin for more than two XTAL cycles Watchdog Reset The MCU is reset when the Watchdog timer period expires and the Watchdog is...

Page 26: ...igure 26 and Figure 27 The total reset period is the Power On Reset period tPOR the Delay Time out period tTOUT As the RESET pin is pulled high by an on chip resistor the pin can be left unconnected i...

Page 27: ...ches the Reset Threshold Voltage VRST on its positive edge the delay timer starts the MCU after the Time out period tTOUT has expired Figure 29 External Reset During Operation WATCHDOG RESET When the...

Page 28: ...trol1 bits 1 0 ISC11 and ISC10 in the MCU general Control Register MCUCR defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed If the INT1 pin f...

Page 29: ...he CompareB Flag in Timer Counter1 is set one in the Timer Counter Interrupt Flag Register TIFR Bit 4 Res Reserved bit This bit is a reserved bit in the AT90S8414 and always reads zero Bit 3 TICIE1 Ti...

Page 30: ...eserved bit in the AT90S8414 and always reads zero Bit 3 ICF1 Input Capture Flag 1 The ICF1 bit is set one to flag an input capture event indicating that the Timer Counter1 value has been transferred...

Page 31: ...g routines requiring a storage of the SREG this must be performed by user software For Interrupts triggered by events that can remain static E g the Output Compare register0 matching the value of Time...

Page 32: ...ding interrupt mask in the GIMSK is set The level and edges on the external INT1 pin that activate the interrupt are defined in the following table Table 4 Interrupt 1 Sense Control ISC11 ISC10 Descri...

Page 33: ...low interrupt and watchdog reset If wakeup from the Analog Comparator interrupt is not required the analog comparator can be powered down by setting the ACD bit in the Analog Comparator Control and St...

Page 34: ...al is synchronized with the oscillator frequency of the CPU To assure proper sampling of the external clock the minimum time for the external clock being low and high must be at least one internal CPU...

Page 35: ...he COM01 COM00 bits Output Compare Interrupt 0 must be disabled by clearing its Interrupt Enable bit in the TIMSK Register Otherwise an interrupt can occur when the bits are changed Bit 3 CTC0 Clear T...

Page 36: ...nd write access If the Timer Counter0 is written and a clock source is present the Timer Counter0 continues counting in the clock cycle following the write operation THE OUTPUT COMPARE REGISTER 0 OCR0...

Page 37: ...he CPU To assure proper sampling of the external clock the minimum time for the external clock being low and high must be at least one internal CPU clock period The external clock signal is sampled on...

Page 38: ...ctual capture event settings are defined by the Timer Counter1 Control Register TCCR1B In addition the Analog Comparator can be set to trigger the Input Capture Refer to the paragraph The Analog Compa...

Page 39: ...OC1X output line to zero 1 1 Set the OC1X output line to one Notes X A or B In PWM mode these bits have a different function Refer to Table 10 for a detailed description When changing the COM1X1 COM1...

Page 40: ...1 0 External Pin T1 rising edge 1 1 1 External Pin T1 falling edge The Stop condition provides a Timer Enable Disable function The CK down divided modes are scaled directly from the CK oscillator cloc...

Page 41: ...lue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER COUNTER1 OUTPUT COMPARE REGISTER OCR1BH AND OCR1BL Bit 15 14 13 12 11 10 9 8 29 MSB OCR1BH 28 LSB OCR1BL 7 6 5 4 3 2 1 0 Read Write R W R W R W R W R W R W R...

Page 42: ...hen the PWM mode is selected Timer Counter1 and the Output Compare Register1A OCR1A and the Output Compare Register1B OCR1B form a dual 10 bit free running glitch free and phase correct PWM with outpu...

Page 43: ...Overflow Interrupt1 and global interrupts are enabled This does also apply to the Timer Output Compare1 flags and interrupts The PWM output frequency is given by f f 2046 PWM TC1 where fTC1 is the Tim...

Page 44: ...is cleared zero the Watchdog Timer function is disabled Bits 2 0 WDP2 WDP1 WDP0 Watch Dog Timer Prescaler 2 1 and 0 The WDP2 WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdo...

Page 45: ...r For the EEPROM read operation the EEDR contains the data read out from the EEPROM at the address given by EEAR THE EEPROM CONTROL REGISTER EECR Bit 7 6 5 4 3 2 1 0 1C EEWE EERE EECR Read Write R R R...

Page 46: ...ite Collision Flag Protection Wakeup from Idle Mode Slave Mode Only Figure 38 SPI Block Diagram The interconnection between master and slave CPUs with SPI is shown in Figure 39 The PB7 SCK pin is the...

Page 47: ...haracters to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed When receiving data however a received character must be read from the SPI Data Regist...

Page 48: ...0 Bit 7 SPIE SPI Interrupt Enable This bit causes setting of the SPIF bit in the SPSR register to execute the SPI interrupt provided that global interrupts are enabled Bit 6 SPE SPI Enable When the SP...

Page 49: ...ISTER SPSR Bit 7 6 5 4 3 2 1 0 0E SPIF WCOL SPSR Read Write R R R R R R R R Initial value 0 0 0 0 0 0 0 0 Bit 7 SPIF SPI Interrupt Flag When a serial transfer is complete the SPIF bit is set one and a...

Page 50: ...eading the register causes the Shift Register Receive buffer to be read The UART The AT90S8414 features a full duplex Universal Asynchronous Receiver and Transmitter UART The main features are Baud ra...

Page 51: ...tatus Register USR is set When this bit is set one the UART is ready to receive the next character At the same time as the data is transferred from UDR to the 10 11 bit shift register bit 0 of the shi...

Page 52: ...falling edge of a start bit and the start bit detection sequence is initiated Let sample 1 denote the first zero sample Following the 1 to 0 transition the receiver samples the RXD pin at sample 8 9 a...

Page 53: ...receiver is disabled This means that the PD0 pin can be used as a general I O pin When RXEN is set the UART Receiver will be connected to the PD0 pin regardless of the setting of the DDD0 bit in DDRB...

Page 54: ...ting UDR UDRE is set one during reset to indicate that the transmitter is ready Bit 4 FE Framing Error This bit is set if a Framing Error condition is detected i e when the stop bit of an incoming cha...

Page 55: ...9 9 Bit Characters When this bit is set one transmitted and received characters are 9 bit long plus start and stop bits The 9 th bit is read and written by using the RXB8 and TXB8 bits in UCR respecti...

Page 56: ...Baud Rate 7 3728 MHz Error 8 MHz Error 9 216 MHz Error 11 059 MHz Error 2400 UBRR 191 0 0 UBRR 207 0 2 UBRR 239 0 0 UBRR 287 4800 UBRR 95 0 0 UBRR 103 0 2 UBRR 119 0 0 UBRR 143 0 0 9600 UBRR 47 0 0 U...

Page 57: ...0 0 Bit 7 ACD Analog Comparator Disable When this bit is set one the power to the analog comparator is switched off This bit can be set at any time to turn off the analog comparator It is most common...

Page 58: ...tput Edge 1 1 Comparator Interrupt on Rising Output Edge Note When changing the ACIS1 ACIS0 bits The Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR regis...

Page 59: ...ue on each Port A pin When reading PORTA the PORTA Data Latch is read and when reading PINA the logical values present on the pins are read PORTA AS GENERAL DIGITAL I O All 8 bits in PORT A are equal...

Page 60: ...gister PORTB 18 Data Direction Register DDRB 17 and the Port B Input Pins PINB 16 The Port B Input Pins address is read only while the Data Register and the Data Direction Register are read write All...

Page 61: ...B2 DDB1 DDB0 DDRB Read Write R W R W R W R W R W R W R W R W Initial value 0 0 0 0 0 0 0 0 THE PORT B INPUT PINS ADDRESS PINB Bit 7 6 5 4 3 2 1 0 16 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PIN...

Page 62: ...red zero and with the internal MOS pull up resistor switched off PB3 is cleared zero this pin also serves as the negative input of the on chip analog comparator AIN0 PORTB Bit 2 AIN0 Analog Comparator...

Page 63: ...T90S8414 Preliminary 4 63 PORT B SCHEMATICS Note that all port pins are synchronized The synchronization latches are however not shown in the figures Figure 47 PORTB Schematic Diagram Pins PB0 and PB1...

Page 64: ...4 64 AT90S8414 Preliminary Figure 48 PORTB Schematic Diagram Pins PB2 and PB3 Figure 49 PORTB Schematic Diagram Pin PB4...

Page 65: ...AT90S8414 Preliminary 4 65 Figure 50 PORTB Schematic Diagram Pin PB5 Figure 51 PORTB Schematic Diagram Pin PB6...

Page 66: ...d low they will source current IIL if the internal pullups are activated The PORT C pins have alternate functions related to the optional external data SRAM PORT C can be configured to be the high ord...

Page 67: ...ERAL DIGITAL I O All 8 bits in PORT C are equal when used as digital I O pins PCn General I O pin The DDCn bit in the DDRC register selects the direction of this pin if DDCn is set one PCn is configur...

Page 68: ...4 68 AT90S8414 Preliminary Figure 53 PORTC Schematic Diagram Pins PC0 PC7...

Page 69: ...nal interrupt 0 input PD3 INT1 External interrupt 1 input PD4 OC0 Timer Counter0 Output compare match output PD5 OC1A Timer Counter1 Output compareA match output PD6 WR Write strobe to external memory...

Page 70: ...OR PORTD RD PORTD Bit 7 RD is the external data memory read control strobe WR PORTD Bit 6 WR is the external data memory write control strobe OC1 PORTD Bit 5 OC1 Output compare match output The PD5 pi...

Page 71: ...The internal pull up MOS resistor can be activated as described above See the interrupt description for further details and how to enable the source TXD PORTD Bit 1 TXD is the serial UART output pin...

Page 72: ...4 72 AT90S8414 Preliminary Figure 55 PORTD Schematic Diagram Pin PD1 Figure 56 PORTD Schematic Diagram Pins PD2 and PD3...

Page 73: ...AT90S8414 Preliminary 4 73 Figure 57 PORTD Schematic Diagrams Pin PD4 and PD5 Figure 58 PORTD Schematic Diagram Pin PD6...

Page 74: ...unprogrammed U or can be programmed P to obtain the additional features listed in Table 22 Table 22 Lock Bit Protection Modes Program Lock Bits Protection Type Mode LB1 LB2 1 U U No program lock feat...

Page 75: ...d Serial Downloading Both the Program and Data memory arrays can be programmed using the serial SPI bus while R E S E T is pulled to GND The serial interface consists of pins SCK MOSI input and MISO o...

Page 76: ...4 76 AT90S8414 Preliminary SERIAL PROGRAMMING ALGORITHM To program and verify the AT90S8414 in the serial programming mode the following sequence is recommended See four byte instruction formats in...

Page 77: ...The Program or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction The selected memory location is first automatically erase...

Page 78: ...ram Memory 0110 H000 xxxx aaaa bbbb bbbb iiii iiii Write H high or low data i to Program memory at word address a b Read EEPROM Memory 1010 0000 xxxx xxxx bbbb bbbb oooo oooo Read data o from EEPROM m...

Page 79: ...listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated i...

Page 80: ...Reset Pulldown Resistor 10 50 KW ICC Power Supply Current Active Mode 3V 4MHz 3 5 mA Idle Mode 3V 4MHz 1000 mA ICC Power Down Mode 2 WDT enabled 3V 50 mA WDT disabled 3V 1 mA VACIO Analog Comparator...

Page 81: ...ress Hold After ALE Low 10 10 ns tRLRH RD Pulse Width 150 3 tck 2 ns tWLWH WR Pulse Width 50 tck 2 ns tRLDV RD Low to Valid Data In 10 10 ns tRHDX Data Hold After RD 0 0 ns tRHDZ Data Float After RD 2...

Page 82: ...rms External Clock Drive Symbol Parameter VCC 2 7 V to 6 0 V VCC 4 0 V to 6 0 V Units Min Max Min Max 1 tCLCL Oscillator Frequency 0 10 0 24 MHz tCLCL Clock Period 100 41 7 ns tCHCX High Time 40 16 7...

Page 83: ...e Package Operation Range AT90S8414 JC AT90S8414 PC 44J 40P6 Commercial 0 C to 70 C AT90S8414 JI AT90S8414 PI 44J 40P6 Industrial 40 C to 85 C Package Type 44J 44 Lead Plastic J Leaded Chip Carrier PL...

Page 84: ...erved 25 ICR1H Timer Counter1 Input Capture Register High Byte 4 41 24 ICR1L Timer Counter1 Input Capture Register Low Byte 4 41 23 Reserved 22 Reserved 21 WDTCR WDE WDP2 WDP1 WDP0 4 44 20 Reserved 1F...

Page 85: ...al if Rd Rr PC PC 2 or 3 None 1 2 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in...

Page 86: ...d Program Memory R0 Z None 3 IN Rd P In Port Rd P None 1 OUT P Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 BIT AND BIT TEST IN...

Page 87: ...AT90S8414 Preliminary 4 87...

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