914
32072H–AVR32–10/2012
AT32UC3A3
34.3
Block Diagram
Figure 34-1. ABDAC Block Diagram
34.4
I/O Lines Description
34.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
34.5.1
I/O Lines
The output pins used for the output bitstream from the Audio Bitstream DAC may be multiplexed
with IO lines.
Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the
Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.
Table 34-1.
I/O Lines Description
Pin Name
Pin Description
Type
DATA0
Output from Audio Bitstream DAC Channel 0
Output
DATA1
Output from Audio Bitstream DAC Channel 1
Output
DATAN0
Inverted output from Audio Bitstream DAC Channel 0
Output
DATAN1
Inverted output from Audio Bitstream DAC Channel 1
Output
Clock Generator
Equalization FIR
COMB
(INT=128)
Sigma-Delta
DA-MOD
Equalization FIR
COMB
(INT=128)
Sigma-Delta
DA-MOD
bit_clk
DATA0
DATA1
GCLK_ABDAC
sample_clk
CHANNEL0[15:0]
Audio Bitstream DAC
PM
User Interface
CHANNEL1[15:0]
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
