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32072H–AVR32–10/2012
AT32UC3A3
8.4.1
Power Management
The RTC remains operating in all sleep modes except Static mode. Interrupts are not available
in DeepStop mode.
8.4.2
Clocks
The RTC can use the system RC oscillator as clock source. This oscillator is always enabled
whenever this module is active. Please refer to the Electrical Characteristics chapter for the
characteristic frequency of this oscillator (f
RC
).
The RTC can also use the 32 KHz crystal oscillator as clock source. This oscillator must be
enabled before use. Please refer to the Power Manager chapter for details.
The clock for the RTC bus interface (CLK_RTC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
RTC before disabling the clock, to avoid freezing the RTC in an undefined state.
8.4.3
Interrupts
The RTC interrupt request line is connected to the interrupt controller. Using the RTC interrupt
requires the interrupt controller to be programmed first.
8.4.4
Debug Operation
The RTC prescaler is frozen during debug operation, unless the OCD system keeps peripherals
running in debug operation.
8.5
Functional Description
8.5.1
RTC Operation
8.5.1.1
Source clock
The RTC is enabled by writing a one to the Enable bit in the Control Register (CTRL.EN). The
16-bit prescaler will then increment on the selected clock. The prescaler cannot be read or writ-
ten, but it can be reset by writing a one to the Prescaler Clear bit in CTRL register (CTRL.PCLR).
The 32KHz Oscillator Select bit in CTRL register (CTRL.CLK32) selects either the RC oscillator
or the 32 KHz oscillator as clock source (defined as INPUT in the formula below) for the
prescaler.
The Prescale Select field in CTRL register (CTRL.PSEL) selects the prescaler tapping, selecting
the source clock for the RTC:
8.5.1.2
Counter operation
When enabled, the RTC will increment until it reaches TOP, and then wraps to 0x0. The status
bit TOPI in Interrupt Status Register (ISR) is set to one when this occurs. From 0x0 the counter
will count TOP+1 cycles of the source clock before it wraps back to 0x0.
f
RTC
f
INPUT
2
⁄
PSEL
1
+
(
)
=
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
