Atmel AT32UC3A3128, Manual

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452
32072H–AVR32–10/2012
AT32UC3A3
Figure 22-8. Slave Transmitter with Multiple Data Bytes
Figure 22-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF
22.8.4 Slave Receiver Mode
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared one
CLK_TWIS cycle after the relevant address match bit in the same register is set).
After the address phase, the following is repeated:
1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to
receive. This is necessary in order to know which of the received bytes is the PEC byte.
NBYTES can also be used to count the number of bytes received if using DMA.
2. Receive a byte. Set SR.BTF when done.
3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise
NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is
used.
4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordi-
nary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC
is enabled and the last byte received was a PEC byte (indicated by NBYTES equal to
zero), The TWIS will automatically return an ACK if the PEC value was correct, other-
wise a NAK will be returned.
5. If STOP is received, SR.TCOMP will be set.
6. If REPEATED START is received, SR.REP will be set.
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the
A DATA n A S DADR R DATA n+5 A P DATA n+m N
TCOMP
TXRDY
Write THR (Data n)
NBYTES set to m
STOP sent by master
TWD
Write THR (Data n+1) Write THR (Data n+m)
Last data sent
DATA (LSB) N P
TWCK
SR.NAK
SR.BTF
t
1
t
1
t
1
: (CLK_TWIS period) x 2
TWD