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32072H–AVR32–10/2012
AT32UC3A3
13.6
Bus Matrix Connections
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU Data master interface.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, HMATRIX
SCFG4 register is associated with the Embedded CPU SRAM Slave Interface.
Table 13-2.
High Speed Bus masters
Master 0
CPU Data
Master 1
CPU Instruction
Master 2
CPU SAB
Master 3
PDCA
Master 4
DMACA HSB Master 1
Master 5
DMACA HSB Master 2
Master 6
USBB DMA
Table 13-3.
High Speed Bus slaves
Slave 0
Internal Flash
Slave 1
HSB-PB Bridge A
Slave 2
HSB-PB Bridge B
Slave 3
AES
Slave 4
Embedded CPU SRAM
Slave 5
USBB DPRAM
Slave 6
EBI
Slave 7
DMACA Slave
Slave 8
HRAMC0
Slave 9
HRAMC1
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
