44
45
English
the precharge command.
Secondary Timing
Fail Count
The number of training failure/retries required before boot from recovery mode.
RAS# Cycle Time (tRC)
The number of memory clock cycles from and activate command to another activate
command.
RAS to RAS Delay (tRRD_S)
The number of clock clocks between two rows activated in different banks of the
same rank.
RAS to RAS Delay (tRRD_L)
The number of clock clocks between two rows activated in different banks of the
same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
Write to Read Delay (tWTR_S)
The number of clocks between the last valid write operation and the next read com-
mand to the same internal bank.
Write to Read Delay (tWTR_L)
The number of clocks between the last valid write operation and the next read com-
mand to the same internal bank.
Write Recovery Time (tWR)
The amount of delay that must elapse after the completion of a valid write opera-
tion, before an active bank can be precharged.
Trcpage (tMAW,MAC)
The minimum average time in memory clock cycles within a refresh window from
an activate command to another activate command.
TrdrdScL
The minimum number of cycles from the last clock of virtual CAS of the first read-
burst operation to the clock in which CAS is asserted for a following read-burst
operation in the same chipselect in the same bank group.
