Artesyn MVME5100, Programmer'S Reference Manual, Page: 51 / 318

Product Data and Memory Maps
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
51
TBEN0
Processor 0 Time Base Enable. When this bit is cleared, the TBEN pin of Processor 0 will be
driven low. When this bit is set, the TBEN pin is driven high.
TBEN1
This bit is not used.
1.5.12 NVRAM/RTC & Watchdog Timer
The MVME5100’s NVRAM/RTC and Watchdog Timer functions are supplied by an M48T37V
device and is fully compliant with the PowerPlusII internal programming configuration. The
M48T37V provides 32K of non-volatile SRAM, a time-of-day clock, and a watchdog timer.
Accesses to the M48T37V is accomplished via three registers: the NVRAM/RTC Address Strobe
0 Register, the NVRAM/RTC Address Strobe 1 Register, and the NVRAM/RTC Data Port Register.
The NVRAM/RTC Address Strobe 0 Register latches the lower 8 bits of the address and the
NVRAM/RTC Address Strobe 1 Register latches the upper 5 bits of the address
REQUIRED OR OPTIONAL X X X X X X O R
Table 1-14 TBEN Bit Register (continued)
REG TBEN Bit Register - Offset 80C0h
Table 1-15 M48T37V Access Registers
Required of
Optional
Offset Address Function
This Group
Optional
80C8 NVRAM/RTC Address Strobe 0 (A7-A0)
80D0 NVRAM/RTC Address Strobe 1 (A15-A8)
80D8 NVRAM/RTC Data Register