Artesyn MVME5100, Programmer'S Reference Manual, Page: 277 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
277
7.
Wait for at least one SDRAM refresh to complete. A simple way to do this is to wait for the
32-bit counter to increment at least 100 times. (Refer to
32-Bit Counter
on page 266
for
more information). Note that the refdis control bit must not be set in the ECC Control
Register.
8.
Now that at least one refresh has occurred since SDRAM was last accessed, it is okay to write
to the SDRAM control registers.
a.
Program the SDRAM Speed Attributes Register using the information obtained in steps
3 and 4 and the fact that the swr_dp and tdp bits should be set to 1’s.
b. Program the SDRAM Base Address Register (Blocks A/B/C/D) and the SDRAM Base
Address Register (Blocks E/F/G/H). Each block’s base address should be programmed
so that it is an even multiple of its size. (The size information was obtained in step 5). If
the isa_hole bit is to be set this may be a good time to do that also. Refer to
Revision
ID/General Control Register on page 232 for more information.
c.
Program the SDRAM Enable and Size Register (Blocks A,B,C,D) and the SDRAM Enable
and Size Register (Blocks E,F,G,H). Use the information from step 5 for this. Only those
blocks that exist should be enabled. Also, only those that exist should be programmed
with a non-zero size.
9.
Wait for at least one SDRAM refresh to complete. A simple way to do this is to wait for the
32-bit counter to increment at least 100 times (refer to
32-Bit Counter
on page 266
more
information). Note that the refdis control bit must not be set in the ECC Control Register.
3.4.3.6 Optional Method for Sizing SDRAM
Generally SDRAM block sizes can be determined by using SPD information (refer to SDRAM
Control Registers Initialization Example on page 271 ).
Sizing SDRAM
Another method for sizing SDRAM is as follows:
1.
Initialize the SMC’s control register bits to a known state.
a. Clear the isa_hole bit (refer to Vendor/Device Register on page 232 for more
information.)
b. Make sure the CLK Frequency Register matches the operating frequency.