Artesyn MVME5100, Programmer'S Reference Manual, Page: 263 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
263
A simple way to meet these requirements is to use the following sequence:
1. Make sure all accesses to SDRAM are done.
2. Wait for the “32-Bit Counter” (refer to 32-Bit Counter on page 266 ) to increment at least
100 times.
3. Perform the write/writes to this register (and other SMC registers if desired).
4. Wait again for the “32-Bit Counter” to increment at least 100 times before resuming
accesses to SDRAM.
cl3
When cl3 is cleared, the SMC assumes that the SDRAM runs with a CAS_ latency of 2. When cl3
is set, the SMC assumes that it runs with a CAS_ latency of 3. Note that writing so as to change
cl3 from 1 to 0 or vice-versa causes the SMC to perform a mode-register-set operation to the
SDRAM array. The moderegister- set operation updates the SDRAM’s CAS latency to match cl3.
trc0,1,2
Together trc0,1,2 determine the minimum number of clock cycles that the SMC assumes the
SDRAM requires to satisfy its Trc parameter. These bits are encoded as follows:
tras0,1
Table 3-44 Trc Encoding
trc0,1,2 Minimum Clocks for Trc
%000 8
%001 9
%010 10
%011 11
%100 reserved
%101 reserved
%110 6
%111 7