Artesyn MVME5100, Programmer'S Reference Manual, Page: 192 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
192
3.2 Functional Description
The following sections describe the logical function of the SMC. The SMC has interfaces
between the PowerPC bus and SDRAM, ROM/Flash, and its Control and Status Register sets
(CSR).

SDRAM Accesses on page 193

SDRAM Organization on page 196

PPC60x Bus Interface on page 196

SDRAM ECC on page 198

ROM/Flash Interface on page 201

I2C Interface on page 208

Refresh/Scrub on page 226

CSR Accesses on page 226
Figure 3-4 Hawk’s System Memory Controller Block Diagram