Artesyn MVME5100, Programmer'S Reference Manual, Page: 163 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
163
WXFTx
Write Any FIFO Threshold. This field is used by the PHB to determine a FIFO threshold at which
to start writing data into local memory during any PCI write transaction. Once the threshold is
exceeded and the write has begun, the PHB will continue to empty its FIFO until it can no longer
create a cache line. This field is only applicable if write-posting has been enabled. The encoding
of this field is shown in the above table. The PCI Slave Offset Registers (PSOFFx) contain offset
information associated with the mapping of PCI memory space to PPC memory space. The field
within the PSOFFx registers is defined as follows:
PSOFFx
PCI Slave Offset. This register contains a 16-bit offset that is added to the upper 16 bits of the
PCI address to determine the PPC address used for transfers from PCI to the PPC bus. This offset
allows PPC resources to reside at addresses that would not normally be visible from PCI.
2.5.2.9 CONFIG_ADDRESS Register
The description of the CONFIG_ADDRESS register is presented in three perspectives: from the
PCI bus, from the PPC bus in big-endian mode, and from the PPC bus in little-endian mode.
Note that the view from the PCI bus is purely conceptual, since there is no way to access the
CONFIG_ADDRESS register from the PCI bus.
Table 2-64 Conceptual perspective from the PCI bus
Offset $CFB $CFA $CF9 $CF8
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CONFIG_ADDRESS
EN
BUS DEV FUN REG
Operation
R/W
R R/W R/W R/W REG
R R
Reset
1
$00 $00 $00 0 $00
0 0
Table 2-65 Perspective from the PPC bus in Big Endian mode
Offset $CF8 $CF9 $CFA $CFB
Bit (DH)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name CONFIG_ADDRESS
REG DEV FUN BUS
EN
Operation R/W
R R
R/W R/W R/W
R/W
R