Artesyn MVME5100, Programmer'S Reference Manual, Page: 161 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
161
2.5.2.8 PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
The PCI Slave Attribute Registers (PSATTx) contain attribute information associated with the
mapping of PCI memory space to PPC memory space. The fields within the PSATTx registers are
defined as follows:
INV
Invalidate Enable. If set, the PPC Master will issue a transfer type code which specifies the
current transaction should cause an invalidate for each PPC transaction originated by the
corresponding PCI Slave. The transfer type codes generated are shown in
Table 2-6 on page 75 .
GBL
Global Enable. If set, the PPC Master will assert the GBL_ pin for each PPC transaction originated
by the corresponding PCI Slave.
RAEN
Read Ahead Enable. If set, read ahead is enabled for the corresponding PCI Slave.
WPEN
Write Post Enable. If set, write posting is enabled for the corresponding PCI Slave.
WEN
Write Enable. If set, the corresponding PCI Slave is enabled for write transactions.
Table 2-61 PCI Slave Attribute/ Offset (0,1,2 and 3) Registers
Offset $04
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PSOFFx PSATTx
WXF
T1
WXF
T0
RXF
T1
RXF
T0
RMF
T1
RMF
T0
REN WEN WPEN RAEN GB
L
INV
Operation R/W
R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W
Reset $0000
1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0