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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

MVME5100 Single Board Computer Programmer’s Reference (6806800H17B

)

146

Write Enable. If set, the corresponding PPC Slave is enabled for write transactions.

WPEN

Write Post Enable. If set, write posting is enable for the corresponding PPC Slave.

MEM

PCI Memory Cycle. If set, the corresponding PPC Slave will generate transfers to or from PCI 
memory space. When clear, the corresponding PPC Slave will generate transfers to or from PCI 
I/O space using the addressing mode defined by the IOM field.

IOM

PCI I/O Mode. If set, the corresponding PPC Slave will generate PCI I/O cycles using spread 
addressing as defined in the section titled Generating PCI Cycles. When clear, the 
corresponding PPC Slave will generate PCI I/O cycles using contiguous addressing. This field 
only has meaning when the MEM bit is clear.

2.5.1.13 PPC Slave Address (3) Register

The PPC Slave Address Register 3 (XSADD3) contains address information associated with the 
mapping of PPC memory space to PCI I/O space. XSADD3 (in conjunction with 
XSOFF3/XSATT3) is the only register group that can be used to initiate access to the PCI 
CONFIG_ADDRESS ($80000CF8) and CONFIG_DATA ($80000CFC) registers. The power up 
value of XSADD3 (and XSOFF3/XSATT3) are set to allow access to these special register spaces 
without PPC register initialization.

The fields within XSADD3 are defined as follows:

Table 2-46 PPC Slave Address (3) Register 

Address

MSADD3 - $FEFF0058

Bit

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17  18 19 20 21 22 23 24 25 26 27 28 29 30 31

Name

XSADD3

START

END

Operation

R/W

R/W

Reset

Regbase 0xfeff0000 => $8000

Regbase 0xfefe0000 => $9000

Regbase 0xfeff0000 => $8080

Regbase 0xfefe0000 => $9080

Summary of Contents for MVME5100

Page 1: ...MVME5100 Single Board Computer Programmer s Reference P N 6806800H17B July 2014...

Page 2: ...anges from time to time in the content hereof without obligation of Artesyn to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for pers...

Page 3: ...ECC Memory 35 1 3 9 P2 I O Modes 36 1 3 10 Serial Presence Detect SPD Definitions 36 1 4 Hawk ASIC 36 1 4 1 Hawk I2C interface and configuration information 37 1 4 2 Vital Product Data VPD and Serial...

Page 4: ...ssor Interrupt Controller 63 2 1 Overview 63 2 1 1 Features 63 2 2 Block Diagram 65 2 3 Functional Description 66 2 3 1 Architectural Overview 66 2 3 2 PPC Bus Interface 67 2 3 3 PCI Bus Interface 79...

Page 5: ...isters 152 2 5 3 MPIC Registers 166 3 System Memory Controller SMC 187 3 1 Overview 187 3 1 1 Bit Ordering Convention 187 3 1 2 Features 187 3 1 3 Block Diagrams 189 3 2 Functional Description 192 3 2...

Page 6: ...ndian Issues 288 4 4 1 Processor Memory Domain 290 4 4 2 MPIC s Involvement 291 4 4 3 PCI Domain 291 A MVME5100 VPD Reference Information 293 A 1 Vital Product Data VPD Introduction 293 A 1 1 How to R...

Page 7: ...ammer s Reference 6806800H17B 7 B VMEbus Mapping Example 309 B 1 Introduction 309 C Related Documentation 313 C 1 Artesyn Embedded Technologies Embedded Computing Documentation 313 C 2 Manufacturer s...

Page 8: ...MVME5100 Single Board Computer Programmer s Reference 6806800H17B Contents 8 Contents Contents...

Page 9: ...Register S1 52 Table 1 17 Geographical Address Register VME board 53 Table 1 18 Extended Features Register 1 54 Table 1 19 Board Last Reset Register 55 Table 1 20 Extended Features Register 2 56 Tabl...

Page 10: ...Table 2 28 Parking Field 131 Table 2 29 Priority Field 132 Table 2 30 Parking Field 132 Table 2 31 Hierarchy Field 133 Table 2 32 Hierarchy Field Mixed Priority Scheme 133 Table 2 33 Hardware Control...

Page 11: ...able 2 64 Conceptual perspective from the PCI bus 163 Table 2 65 Perspective from the PPC bus in Big Endian mode 163 Table 2 66 Perspective from the PPC bus in Little Endian mode 164 Table 2 67 Concep...

Page 12: ...MHz 206 Table 3 6 PPC60x Bus to ROM Flash Access Timing 80ns 100 MHz 207 Table 3 7 PPC60x Bus to ROM Flash Access Timing 50ns 100 MHz 207 Table 3 8 PPC60x Bus to ROM Flash Access Timing 30ns 100 MHz...

Page 13: ...Blocks E F G H 261 Table 3 43 SDRAM Speed Attributes Register 262 Table 3 44 Trc Encoding 263 Table 3 45 tras Encoding 264 Table 3 46 Address Parity Error Log Register 265 Table 3 47 Address Parity E...

Page 14: ...MVME5100 Single Board Computer Programmer s Reference 6806800H17B 14 List of Tables Table C 2 Manufacturer s Publications 314 Table C 3 Related Specifications 315...

Page 15: ...ttle Endian Data Swap 98 Figure 2 9 Serial Mode Interrupt Scan 111 Figure 2 10 MPIC Block Diagram 116 Figure 3 1 Hawk Used with Synchronous DRAM in a System 189 Figure 3 2 Hawk s System Memory Control...

Page 16: ...MVME5100 Single Board Computer Programmer s Reference 6806800H17B 16 List of Figures...

Page 17: ...agnostics Manual As of the printing date of this manual the MVME5100 is available in the configurations shown below Part Number Description 450 MHz MPC750 Commercial Models MVME5100 016x 450 MHz MPC75...

Page 18: ...ne RJ 45 10 100 Ethernet connector includes 3 row DIN P2 adapter module and cable for 8 bit SCSI MVME761 011 Transition module Two DB 9 async serial port connectors two HD 26 sync async serial port co...

Page 19: ...ter 4 Hawk Programming Details provides a summary of the Hawk programming details that are relevant to every day programming functions including a listing of the Hawk MPIC External Interrupts the 8259...

Page 20: ...r I2 C Inter Integrated Circuit IDSEL Identification Device Select IPMC Internet Protocol Multimedia Communications KB Kilo Byte L2CR Cache Control Register LED Light Emitting Diode MB Mega Byte MB s...

Page 21: ...threading SPD Serial Presence Detect SRAM Static Random Access Memory TBEN Time Base Enable UART Universal Asynchronous Receiver Transmitter UCD User Configuration Data VME Virtual Machine Environment...

Page 22: ...escription Repeated item for example node 1 node 2 node 12 Omission of information from example command that is not necessary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3...

Page 23: ...iated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a sign...

Page 24: ...ctions were made to Table 4 1 in Chapter 4 Additions were made to Appendix A Releated Documentation Appendix B VPD Information wasadded Thissectiontitled AboutthisManual was also added V5100A PG3 07 2...

Page 25: ...oard Hawk ASIC provides the bridge function between the processor s bus and the PCI bus It provides 32 bit addressing and 64 bit data however 64 bit addressing dual address cycle is not supported The...

Page 26: ...Serial Port s Routed to the Front Panel RJ 45 Connector COM1 and On Board Header COM2 DualEthernetInterfaces oneroutedtotheFrontPanelRJ 45 one routed to the Front Panel RJ 45 or optionally routed to P...

Page 27: ...and Memory Maps MVME5100 Single Board Computer Programmer s Reference 6806800H17B 27 The following block diagram illustrates the architecture of the MVME5100 Single Board Computer Figure 1 1 MVME5100...

Page 28: ...age 32 1 2 1 Processor Memory Map The processor memory map configuration is under the control of the PCI Host Bridge PHB and System Memory Controller SMC portions of the Hawk ASIC The Hawk adjusts sys...

Page 29: ...2 Default Processor Memory Map Processor Address Size Definition Start End 0000 0000 7FFF FFFF 2 GB Not Mapped 8000 0000 8080 FFFF 8 MB 64 KB Zero based PCI ISA I O Space 8081 0000 FEF7 FFFF 2 GB 24 M...

Page 30: ...ess 0x50000000 1 G 256 M Table 1 3 Suggested CHRP Memory Map Processor Address Size Definition Notes Start End 0000 0000 top_dram dram_size System Memory onboard DRAM 1 top_dram F3FF FFFF 4 G dram_siz...

Page 31: ...via Hawk ASIC The actual PowerPlus II size of each ROM FLASH bank may vary The first 1 MB of ROM FLASH Bank A appears at this range after a reset if the rom_b_rv control bit is cleared If the rom_b_r...

Page 32: ...tion For detailed PCI memory maps including suggested CHRP and PREPcompatible memory maps refer to the Hawk portion of this manual Chapter 2 Hawk PCI Host Bridge Multi Processor Interrupt Controller a...

Page 33: ...755 and MPC7410 processors The maximum external processor bus speed is 100 MHz Parity checking is supported for the system address and data busses 1 3 2 Processor Type Identification The processor ver...

Page 34: ...of data and 8 bits of address L2 cache port on the processor The L2 cache normally operates in copyback modes and supports system cache coherency through snooping Parity generation and checking may be...

Page 35: ...awk PCI Host Bridge Multi Processor Interrupt Controller and Chapter 3 System Memory Controller SMC for additional programming information Memory block size is dependent upon the SDRAM devices install...

Page 36: ...or the SBC and PMC modes are described in the MVME5100 Single Board Computer Installation and Use manual 1 3 10 Serial Presence Detect SPD Definitions The MVME5100 SPD uses the SPD JEDEC standard defi...

Page 37: ...and Serial Data Line SDA composed of two 256 x 8 Serial EEPROM s This interface has master only capability and is used to communicate the configuration information to a slave I2C serial EEPROM A separ...

Page 38: ...ce Detect SPD information consists of data items that are pertinent to board configuration and operation For information on the VPD and SPD data formats and definitions refer to Appendix A MVME5100 VP...

Page 39: ...anine card PCI Expansion Slot The section discusses the following topics PCI Arbitration Assignments for Hawk ASIC on page 40 The Ethernet Controller on page 40 PMC PCI Expansion Slots on page 41 The...

Page 40: ...Intel GD82559ER Fast Ethernet PCI controller chips Port 1 s 10BaseT 100BaseTx interface is routed through the front panel Port 2 s Ethernet interface is routed to either the front panel or the P2 conn...

Page 41: ...ital Product Data VPD Serial EEPROM which provides storage of the MVME5100 hardware configuration Refer to Appendix B MVME5100 VPD Reference Information for more information on VPD Refer to the Intel...

Page 42: ...uct Data and Memory Maps MVME5100 Single Board Computer Programmer s Reference 6806800H17B 42 1 5 4 The Universe ASIC The VMEbus interface is provided by the Universe ASIC Figure 1 3 VMEbus Master Map...

Page 43: ...ASIC Programmable mapping performed via PCI Slave images in Universe ASIC Programmable mapping performed via Special Slave image SLSI in Universe ASIC Table 1 7 IDSEL Mapping for PCI Devices Device N...

Page 44: ...Hawk External Register Bus Address Assignments This section will describe in detail the Hawk External Register Bus Address Assignments on MVME5100 The address range for the External Register Set on M...

Page 45: ...Register Name 0 1 2 3 4 5 6 7 FEF88000 THIS GROUP REQUIRED UART 1 RBR THR FEF88010 UART 1 IER FEF88020 UART 1 IIR FCR FEF88030 UART 1 LCR FEF88040 UART 1 MCR FEF88050 UART 1 LSR FEF88060 UART 1 MSR FE...

Page 46: ...erPlus II Programming Model for UART Registers The following tables reflect this model FEF88200 THIS GROUP OPTIONAL UART 2 RBR THR FEF88210 UART 2 IER FEF88220 UART 2 IIR FCR FEF88230 UART 2 LCR FEF88...

Page 47: ...the PPMC750 1 5 8 Status Register The MVME5100 implementation of this Register is fully compliant with the PowerPlus II programming model with exceptions to bits RD5 RD6 and RD7 as identified in the t...

Page 48: ...e baud output clock of the TL16C550 UART referenced to the 1 8432 MHz UART oscillator This signal can be used as a timing reference FUSE This bit provides the current state of the FUSE signal If set a...

Page 49: ...he ABORT_ signal If set ABORT_ is not active If cleared the ABORT_ signal is active GREEN_LED This bit not used 1 5 10 MODRST Bit Register The MODRST Bit register provides the means to reset the board...

Page 50: ...is cleared 1 5 11 TBEN Bit Register The MVME5100 implementation of this register is fully compliant with the PowerPlus II Programming Specification with exceptions to Bit RD6 as indicated in the table...

Page 51: ...olatile SRAM a time of day clock and a watchdog timer Accesses to the M48T37V is accomplished via three registers the NVRAM RTC Address Strobe 0 Register the NVRAM RTC Address Strobe 1 Register and th...

Page 52: ...t particular bit and a logic 1 means the header switch is in the off position SRH Register Bit 0 is associated with Pin 1 and Pin 16 of the SRH and SRH Register Bit 7 is associated with Pin 8 and Pin...

Page 53: ...ess Register is an 8 bit read only register This register reflects the states of the geographical address pins on the 5 row 160 pin P1 connector Figure 1 4 SRH Pin Assignments Table 1 17 Geographical...

Page 54: ...is no PMC module installed in position 2 If cleared the PMC module is installed MMEZ1_P_L Memory Mezzanine 1 present When set there is no memory mezzanine 1 present When cleared there is a memory mez...

Page 55: ...occurred WDT2 Watchdog Timer Level 2 Reset If set a level 2 Watchdog timer reset has occurred CPCIRST CompactPCI Reset If set a CompactPCI RST reset has occurred Not applicable for the MVME5100 CMDRS...

Page 56: ...esent If set there is no PCIX device installed If cleared the PCIX slot contains a PCI Mezzanine Card 1 6 IPMC7xx ISA Bus Resources The following subsections provide resource information pertaining to...

Page 57: ...ace a PS 2 mouse interface a PS 2 floppy port two async serial ports and a parallel port Refer to the PC87308VUL Data Sheet for additional details and programming information The following table shows...

Page 58: ...riority than the Z85230 ESCC in the interrupt daisy chain The following list the registers associated with accessing these two devices 1 6 3 2 Z8536 CIO Port Pins The assignment for the Port pins of t...

Page 59: ...FAIL LED to be lit PA7 IDREQ_ Output Module ID Request low true PB0 TM4_MID2 Input Port 4 Test Mode when IDREQ_ 1 Module ID Bit 2 when IDREQ_ 0 PB1 DSR4_MID3 Input Port 4 Data Set Ready when IDREQ_ 1...

Page 60: ...3 EIA232 DCE 01 W3876B01 0 0 0 0 0 1 Module 3 EIA232 DTE 01 W3877B01 0 0 0 0 1 0 Module 3 EIA530 DCE 01 W3878B01 0 0 0 0 1 1 Module 3 EIA530 DTE 01 W3879B01 0 0 1 1 1 1 Module 3 Not Installed 0 1 0 0...

Page 61: ...ignments PIB Priority PIB Label Controller DMA Assignment Highest Channel 0 DMA1 Serial Port 3 Receiver Z85230 Port A Rx Channel 1 Serial Port 3 Transmitter Z85230 Port A Tx Channel 2 Floppy Drive Con...

Page 62: ...Product Data and Memory Maps MVME5100 Single Board Computer Programmer s Reference 6806800H17B 62...

Page 63: ...synchronous bus capable of transfer rates of 132 MB sec in 32 bit mode or 264 MB sec in 64 bit mode using a 33 MHz clock The chapter discusses the following topics Block Diagram Functional Descriptio...

Page 64: ...upport for 16 external interrupt sources and two processors Supports 15 programmable Interrupt and Processor Task priority levels Supports the connection of an external 8259 for ISA AT compatibility D...

Page 65: ...Hawk PCI Host Bridge Multi Processor Interrupt Controller MVME5100 Single Board Computer Programmer s Reference 6806800H17B 65 2 2 Block Diagram Figure 2 1 Hawk PCI Host Bridge Block Diagram...

Page 66: ...PCI Decode and PPC Decode blocks The control register logic is contained in the PCI Registers and PPC Registers blocks The clock phasing and reset control logic is contained within the PPC PCI Clock...

Page 67: ...data is captured from the PPC60x bus within the PPC Input block From there the data is fed into the PCI FIFO The PCI Output block removes the data from the FIFO and presents it to the PCI bus The MPI...

Page 68: ...pace into PPC address space using four programmable map decoders These decoders provide windows of access to the PCI bus from the PPC bus The most significant 16 bits of the PPC address are compared w...

Page 69: ...ample of this is shown in the following figure Care should be taken to ensure that all programmable decoders decode unique address ranges since overlapping address ranges will lead to undefined operat...

Page 70: ...posted regardless of the write posting attribute within the associated map decoder register If the PPC Slave is servicing a posted write transaction and the PPC FIFO can accept the transaction the ass...

Page 71: ...ake the data FIFO the limiting factor for write posting Four single beat transactions make the command FIFO the limiting factor If either limit is exceeded then any pending PPC transactions is delayed...

Page 72: ...e beat transactions as needed until the next highest cache line boundary is reached If a write transaction ends on a non cache line boundary then the PPC Master finishes the transaction with as many s...

Page 73: ...needed This can be accomplished by changing the WXFT Write Any Fifo Threshold field within the PSATTx registers to recharacterize PHB write posting mechanism The FIFO threshold should be lowered to a...

Page 74: ...IFO Therefore caution should be exercised when using the prefetch option within coherent memory space The PPC Master never performs prefetch reads beyond the address range mapped within the PCI Slave...

Page 75: ...uirements of the FIFO The Bug Hog mode was primarily designed to assist with system level debugging and is not intended for normal modes of operation It is a brute force method of guaranteeing that al...

Page 76: ...ion field XID within the GCSR When the PPC Arbiter is enabled the PHB receives requests and issue grants for itself and for the other three bus masters The XID field is determined by the PPC Arbiter T...

Page 77: ...tem level debug functions provided by the PPC Arbiter The PPC Arbiter has the optional ability to flatten the PPC60x bus pipeline Flattening can be imposed uniquely on single beat reads single beat wr...

Page 78: ...s no response to a transfer request The time out length of the bus timer is determined by the XBT field within the GCSR The PPC Timer is designed to handle the case where an address tenure is not clos...

Page 79: ...ion is being timed by its own PCI bus Any other bridge devices listening to this signal understand that the current pending cycle should not be subject to a time out period During non PCI bound cycles...

Page 80: ...ese control registers support a mapping scheme that is functionally similar to the PCI to PPC mapping scheme described in the section titled PPC Address Mapping PPC Bus Address Space The PHB maps PPC...

Page 81: ...This offset allows devices to reside at any PPC address independent of the PCI address map An example of this is shown in the following figure All PHB address decoders are prioritized so that program...

Page 82: ...Slave will hold off the master with wait states while each beat of data is being transferred The PCI Slave issues TRDY_ only after the data transfer has successfully completed on the PPC bus If a rea...

Page 83: ...ng of the byte enables against the address being presented and assert SERR in the event there is an error The PCI Slave only honors the Linear Incrementing addressing mode The PCI Slave performs a dis...

Page 84: ...etry disconnect with no data transfer While within a lock sequence the PCI Slave retries all non locking masters At the completion of a lock sequence between the times the two locks are released on th...

Page 85: ...ss any PCI resource represented by the PHB results in the PCI Slave issuing a retry Parity The PCI Slave supports address parity error detection data parity generation and data parity error detection...

Page 86: ...nsaction into two parts The first part starts on the address presented with the CWF transfer request and continues up to the end of the current cache line The second transfer starts at the beginning o...

Page 87: ...efinitely until the transaction is completed the transaction is aborted by the target or if the transaction is aborted due to a PHB detected bridge lock The same happens if the target responds with a...

Page 88: ...first transaction If at least one command is pending within the PPC FIFO The PCI Master always removes its request when it receives a disconnect or a retry ThereisacasewherethePCIMastercouldassertareq...

Page 89: ...below If the MEM bit is set the PHB performs Memory addressing on the PCI bus The PHB takes the PPC bus address applies the offset specified in the XSOFFx register and maps the result directly to the...

Page 90: ...ults in unpredictable operation For example an I O transfer of four bytes starting at address 80000010 is considered a valid transfer An I O transfer of four bytes starting at address 80000011 is cons...

Page 91: ...onfiguration consequently I O space The XSADD3 XSOFF3 register group is initialized at reset to allow PCI I O access starting at address 80000000 The powerup location Little Endian disabled of the CON...

Page 92: ...e PHB for a special cycle the host processormustwritea32bitvaluetotheCONFIG_ADDRESSregister Thecontentsofthewrite aredefinedlaterinthischapterundertheCONFIG_ADDRESSregisterdefinition Afterthewrite to...

Page 93: ...bit is added to hold grant asserted for an agent that initiates a lock cycle Once a lock cycle is detected the grant is held asserted until the PCI LOCK_ pin is released This feature works only when t...

Page 94: ...PARB6 and PARB5 are defined in group1 PARB4 and PARB3 are defined in group 2 PARB2 and PARB1 are defined in group 3 PARB0 and HAWKaredefinedingroup4 Arbitrationissetforroundrobinmodebetweenthe2reques...

Page 95: ...HAWK PARB6 5 PARB4 3 PARB2 1 010 group 3 group 4 group 1 group 2 PARB2 1 PARB0 HAWK PARB6 5 PARB4 3 011 group 2 group 3 group 4 group 1 PARB4 3 PARB2 1 PARB0 HAWK PARB6 5 000 is the default setting i...

Page 96: ...CI arbiter control register is set the grant associated with the agent initiating the lock cycle will be held asserted until the lock cycle is complete If this bit is clear the arbiter does not distin...

Page 97: ...PHB may be programmed to perform the endian conversion described below The section discusses the following topics When PPC Devices are Big Endian on page 97 When PPC Devices are Little Endian on page...

Page 98: ...7B 98 This is shown in the following figure 2 3 4 2 When PPC Devices are Little Endian When all PPC devices are operating in little endian mode the originating address is modified to remove the exclus...

Page 99: ...nto multiple aligned transfers on the PPC bus 2 3 4 3 PHB Registers The PHB registers are not sensitive to changes in Big Endian and Little Endian mode With respect to the PPC bus but not always the a...

Page 100: ...dress of a PIACK cycle is undefined therefore address modification during Little Endian mode is not an issue 2 3 5 Error Handling The PHB is capable of detecting and reporting the following errors to...

Page 101: ...n which cannot be associated with a particular PPC master would be a PCI system error 2 3 6 Watchdog Timers PHB features two watchdog timers called Watchdog Timer 1 WDT1 and Watchdog Timer 2 WDT2 Alth...

Page 102: ...ister is used to read the instantaneous count value of the watchdog timer Programming the Watchdog Timers To program the Watchdog Timers through the WDTxCNTL register 1 Arm the WDTxCNTL register by wr...

Page 103: ...md feff0060 FEFF0060 000FFFFF 0000FFFF 000FFFFF 0000FFFF FEFF0070 03FE0000 00000000 00000000 FFFFFFFF PPC1 Bug mw feff0068 55 b Effective address FEFF0068 Effective data 55 PPC1 Bug md feff0060 FEFF00...

Page 104: ...h slaves means that a bridge lock has happened To resolve this one of the slaves must back out of its currently pending transaction This will allow the other stalled slave to proceed with its transact...

Page 105: ...the PCI FIFO from getting filled A similar case exists with regard to PCI read cycles Having the bridge lock resolution associated with a particular PCI FIFO threshold would allow the PPC Master to g...

Page 106: ...or benign requests and will unconditionally remove a speculative request after 16 clocks The PHB considers the speculative PCI request mode to be the default mode of operation If this is not desired t...

Page 107: ...er the PCI slave hasacceptedawrite postedtransactionandthetransactionhasnotcompletedonthePPC bus The PPC Slave address decode logic settles out several clocks after the assertion of TS_ at which time...

Page 108: ...All of the sampled pins are cascaded with several layers of registers to eliminate problems with hold time The following table summarizes the hardware configuration options that relate to the PHB Tabl...

Page 109: ...on page 111 Interrupt Source Priority on page 111 Processor s Current Task Priority on page 112 Nesting of Interrupt Events on page 112 Spurious Vector Generation on page 112 Interprocessor Interrupts...

Page 110: ...r timer sources and one Hawk internal error interrupt source The externally sourced interrupts 1 through 15 have two modes of activation low level or active high positive edge External interrupt 0 can...

Page 111: ...exactly 16 external interrupts 2 4 4 CSR s Readability Unless explicitly specified all registers are readable and return the last value written The exceptions are the IPI dispatch registers and the E...

Page 112: ...ocessing for the highest priority in service interrupt 2 4 8 Spurious Vector Generation Under certain circumstances the MPIC will not have a valid vector to return to the processor during an interrupt...

Page 113: ...or interrupt This Hawk internal error interrupt request is an active low level sensitive interrupt The interrupt delivery mode for this interrupt is distributed When the OPIC is disabled the Hawk inte...

Page 114: ...upts multicast delivery is not supported The interrupt is delivered to a processor when the priority of the interrupt is greater than the priority contained in the task register for that processor whe...

Page 115: ...00 Single Board Computer Programmer s Reference 6806800H17B 115 The section discusses the following topics Program Visible Registers on page 117 Interrupt Pending Register IPR on page 117 Interrupt Se...

Page 116: ...t Bridge Multi Processor Interrupt Controller MVME5100 Single Board Computer Programmer s Reference 6806800H17B 116 In Service Register ISR on page 118 Interrupt Router on page 118 Figure 2 10 MPIC Bl...

Page 117: ...stination bit Since the internally generated interrupts use direct delivery mode with multicast capability there are two bits in the IPR one for each processor associated with each IPI and Timer inter...

Page 118: ...here is one bit for each possible interrupt priority and one bit for each possible interrupt source 2 4 14 6 Interrupt Router The Interrupt Router monitors the outputs from the ISR s Current Task Prio...

Page 119: ...is not present is ISR_1 The priority from IRR_0 is greater than the highest priority in ISR_0 The priority from IRR_0 is greater than the Task Register_0 contents The contents of Task Register_0 is l...

Page 120: ...nal interrupts the MSRee bit is set to 1 MPIC blocks interrupts from sources with equal or lower priority until an End of Interrupt is received for that interrupt source Interrupts from higher priorit...

Page 121: ...ge 122 Interrupt Acknowledge Register on page 122 8259 Mode on page 122 Current Task Priority Level on page 123 2 4 16 1 Interprocessor Interrupts Four interprocessor interrupt IPI channels are provid...

Page 122: ...register which is used to signal the end of processing for a particular interrupt event If multiple nested interrupts are in service the EOI command terminates the interrupt service of the highest pr...

Page 123: ...ptsmaycontinuetooccurforanindeterminatenumberofcyclesafterthe processor has updated the task priority register If this is not acceptable the interrupt controller architecture should recommend that if...

Page 124: ...hapter It is possible to place the base address of the PPC registers at either FEFF0000 or FEFE0000 Having two choices for where the base registers reside allows the system designer to use two of the...

Page 125: ...PPC Slave Offset Attribute 0 1 and 2 Registers on page 145 PPC Slave Address 3 Register on page 146 PPC Slave Offset Attribute 3 Registers on page 147 WDTxCNTL Registers on page 148 WDTxSTAT Register...

Page 126: ...EFF0064 WDT1STAT FFEF0068 WDT2CNTL FEFF006C WDT2STAT FEFF0070 GPREG0 Upper FEFF0074 GPREG0 Lower FEFF0078 GPREG1 Upper FEFF007C GPREG1 Lower Name VENID DEVID Operation R R Reset 1057 4803 Table 2 20 P...

Page 127: ...duplicated in the PCI Configuration Registers 2 5 1 2 Revision ID Register REVID Revision ID This register identifies the PHB revision level This register is duplicated in the PCI Configuration Regis...

Page 128: ...of the PHB operates in the Bus Hog mode Bus Hog mode means the PPC Master continually requests the PPC bus for the entire duration of each transfer If Bus Hog is not enabled the PPC master requests th...

Page 129: ...are passed on to the MPIC If cleared PHB detected errors are passed on to the processor 0 INT pin XIDx PPC ID This field is encoded as shown below to indicate who is currently the PPC bus master This...

Page 130: ...e below FBWx Flatten Burst Write This field is used by the PPCArbiter to control how bus pipelining will be affected after all burst write cycles The encoding of this field is shown in the table below...

Page 131: ...d state of the PPC Arbiter If set the PPC Arbiter is enabled and is acting as the system arbiter If cleared the PPC Arbiter is disabled and external logic is implementing the system arbiter Refer to P...

Page 132: ...ed by the PCI Arbiter to establish a particular bus parking scheme The encoding of this field is shown in the following table HIERx Table 2 29 Priority Field PRI Priority Scheme 00 Fixed 01 Round Robi...

Page 133: ...highest to lowest 000 PARB6 PARB5 PARB4 PARB3 PARB2 PARB1 PARB0 HAWK 001 HAWK PARB6 PARB5 PARB4 PARB3 PARB2 PARB1 PARB0 010 PARB0 HAWK PARB6 PARB5 PARB4 PARB3 PARB2 PARB1 011 PARB1 PARB0 HAWK PARB6 PA...

Page 134: ...abled and external logic is implementing the system arbiter Please refer to the section titled PHB Hardware Configuration for more information on how this bit gets set 2 5 1 5 Hardware Control Status...

Page 135: ...a transaction is pending within the PHB FIFOs WLRTx Write Lock Resolution Threshold This field is used by the PHB to determine a PPC bound write FIFO threshold at which a bridge lock resolution will c...

Page 136: ...st Register XPAD is used to specify a scale factor for the prescaler to ensure that the time base for the bus timer is 1MHz The scale factor is calculated as follows XPAD 256 Clk where Clk is the freq...

Page 137: ...B is acting as a PPC bus master An address parity error will be created on the corresponding PPC address parity bus if a bit is set For example setting APE0 will cause AP0 to be generated incorrectly...

Page 138: ...T register will be used to assert the MCHK output to the current address bus master When this bit is clear MCHK will not be asserted PPERM PCI Parity Error Machine Check Enable When this bit is set th...

Page 139: ...rupt controller When this bit is clear no interrupt will be asserted PSERI PCI System Error Interrupt Enable When this bit is set the PSER bit in the ESTAT register will be used to assert an interrupt...

Page 140: ...he PHB detects a data bus parity error It may be cleared by writing a 1 to it writing a 0 to it has no effect When the XDPEM bit in the EENAB register is set the assertion of this bit will assert MCHK...

Page 141: ...egister is set the assertion of this bit will assert an interrupt through the MPIC PRTA PCI Master Received Target Abort This bit is set when the PCI master receives target abort to terminate a PCI tr...

Page 142: ...originated the transfer in which the error occurred The encoding scheme is identical to that used in the GCSR register TBST Transfer Burst This bit is set when the transfer in which the error occurre...

Page 143: ...ng scheme is identical to that used in the GCSR register COMMx PCI Command This field contains the PCI command of the PCI transfer in which the error occurred BYTEx PCI Byte Enable This field contains...

Page 144: ...ers XSADD0 XSADD1 and XSADD2 contains address information associated with the mapping of PPC memory space to PCI memory I O space The fields within the XSADDx registers are defined as follows START St...

Page 145: ...ave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PPC address to determine the PCI address used for transfers from the PPC bus to PCI This offset allows PCI r...

Page 146: ...will generate PCI I O cycles using contiguous addressing This field only has meaning when the MEM bit is clear 2 5 1 13 PPC Slave Address 3 Register The PPC Slave Address Register 3 XSADD3 contains a...

Page 147: ...ce to PCI I O space The field within the XSOFF3 register is defined as follows XSOFFx PPC Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PPC address to d...

Page 148: ...When clear the corresponding PPC Slave generates PCI I O cycles using contiguous addressing 2 5 1 15 WDTxCNTL Registers The Watchdog Timer Control Registers WDT1CNTL and WDT2CNTL are used to provide...

Page 149: ...will be enabled A zero written to this bit will disable the timer The ENAB bit may only be modified on the second step of a successful two step arming process ARM ARMED This read only bit indicates t...

Page 150: ...PPC6 Bug mw feff0068 55 b Effective address FEFF0068 Effective data 55 PPC6 Bug mw feff0068 aa88 h Effective address FEFF0068 Effective data AA88 PPC6 Bug md feff006c FEFF006C 0000B26D 03FE4000 000000...

Page 151: ...E4000 00000000 FEFF0078 00000000 FFFFFFFE FFFFFFFF FFFFFFFF PPC6 Bug 2 5 1 16 WDTxSTAT Registers The Watchdog Timer Status Registers WDT1STAT and WDT2STAT are used to provide status information from t...

Page 152: ...ions to reserved registers will be treated as no ops That is the access will be completed normally on the bus and the data will be discarded Read accesses to reserved or unimplemented registers will b...

Page 153: ...e Address 0 1 2 and 3 Registers on page 160 PCI Slave Attribute Offset 0 1 2 and 3 Registers on page 161 CONFIG_ADDRESS Register on page 163 CONFIG_DATA Register on page 165 MMBAR 14 18 7C PSADD0 80 P...

Page 154: ...Registers The Command Register COMMAND provides coarse control over the PHB ability to generate and respond to PCI cycles The bits within the COMMAND register are defined as follows IOSP Table 2 54 V...

Page 155: ...arity errors that it detects and continue normal operation SERR System Error Enable This bit enables the SERR_ output pin If clear the PHB will never drive SERR_ If set the PHB will drive SERR_ active...

Page 156: ...y writing it to 1 writing a 0 has no effect RCVMA Received Master Abort This bit is set by the PCI Master whenever its transaction except for Special Cycles is terminated by a master abort It is clear...

Page 157: ...PCI Host Bridge Program Class Code 00 Not Used 2 5 2 4 Header Type Register The Header Type Register Header identifies the PHB as follows Header Type 00 Single Function Configuration Header Operation...

Page 158: ...bit is hard wired to zero BASE Base Address These bits define the I O space base address of the MPIC control registers The MIBAR decoder is disabled when the BASE value is zero 2 5 2 6 MPIC Memory Bas...

Page 159: ...to zero to indicate that the MPIC registers can be located anywhere in the 32 bit address space PRE Prefetch This bit is hard wired to zero to indicate that the MPIC registers are not prefetchable BAS...

Page 160: ...articular memory area on the PCI buswhichwillbeusedtoaccessPPCbusresources Thevalueofthisfieldwillbecomparedwith the upper 16 bits of the incoming PCI address END End Address This field determines the...

Page 161: ...nsfer type codes generated are shown in Table 2 6 on page 75 GBL GlobalEnable Ifset thePPCMasterwillasserttheGBL_pinforeachPPCtransactionoriginated by the corresponding PCI Slave RAEN Read Ahead Enabl...

Page 162: ...d ahead has been enabled The encoding of this field is shown in the table below RXFTx Read Any FIFO Threshold This field is used by the PHB to determine a FIFO threshold at which to continue prefetchi...

Page 163: ...ess to determine the PPC address used for transfers from PCI to the PPC bus This offset allows PPC resources to reside at addresses that would not normally be visible from PCI 2 5 2 9 CONFIG_ADDRESS R...

Page 164: ...onfiguration cycle Special Cycles This field must be written with all ones DEV Device Number Configuration Cycles Identifies a target s physical PCI device number Refer to the section on Generating PC...

Page 165: ...alCycles WritingaonetothisbitenablesCONFIG_DATAtoSpecialCycletranslation Ifthis bit is a zero subsequent accesses to CONFIG_DATA will be passed though as I O Cycles 2 5 2 10 CONFIG_DATA Register The d...

Page 166: ...e 170 Vendor Identification Register on page 172 Processor Init Register on page 172 IPI Vector Priority Registers on page 173 Spurious Vector Register on page 174 Timer Frequency Register on page 174...

Page 167: ...VE of the PHB has two decoders for generating the MPIC select These decoders will generate a select and acknowledge all accesses which are in a reserved 256K byte range If the index into that 256K blo...

Page 168: ...ION REGISTER 10050 INT SRC 3 VECTOR PRIORITY REGISTER 10060 INT SRC 3 DESTINATION REGISTER 10070 INT SRC 4 VECTOR PRIORITY REGISTER 10080 INT SRC 4 DESTINATION REGISTER 10090 INT SRC 5 VECTOR PRIORITY...

Page 169: ...GISTER PROC 0 20050 IPI 2 DISPATCH REGISTER PROC 0 20060 IPI 3 DISPATCH REGISTER PROC 0 20070 CURRENT TASK PRIORITY REGISTER PROC 0 20080 IACK REGISTER P0 200a0 EOI REGISTER P0 200b0 IPI 0 DISPATCH RE...

Page 170: ...ler This value reports what level of the specification is supported by this implementation Version level of 02 is used for the initial release of the MPIC specification 2 5 3 3 Global Configuration Re...

Page 171: ...In the pass through mode interrupt source 0 is passed directly through to the processor 0 INT pin MPIC is essentially disabled In the mixed mode 8259 interrupts are delivered using the priority and d...

Page 172: ...sion number of Hawk s MPIC 2 5 3 5 Processor Init Register P1 PROCESSOR 1 Writing a 1 to P1 will assert the Soft Reset input of processor 1 Writing a 0 to it will negate the SRESET signal P0 Table 2 7...

Page 173: ...terrupt is set in the IPR the interrupt request will be generated ACT ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when...

Page 174: ...he frequency in Hz of the clock source for the global timers Following reset this register contains zero The system initialization code must initialize this register to one eighth the MPIC clock frequ...

Page 175: ...er transitions from a 1 to a 0 CC CURRENT COUNT The current count field decrements while the Count Inhibit bit is the Base Count Register is zero When the timer counts down to zero the Current Count r...

Page 176: ...gister and the CI bit transitions from a 1 to a 0 it is copied into the corresponding Current Count register and the toggle bit in the Current Count register is cleared When the timer counts down to z...

Page 177: ...t is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR PRIORITY Interrupt priority 0 is the lowest and 15 is the highest Note that a priority l...

Page 178: ...OR 0 The interrupt is directed to processor 0 2 5 3 13 External Source Vector Priority Registers Table 2 83 Timer Destination Registers Offset Timer 0 01130 Timer 1 01170 Timer 2 011B0 Timer 3 011F0 B...

Page 179: ...edge OnlyExternal Interrupt Source 0 uses this bit in this register For external interrupts 1 through 15 this bit is hard wired to 0 SENSE SENSE This bit sets the sense for external interrupts Setting...

Page 180: ...The interrupt is pointed to processor 1 P0 PROCESSOR 0 The interrupt is pointed to processor 0 2 5 3 15 Hawk Internal Error Interrupt Vector Priority Register Table 2 85 External Source Destination R...

Page 181: ...Register or In Service Register is set SENSE SENSE This bit sets the sense for Hawk s internal error interrupt It is hardwired to 1 to enable active low level sensitive interrupts PRIOR PRIORITY Inter...

Page 182: ...s pointed to processor 0 2 5 3 17 Interprocessor Interrupt Dispatch Registers Table 2 87 Hawk Internal Error Interrupt Destination Register Offset 10210 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 183: ...R 1 The interrupt is directed to processor 1 P0 PROCESSOR 0 The interrupt is directed to processor 0 2 5 3 18 Current Task Priority Registers There is one Task Priority Register per processor Priority...

Page 184: ...will return a value of FF hex The associated bit in the Interrupt Pending Register is cleared Reading this register will update the In Service register VECTOR Vector This vector is returned when the...

Page 185: ...Code values other than 0 are currently undefined Data values written to this register are ignored zero is assumed Writing to this register signals the end of processing for the highest priority inter...

Page 186: ...Hawk PCI Host Bridge Multi Processor Interrupt Controller MVME5100 Single Board Computer Programmer s Reference 6806800H17B 186...

Page 187: ...the information for using the device in a system programming it in a system and testing it is contained here The chapter discusses the following topics Functional Description Programming Model Softwa...

Page 188: ...able Interrupt on Single Double Bit Error Error address and Syndrome Log Registers for Error Logging Does not provide TEA_ on Double Bit Error Chip has no TEA_ pin ROM Flash Interface Two blocks with...

Page 189: ...Diagrams The following figure depicts a Hawk as it would be connected with SDRAMs in a system Figure 3 1 shows the SMC s internal data paths Figure 3 2 shows the overall SDRAM connections Figure 3 3 s...

Page 190: ...System Memory Controller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 190 Figure 3 2 Hawk s System Memory Controller Internal Data Paths...

Page 191: ...System Memory Controller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 191 Figure 3 3 Overall SDRAM Connections 4 Blocks using Register Buffers...

Page 192: ...The SMC has interfaces between the PowerPC bus and SDRAM ROM Flash and its Control and Status Register sets CSR SDRAM Accesses on page 193 SDRAM Organization on page 196 PPC60x Bus Interface on page 1...

Page 193: ...data one on each clock Hence the SMC can provide the four beats of data with zero idle clocks between each beat 3 2 1 2 Single beat Reads Writes Because of start up addressing and completion overhead...

Page 194: ...cs The bits that control this configuration are located in the SDRAM Speed Attributes Register which is described in the Register portion of this section Refer to Table 3 1 for some specific timing nu...

Page 195: ...t Read after 1 Beat Read SDRAM Bank Active Page Hit 5 1 Beat Write after idle SDRAM Bank Active or Inactive 5 1 Beat Write after 1 Beat Write SDRAM Bank Active Page Miss 13 1 Beat Write after 1 Beat W...

Page 196: ...he slave interfaceisthemechanismforallaccessestoSDRAM ROM Flash andtheinternalandexternal register sets This section discusses the following topics Responding to Address Transfers on page 196 Completi...

Page 197: ...parity by software bits that can force the generation of wrong even parity During write cycles to the SMC the SMC checks each of the eight PPC60x data byte lanes and its corresponding DP signal for o...

Page 198: ...CLM_ OncyclesthatselecttheSMC theSMCsamplesL2CLM_onthesecond rising edge of the CLK input after the assertion of TS_ If L2CLM_ is high the SMC responds normally to the cycle If it is low the SMC ignor...

Page 199: ..._ The SMC can however assert machine check MCHK0_ on double bit error Table 3 2 Error Reporting Error Type Single Beat Four Beat Read Single Beat Write Four Beat Write Scrub Single Bit Error Terminate...

Page 200: ...0x bus cycle normally Do not perform the write portion of the read modify write cycle to SDRAM Assert Hawk s internal error interrupt if so enabled 2 Assert MCHK0_ if so enabled N A 1 This cycle is no...

Page 201: ...per configuration This allows the board designer to use external jumpers to enable disable Block A B ROM Flash as the source of reset vectors The base address for each block is software programmable A...

Page 202: ...ions in this chapter In order to place code correctly in the ROM Flash devices address mapping information is required Table 2 3 shows how PPC60x addresses map to the ROM Flash addresses when ROM Flas...

Page 203: ...XFFFFFF 7FFFFF Lower X0000000 000000 Upper X0000001 000000 Upper X0000002 000000 Upper X0000003 000000 Upper X0000004 000000 Lower X0000005 000000 Lower X0000006 000000 Lower X0000007 000000 Lower X00...

Page 204: ...Upper X3FFFFF9 7FFFFF Upper X3FFFFFA 7FFFFF Upper X3FFFFFB 7FFFFF Upper X3FFFFFC 7FFFFF Lower X3FFFFFD 7FFFFF Lower X3FFFFFE 7FFFFF Lower X3FFFFFF 7FFFFF Lower Table 3 4 PPC60x to ROM Flash 64 Bit Wi...

Page 205: ...001 Lower X000000E 000001 Lower X000000F X3FFFFF0 000001 7FFFFE Lower Upper X3FFFFF1 7FFFFE Upper X3FFFFF2 7FFFFE Upper X3FFFFF3 7FFFFE Upper X3FFFFF4 7FFFFE Lower X3FFFFF5 7FFFFE Lower X3FFFFF6 7FFFF...

Page 206: ...OM Flash 64 Bit Width Address Mapping continued PPC60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected Table 3 5 PPC60x Bus to ROM Flash Access Timing 120ns 100 MHz ACCESS TYPE CLOCK PERIODS REQUIRE...

Page 207: ...t Read 1 byte 18 18 18 18 1 Beat Read 2 to 8 bytes 54 18 54 18 1 Beat Write 21 21 21 21 The information in Table 2 5 applies to access timing when configured for devices with an access time equal to 8...

Page 208: ...em may be desirable The EEPROM could maintain the configuration The information in Table 2 6 applies to access timing when configured for devices with an access time equal to 5 clock periods Table 3 8...

Page 209: ...the fast mode The I2 C serial clock SCL is programmable via I2_PRESCALE_VAL bits in the I2 C Clock Prescaler Register The I2 C clock frequency is determined by the following formula I2 C CLOCK SYSTEM...

Page 210: ...d into the I2 C Transmitter Data Register to be transmitted to the slave device Again i2_cmplt and i2_ackin bits must be tested for proper response After the word address is successfully transmitted t...

Page 211: ...0H17B 211 Transmitter Data Register The I2 C Status Register must now be polled to test i2_cmplt bit for the operation complete status The stop sequence will initiate a programming cycle for the seria...

Page 212: ...ntroller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 212 the suggested software flow diagram for programming the I2 C byte write operation Figure 3 5 Programming Sequence for...

Page 213: ...vice Again i2_cmplt and i2_ackin bits must be tested for proper response At this point the slave device is still in a write mode Therefore another start sequence must be sent to the slave to change th...

Page 214: ...806800H17B 214 Data Register The I2 C Status Register must now be polled to test i2_cmplt bit for the operation complete status The stop sequence will relinquish the ASIC master s possession of the I2...

Page 215: ...System Memory Controller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 215 random read operation Figure 3 6 Programming Sequence for I2 C Random Read...

Page 216: ...The i2_cmpltbitbecomessetwhenthedeviceaddressandreadbithavebeentransmitted andthe i2_ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful t...

Page 217: ...00H17B 217 care to the I2 C Transmitter Data Register The I2 C Status Register must now be polled to test i2_cmplt bit for the operation complete status The stop sequence will relinquish the ASIC mast...

Page 218: ...Memory Controller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 218 programming the I2 C current address read operation Figure 3 7 Programming Sequence for I2 C Current Addres...

Page 219: ...when the device address and write bit have been transmitted and the i2_ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of...

Page 220: ...806800H17B 220 must now be polled to test i2_cmplt bit for the operation complete status The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master s...

Page 221: ...System Memory Controller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 221 programming the I2 C page write operation Figure 3 8 Programming Sequence for I2 C Page Write...

Page 222: ...vice is still in a write mode Therefore another start sequence must be sent to the slave to change the mode to read by first setting the i2_start i2_ackout and i2_enbl bits in the I2 C Control Registe...

Page 223: ...00H17B 223 data don t care to the I2 C Transmitter Data Register The I2 C Status Register must now be polled to test i2_cmplt bit for the operation complete status The stop sequence will relinquish th...

Page 224: ...System Memory Controller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 224 diagram for programming the I2 C sequential read operation...

Page 225: ...System Memory Controller SMC MVME5100 Single Board Computer Programmer s Reference 6806800H17B 225 Figure 3 9 Programming Sequence for I2 C Sequential Read...

Page 226: ...or some status 3 2 9 External Register Set The SMC has an external register chip select pin which enables it to talk to an external set of registers This interface is like the ROM Flash interface but...

Page 227: ...hitecture Register Summary Detailed Register Bit Descriptions 3 3 1 CSR Architecture The CSR control and status register set consists of the chip s internal register set and its external register set...

Page 228: ...en RAM A SIZ ram b en RAM B SIZ ram c en RAM C SIZ ram d en RAM D SIZ FEF80018 RAM A BASE RAM B BASE RAM C BASE RAM D BASE FEF80020 CLK FREQUENCY por FEF80028 refdis rwcb derc apien scien dpien sien m...

Page 229: ...SIZ ram f en RAM F SIZ ram g en RAM G SIZ ram h RAM H SIZ FEF800C8 RAM E BASE RAM F BASE RAM G BASE RAM H BASE FEF800D0 cl3 trc0 trc1 trc2 tras0 tras1 swr_dpl tdp trp trcd FEF800E0 apelog APE_TT APE_A...

Page 230: ...eral Control Register on page 232 All empty bit fields are reserved and read as zeros All status bits are shown in italics All control bits are shown with underline All control and status bits are sho...

Page 231: ...Speed Attributes Registers on page 252 Data Parity Error Log Register on page 253 Data Parity Error Address Register on page 254 Data Parity Error Upper Data Register on page 255 Data Parity Error Lo...

Page 232: ...ID General Control Register Table 3 12 Vendor Device Register Address FEF80000 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name VENDID DEVID Operation REA...

Page 233: ...1 aonly_en Normally the SMC responds to address only cycles only if they fall within the address range of one of its enabled map decoders When the aonly_en bit is set the SMC also responds to address...

Page 234: ...rement at least 100 times The wait period needs to happen during the envelope ram a b c d en ram a b c d en enables 60x accesses to the corresponding block of SDRAM when set and disables them when cle...

Page 235: ...4Mx16 5 32MBytes 64Mbit 0010 8Mx8 9 64MBytes 64Mbit 0011 8Mx16 5 64MBytes 128Mbit 0100 16Mx4 18 128MBytes 64Mbit 0101 16Mx8 9 128MBytes 128Mbit 0110 16Mx16 5 128MBytes 256Mbit 0111 32Mx4 18 256MBytes...

Page 236: ...ust happen during the envelope RAM A B C D BASE These control bits define the base address for their block s SDRAM RAM A B C D BASE bits 0 7 8 15 16 23 24 31 correspond to PPC60x address bits 0 7 For...

Page 237: ...4 for 100 MHz The formula is Counter_Output_Frequency Clock Frequency CLK_FREQUENCY For example if the Clock Frequency is 100 MHz and CLK_FREQUENCY is 64 then the counter output frequency is 100 MHz 1...

Page 238: ...15 625 us Some SDRAMs require a refresh rate of 7 8 us 64 ms 8192 rows 7 8 us In order for Hawk 1 or 2 to accommodate such SDRAM s their CLK_FREQUENCY must be programmed with the CLK pin bus clock fre...

Page 239: ...d cleared If a refresh cycle is in process when refdis is updated by a write to this register the update does not take effect until the refresh cycle has completed This prevents the generation of ille...

Page 240: ...t error This can be avoided by disabling scrub writes Also note that writingbadcheck bitscansettheelogbitintheErrorLoggerRegister Thewritingofcheck bits causes the SMC to perform a read modify write t...

Page 241: ...written 3 Duringsingle beatwrites thewriteportionoftheread modifywritehappensregardlessof whether there is a multiple bit error during the read portion No correction of data is attempted Checkbits ar...

Page 242: ...occurs It is cleared by reset or by software writing a one to it The Hawk s internal error interrupt tracks int When int is set Hawk s internal error interrupt is asserted When int is cleared Hawk s...

Page 243: ...was accessing SDRAM at the last logging of a single or multiple bit error by the SMC If escb is 1 it indicates that the scrubber was accessing SDRAM If escb is 0 it indicates that the PPC60x bus mast...

Page 244: ...gged a scrub error esblk0 esblk1 esbik2 are 0 0 0 for Block A 0 0 1 for Block B 0 1 0 for Block C and 0 1 1 for Block D etc scof scof is set by the SBE COUNT register rolling over from FF to 00 It is...

Page 245: ...cb1 These bits increment every time the scrubber completes a scrub of the entire SDRAM When they reach binary 11 they roll over to binary 00 and continue These bits are cleared by power up reset swen...

Page 246: ...etes to all of the blocks of SDRAM When it reaches all 1s it rolls back over to all 0s and continues counting The SCRUB_ADDRESS counter is readable and writable for test purposes Note that when this r...

Page 247: ...appear at an even multiple of its size ROM A BASE is initialized to FF0 at power up or local bus reset rom_a_64 Table 3 24 ROM A Base Size Register Address FEF80050 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 248: ...siz control bits are the size of ROM Flash for Block A They are encoded as shown in Table 2 221 rom_a_rv rom_a_rv and rom_b_rv determine which if either of Blocks A and B is the source of reset vecto...

Page 249: ...allowed The SMC ignores other writes If a valid write is attempted and rom a we is cleared the write does not happen but the cycle is terminated normally See the following table for details of ROM Fl...

Page 250: ...s base address will always appear at an even multiple of its size ROM B BASE is initialized to FF4 at power up or local bus reset rom_b_64 Table 3 28 ROM B Base Size Register Address FEF80050 Bit 0 1...

Page 251: ...b siz The rom b siz control bits are the size of ROM Flash for Block B They are encoded as shown in the following table rom_b_rv rom_b_rv and rom_a_rv determine which if either of Blocks A and B is t...

Page 252: ...with the section titled ROM Flash Read Timing Diagram Writes that change these bits must be enveloped by a period of time in which no accesses to ROM Flash Block A occur A simple way to provide the e...

Page 253: ...data bus during a PPC60x data cycle whose parity the SMC is qualified to check It is cleared by writing a one to it or by power up reset dpe_tt0 4 dpe_tt is the value that was on the TT0 TT4 signals...

Page 254: ...machine check interrupt request pin MCHK0_ true When dpe_me is cleared the Hawk does not assert its MCHK0_ pin based on the dpelog bit GWDP The GWDP0 GWDP7 bits are used to invert the value that is dr...

Page 255: ...E_DL DPE_DL is the value on the lower half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk It is updated only when dpelog goes from 0 to 1 Table 3...

Page 256: ...on a 100 0 MHz system clock Writes to this register will be restricted to 4 bytes only 3 3 3 19 I2 C Control Register i2_start Table 3 36 I2 C Clock Prescaler Register Address FEF80090 Bit 0 1 2 3 4...

Page 257: ...ill automatically clear the i2_stop bit and then set the i2_cmplt bit in the I2 C Status Register i2_ackout When set the I2 C master controller generates an acknowledge on the I2 C bus during read cyc...

Page 258: ...from the I2 C Status Register will clear this bit i2_ackin This bit is set if the addressed slave device is acknowledged to either a start sequence or data writes from the I2 C master controller and c...

Page 259: ...a start sequence with I2_DATAWR 31 1 subsequent writes to the I2 C Transmitter Data Register data don t care will cause the responding slave device to transmit data to the I2 C Receiver Data Register...

Page 260: ...ent at least 100 times The wait period needs to happen during the envelope ram e f g h en ram e f g h en enables accesses to the corresponding block of SDRAM when set and disables them when cleared ra...

Page 261: ...write starts and none should begin until after the write is done A simple way to do this is to perform at least two read accesses to this or another register before and after the write Additionally s...

Page 262: ...s serve two purposes 1 They make sure that all of the SDRAMs are idle ensuring that mode register set operations for cl3 updates work properly and 2 They make sure that no SDRAM accesses happen during...

Page 263: ...s to SDRAM cl3 When cl3 is cleared the SMC assumes that the SDRAM runs with a CAS_ latency of 2 When cl3 is set the SMC assumes that it runs with a CAS_ latency of 3 Note that writing so as to change...

Page 264: ...he minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Tdp parameter When tdp is 0 the minimum time provided for Tdp is 1 clock When tdp is 1 the minimum is 2 clocks...

Page 265: ...the AP0 AP3 signals when the apelog bit was set ape_me Whenape_meisset thetransitionoftheapelogbitfromfalsetotruecausestheHawktopulse its machine check interrupt request pin MCHK0_ true When ape_me i...

Page 266: ...is updated only when apelog goes from 0 to 1 3 3 3 28 32 Bit Counter CTR32 Table 3 47 Address Parity Error Address Register Address FEF800E8 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21...

Page 267: ...TERNAL REGISTER SET interface is similar to that for ROM Flash Block A and B In fact another name for the External Register Set is ROM Flash Block C The differences between Blocks A B and C are that t...

Page 268: ...Register Set interface is disabled and the SMC does not respond to accesses in its designated range except that it responds to the address of this tben register p1_tben When the tben_en bit is set th...

Page 269: ...to be controlled by the Hawk should make note of the address mapping that is shown in Table 3 3 and in Table 3 4 For example when using 8 bit devices the code will be split so that every other 4 byte...

Page 270: ...t ROM Flash while the affected Block is being accessed This generally means that the ROM Flash size base address enable write enable etc are changed only while executing initially in the reset vector...

Page 271: ...ssizebitstomatch The value programmed into the size bits tells the Hawk how big the block is for map decoding and how to translate that block s 60x addresses to SDRAM addresses Programming a block s...

Page 272: ...bus determine which memory blocks are present Using the addressing scheme established by the board designer probe for SPD s to determine which blocks of SDRAM are present SPD byte 0 could be used to...

Page 273: ...d and trc Do not actually update these bits in the Hawk at this time You will use the information from this step later Table 3 51 Deriving tras trp trcd and trc Control Bit Values from SPD Information...

Page 274: ...nd 27 tRC_CLK tRAS tRP T T CLK Period in nanoseconds See Notes 7 8 and 9 0 0 tRC_CLK 6 0 trc 110 6 0 tRC_CLK 7 0 trc 111 7 0 tRC_CLK 8 0 trc 000 8 0 tRC_CLK 9 0 trc 001 9 0 tRC_CLK 10 0 trc 010 10 0 t...

Page 275: ...hin each device If the total number of addresses in a device is A then A ROWS X COLUMNS d Calculate the total number of locations in the block using the results of step 3 and SPD byte 17 If the total...

Page 276: ...ze 3 Value to be programmed into the Block s ram_x_siz bits 4 4M 16 32MB 0001 8M 8 64MB 0010 8M 16 64MB 0011 16M 4 128MB 0100 16M 8 128MB 0101 16M 16 128MB 0110 32M 4 256MB 0111 32M 8 256MB 1000 64M 4...

Page 277: ...set this may be a good time to do that also Refer to Revision ID General Control Register on page 232 for more information c Program the SDRAM Enable and Size Register Blocks A B C D and the SDRAM En...

Page 278: ...A and B are not enabled to respond in the range 00000000 20000000 Refer to ROM A Base Size Register on page 247 and ROM B Base Size Register on page 250 for more information g Make sure that no other...

Page 279: ...s a size of 0MB Its size should be programmed to 0 3 Wait enough time to allow at least 1 SDRAM refresh to occur before beginning any SDRAM accesses Table 3 53 Address Lists for Different Block Size C...

Page 280: ...17 13 rd33 C4 rd49 31 ckd1 02 rd2 2C rd18 0B rd34 C2 rd50 B0 ckd2 04 rd3 2A rd19 8A rd35 A2 rd51 A8 ckd3 08 rd4 E9 rd20 7A rd36 9E rd52 A7 ckd4 10 rd5 1C rd21 07 rd37 C1 rd53 70 ckd5 20 rd6 1A rd22 86...

Page 281: ...8A rd19 AA CA EA 0B rd18 2B 4B 6B 8B AB CB EB 0C 2C rd2 4C rd1 6C 8C rd15 AC CC EC 0D rd14 2D 4D 6D 8D AD CD ED 0E rd13 2E 4E 6E 8E AE CE EE 0F 2F 4F rd44 6F 8F AF CF EF 10 ckd4 30 50 70 rd53 90 B0 rd...

Page 282: ...20 9A BA DA FA 1B 3B 5B 7B 9B BB DB FB 1C rd5 3C 5C 7C 9C BC DC FC 1D 3D rd28 5D 7D 9D BD DD FD 1E 3E 5E 7E 9E rd36 BE DE FE 1F 3F 5F 7F 9F BF DF FF Table 3 55 Single Bit Errors Ordered by Syndrome Co...

Page 283: ...Interrupts on page 285 4 2 1 Hawk MPIC External Interrupts The MVME5100 Hawk MPIC is fully compliant with the industry standard Multi Processor Interrupt Controller Specification Following a power up...

Page 284: ...Alarm 1 Table 4 1 MPIC Interrupt Assignments continued MPIC IRQ Edge Level Polarity Interrupt Source Notes Interrupting device is addressed from Hawk External Register Bus The mapping of interrupt so...

Page 285: ...welve ISA interrupt lines IRQ0 IRQ2 IRQ8_ and IRQ13 are reserved for ISA system interrupts These active low inputs are used for some of the on board PCI devices Since PCI interrupts are defined as lev...

Page 286: ...are the following Power On Reset RESET Switch Watchdog Timer Reset 11 IRQ3 IRQ3 INT1 Level Low COM2 or COM4 Interrupt 12 IRQ4 IRQ4 Level Low COM1 or COM3 Interrupt 13 PIRQB_ IRQ5 Level Low 21554 Seco...

Page 287: ...held in reset Clearing the P1 bit will release the reset This feature can be used by a processor on the host board to disable the local processor while the host processor programs the Bank A on board...

Page 288: ...rate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Target Abort Store Discard write data and terminate bus cycle normally Load Return all 1s an...

Page 289: ...etails MVME5100 Single Board Computer Programmer s Reference 6806800H17B 289 The following figures show how the MVME5100 series handles the endian issue in Big Endian and Little Endian modes Figure 4...

Page 290: ...Big Endian and Little Endian modes However it always treats the external processor memory bus as Big Endian by performing address rearrangement and reordering when running in Little Endian mode The M...

Page 291: ...ess invariance when it is programmed to operate in Big Endian mode with the processor and the memory sub system InLittle Endianmode itreverse rearranges theaddress forPCI boundaccesses andrearranges t...

Page 292: ...Hawk Programming Details MVME5100 Single Board Computer Programmer s Reference 6806800H17B 292...

Page 293: ...ctory Assembly Number e g 01 W3403F01 Serial number of the specific MVME5100 Processor family number e g 750 7410 etc Hardware clock frequencies internal external fixed PCI bus Component configuration...

Page 294: ...srom i Can be used as a byte viewer Indirect block move command ibm addr i Reads the entire SROM block to memory Memory display command md addr Can be used to display a VPD block which has been copie...

Page 295: ...than usual SROM update command update Updates each SROM on the board to the current revision using network files A 1 4 How to Fix Corrupted VPD Information The firmware is designed to reach the promp...

Page 296: ...general reference information It is divided into two major sections VPD Data Definitions which define VPD packet formats and VPD Content Information which includes information on what is actually cont...

Page 297: ...essor bus frequency Integer 4 byte 2 07 04 Reference Clock Frequency in Hertz e g 32 768 decimal etc This value is the frequency of the crystal driving the OSCM Integer 4 byte 2 08 06 Ethernet Address...

Page 298: ...packet Binary 10 BF Reserved C0 FE User Defined Anexampleofauserdefinedpacketcouldbethe type of LCD panel connected in an MPC821 based application FF N A Termination Packet follows the last initializ...

Page 299: ...resent 8 PCO_ISA_CONN1 ISA bus connector 1 present 9 PCO_ISA_CONN2 ISA bus connector 2 present 10 PCO_ISA_CONN3 ISA bus connector 3 present 11 PCO_ISA_CONN4 ISA bus connector 4 present 12 PCO_EIDE1_CO...

Page 300: ...present 36 PCO_KEYBOARD_CONN Keyboard connector present 37 PCO_MOUSE_CONN Mouse connector present 38 PCO_VGA1_CONN VGA device 1 connector present 39 PCO_SPEAKER_CONN Speaker connector present 40 PCO_...

Page 301: ...ion Data Byte Offset Field Size Bytes Field Mnemonic Field Description 00 2 FMC_MID Manufacturer s Identifier FFFF Undefined Not Applicable 02 2 FMC_DID Manufacturer s Device Identifier FFFF Undefined...

Page 302: ...A 4 L2 Cache Configuration Data Byte Offset Field Size Bytes Field Mnemonic Field Description 00 2 L2C_MID Manufacturer s Identifier FFFF Undefined Not Applicable 02 2 L2C_DID Manufacturer s Device Id...

Page 303: ...physical organization above 00 256K 01 512K 02 1M 03 2M 04 4M 0D 1 L2C_TYPE_BACKSIDE L2 Cache Type Backside Configurations 00 Late Write Sync 1nS Hold Differential Clock Parity 01 Pipelined Sync Burst...

Page 304: ...have exactly one VPD revision packet A 1 11 1 SROM_CRC C srom_crc generate CRC data for the passed buffer description This function s purpose is to generate the CRC for the passed buffer call argumen...

Page 305: ...t index dbit msb crc 0xffffffff for index 0 index elements_n index cbyte elements_p for dbit 0 dbit 8 dbit msb crc 31 1 crc 1 if msb cbyte 1 crc 0x04c11db6 crc 1 cbyte 1 crc_flipped 0 for index 0 inde...

Page 306: ...lculated checksum A 1 11 3 Serial Presence Detect SPD Checksum Calculation The checksum field Byte 63 designates the checksum for checking data integrity similar to parity for bytes 0 62 It is written...

Page 307: ...esses 0 62 and eliminating all but the low order byte The low order byte is the Checksum Table A 6 Example of a Checksum Calculation SPD Byte Address Serial PD Convert to Decimal 00 0x00 0010 0100 36...

Page 308: ...MVME5100 VPD Reference Information MVME5100 Single Board Computer Programmer s Reference 6806800H17B 308...

Page 309: ...d other MVME boards In this description all 64MB of both boards are mapped onto the VMEbus in A32 D32 space The specific slave image register set used was arbitrary but based most nearly on those setu...

Page 310: ...C000 0000 the first 1MB 100 0000 is set aside for other devices on the PCI Local Bus that require PCI Memory PowerPC addresses from C000 0000 to DFFF FFFF are presented zero based on the PCI Local Bu...

Page 311: ...a PPC generated address of 8100 0000 appears on the PCI Local Bus as 8100 0000 Again the same translation calculation is required to adjust this address to be presented as 0000 0000 on the VMEbus In...

Page 312: ...VMEbus Mapping Example MVME5100 Single Board Computer Programmer s Reference 6806800H17B 312...

Page 313: ...www artesyn com computing 2 Under SUPPORT click TECHNICAL DOCUMENTATION 3 Under FILTER OPTIONS click the Document types drop down list box to select the type of document you are looking for 4 In the S...

Page 314: ...5 1 800 267 7231 613 592 0714 Fax 613 592 1320 http www tundra com page cfm tree_id 100008 Universe II 9000000 MD303 01 Dallas Semiconductor DS1621 Digital Thermometer and Thermostat Dallas Semiconduc...

Page 315: ...mber Peripheral Component Interconnect PCI Interface Specification Revision 2 1 PCI Special Interest GroupP O Box 14070 Portland Oregon 97214 4070 Marketing Help Line Telephone 503 696 6111 Document S...

Page 316: ...Related Documentation MVME5100 Single Board Computer Programmer s Reference 6806800H17B 316...

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