Artesyn MVME5100, Programmer'S Reference Manual, Page: 131 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
131
PRI
Priority. If set, the PPC Arbiter will impose a rotating between CPU0 grants. If cleared, a fixed
priority will be established between CPU0 and CPU1 grants, with CPU0 having a higher priority
than CPU1.
PRKx
Parking. This field determines how the PPC Arbiter will implement CPU parking. The encoding
of this field is shown in the table below.
ENA
Enable. This read only bit indicates the enabled state of the PPC Arbiter. If set, the PPC Arbiter
is enabled and is acting as the system arbiter. If cleared, the PPC Arbiter is disabled and external
logic is implementing the system arbiter. Refer to
PHB Hardware Configuration for more
information on how this bit gets set.
The PCI Arbiter Register (PARB) provides control and status for the PCI Arbiter. Refer to PCI
Arbiter for more information. The bits within the PARB register are defined as follows:
PRIx
01 None
10 Flatten always
11 Flatten if switching masters
Table 2-28 Parking Field
PRK CPU Parking
00 None
01 Park on last CPU
10 Park always on CPU0
11 Park always on CPU1
Table 2-27 Flatten Single Write Field (continued)
FBR/FSR/FBW/FSW Effects on Bus Pipelining