Artesyn MVME5100, Programmer'S Reference Manual, Page: 111 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
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In parallel mode, 16 external signal pins are used as interrupt inputs (interrupts 0 through 15).
Using PCLK as a reference, external logic will pulse SI_STA one clock period indicating the
beginning of an interrupt scan period. On the same clock period that SI_STA is asserted,
external logic will feed the state of EXT0 on the SI_DAT pin. External logic will continue to
sequentially place EXT1 through EXT15 on SI_DAT during the next 15 clock periods. This
process may be repeated at any rate, with the fastest possible next assertion of SI_STA on the
clock following the sampling of EXT15. Each scan process must always scan exactly 16 external
interrupts.
2.4.4 CSR’s Readability
Unless explicitly specified, all registers are readable and return the last value written. The
exceptions are the IPI dispatch registers and the EOI registers which return zeros on reads, the
interrupt source ACT bit which returns current interrupt source status, the interrupt
acknowledge register, which returns the vector of the highest priority interrupt which is
currently pending, and reserved bits which returns zeros. The interrupt acknowledge register
is also the only register which exhibits any read side-effects.
2.4.5 Interrupt Source Priority
Each interrupt source is assigned a priority value in the range from 0 to 15 where 15 is the
highest. In order for delivery of an interrupt to take place, the priority of the source must be
greater than that of the destination processor. Therefore, setting a source priority to zero
inhibits that interrupt.
Figure 2-9 Serial Mode Interrupt Scan