Artesyn MaxCore MC1600, Installation And Use Manual, Page: 43 / 118

System Overview
MC1600 Extreme Edge Server Installation and Use (6806870A02A) 41
1.6.2.1 Real Time Clock
A real-time clock circuit is implemented for each CPU. This circuit is backed up by an on-board
coin cell battery. The CPUs synchronize their system time to the BMC.
1.6.2.2 Trusted Platform Module (TPM)
A TPM 1.2 compliant implementation is used on the Extreme Edge Server.
The TPM is connected to the LPC interface of the processor. The SERIRQ output of the device is
connected to the SERIRQ input of the processor.
1.7 Interfaces
1.7.1 PCI Express Interfaces
Each CPU has one x8 PCIe Gen3 interface to the x16 PCIe connector on the base board.
CPU1 has two x4 PCIe Gen3 interfaces to M.2 NVMe sockets on the base board. CPU1 also has
an x1 PCIe Gen2 interface to the integrated Ethernet switch, one PCIe lane used to connect to
an Ethernet MAC/PHY, and an additional PCIe lane that connects to the BMC.
CPU2 has one x4 PCIe Gen3 interface to a single M.2 NVMe socket.
There is a second Ethernet MAC/PHY device that can connect to CPU1 or CPU2 via a single PCIe
lane. These connections are described in more detail below.
Table 1-3 ECC/Non-ECC DIMM Types
DIMM Type Ranks
8Gb
Chips
Qualified Module
Artesyn Part
#
RDIMM 1 Rank x8 8GB
X4B08QD8BNTDME-E-AY1 (C-temp)
X4B08QD8BNTDMW-E-AY1 (I-temp) 9706802B79
9706802B80
RDIMM 1 Rank x4 16GB
RDIMM 2 Rank x8 16GB
RDIMM 2 Rank x4 32GB