Artesyn BajaPPC-750, User Manual

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6-22 BajaPPC-750: VMEbus Interface
May 2002
6.6 VMEbus System Controller
When the BajaPPC-750 circuit board is located in slot 1 of the VME system, the
Universe acts as VMEbus system controller. In this capacity, the Universe provides
a system clock driver, an arbitration module, an IACK Daisy Chain Driver (DCD),
and a bus timer.
To determine if the BajaPPC-750 is in slot 1, the Universe samples BG3IN* imme-
diately after reset. If lines BG[3:0]* are sampled at logic low, then the the Universe
becomes the VMEbus system controller. Otherwise, the SYSCON module is dis-
abled. Software can override the automatic first slot detector by manipulating the
SYSCON bit in the Universe’s MISC_CTL register (see Register Map 6-4).
6.7 SYSFAIL Control
The Universe asserts SYSFAIL* after power-up or reset. It remains asserted until
explicitly cleared, typically after self-tests and diagnostics are completed. To de-
assert the signal, write a one to the SYSFAIL bit at 1E
16
of the VCSR_CLR register
at offset FF4
16
. Refer to the Universe specification for further information.
At power-up all boards in the system assert SYSFAIL* until their diagnostics are
complete. Once all boards are initialized, SYSFAIL* should not be asserted by any
board, except to indicate a failure. (SYSFAIL* may be polled.)
6.8 Bus Timer
The Universe has a programmable bus timer accessible through the VBTO field of
the MISC_CTL register (see Register Map 6-4). The default time-out period for the
VMEbus is 64 µs. The bus timer asserts VXBERR# when a VMEbus time-out
occurs.
6.9 Mailboxes
The Universe supports four 32-bit mailbox registers which can generate interrupts
on either the VMEbus or PCI bus. The mailbox registers are in the existing register
space beginning at hex offset 348
16
. Bits [19:16] of the Local Interrupt Enable Reg-
ister, LINT_EN, at hex offset 300
16
allow each mailbox interrupt to be enabled or
masked by writing either a 1 or 0, respectively, to the corresponding MBOX field.