Artesyn BajaPPC-750, User Manual

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6-18 BajaPPC-750: VMEbus Interface
May 2002
Although posted transactions do enhance performance, keep in mind that:
• VMEbus errors will be reported via interrupt to the PCI master, rather than a
target-abort. If the BajaPPC-750 processor is a PCI master (via the MPC106),
VMEbus errors translate to an external interrupt (vector 500
16
) instead of the
MCP/TEA.
• Posted mode has less determinism than coupled mode. For example, a VME-
bus error may not be reported as quickly in posted mode because the Uni-
verse must re-acquire the PCI channels to report the error. However, the PCI
interrupt channel does have priority over the DMA and slave channels.
6.4.1 Slave Mapping Example
The following code example maps an A32/D32 image to extended space. To com-
pute the bound address (LSIx_BD) for the PCI slave window, simply add the
memory size to the base address (LSIx_BS). The VME slave window bound address
(VSIx_BD) may be determined in the same manner. (See control registers in
Section 6.2.)
/*****************************************************************************/
void universe_init()
{
volatile UNIVERSE_PORT *universeIO = (UNIVERSE_PORT *)UNIVERSE_MPC_IO_BASE;
int noError = 0;
/*map the Universe - via PCI configuration cycle - to PCI memory space at
address UNIVERSE_PCI_MEM_BASE */
/*The CHRP_MAP definition has no bearing on the Universe chip - it simply
tells the function where configuration space resides*/
noError = pci_dev_config_write((int)IDSEL_UNIVERSE,
(int)UNIVERSE_VENDOR_ID,
(int)UNIVERSE_PCI_BS,
(int)(UNIVERSE_PCI_MEM_BASE),
CHRP_MAP);
if (noError < 0){
exit();
}
/*enable the MEM space map, clear any previously asserted status bits*/
noError = pci_dev_config_write((int)IDSEL_UNIVERSE,
(int)UNIVERSE_VENDOR_ID,
(int)UNIVERSE_PCI_CSR,
(int)(UNIV_PCI_CSR_D_PE |
UNIV_PCI_CSR_S_ERR |
UNIV_PCI_CSR_R_MA |
UNIV_PCI_CSR_R_TA |
UNIV_PCI_CSR_S_TA |
UNIV_PCI_CSR_BM |
UNIV_PCI_CSR_MS),
(int)CHRP_MAP);