Artesyn BajaPPC-750, User Manual

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Universe Configuration Registers 6-9
0002M621-15
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
D_PE S_ERR R_MA R_TA S_TA DEVSEL DP_D TFBBC Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved MF-BBC SERR_EN WAIT PERESP VGAPS MWI_EN SC BM MS IOS
Register Map 6-2. Universe PCI Configuration Space and Status, PCI_CSR
D_PE Detected parity error (write 1 to clear).
Binary 0=no parity error, 1=parity error.
S_ERR Signalled SERR# (write 1 to clear).
Binary 0=SERR# not asserted, 1=SERR# asserted.
R_MA Received master abort generated by master (write 1 to clear).
Binary 0=no, 1=yes.
R_TA Received target abort and master detected it (write 1 to clear).
Binary 0=no, 1=yes.
S_TA Signalled target abort, target terminated transaction (write 1 to clear).
Binary 0=no, 1=yes.
DEVSEL Device select timing (read only). Binary 01=medium speed device.
DP_D Data parity detected, master detected/generated data parity error.
Binary 0=no, 1=yes.
TFBBC Target fast back-to-back capable (read only). The Universe can not accept
back-to-back cycles from a different agent.
MF-BBC Master fast back-to-back enable (read only). The Universe never gener-
ates fast back-to-back transactions.
SERR_EN SERR# driver enable, in conjunction with PERESP to report address parity
errors with SERR#.
Binary 0=disable, 1=enable.
WAIT Wait cycle control (read only).
Binary 0=no address/data stepping.
PERESP Parity error response, allow assertion of PERR# to report data parity
errors.
Binary 0=disable, 1=enable.