Artesyn BajaPPC-750, User Manual

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3-4 BajaPPC-750: Central Processing Unit
May 2002
3.2.2 Machine State Register
The Machine State Register, MSR, configures the state of the PPC750 CPU. On ini-
tial power-up of the BajaPPC-750, most of the MSR bits are cleared. The MSR may
be read using the Move to Machine State Register (
mtmsr ) instruction. The
mtmsr , System Call ( sc ), and Return from Exception ( rfi ) instructions may be
used to modify the MSR. Please refer to the PPC750 RISC Microprocessor User’s
Manual for detailed bit descriptions.
I/DLOCK Instruction and data cache lock bits.
ICFI/DCFI Instruction and data cache flash invalidate bits.
SPD Speculative cache access disable.
IFEM Instruction fetch enable M bit.
SGE Store gathering enable.
DCFA Data cache flush assist.
BTIC Disable 64-entry branch instruction cache.
ABE Address broadcast enable. Allows broadcast of dcbf , dcbi , and dcbst on
the bus.
BHT Enable branch history table.
NOOPTI No-op touch instructions.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
reserved POW res. ILE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EE PR FP ME FE0 SE BE FE1 res. IP IR DR reserved RI LE
Register Map 3-3. CPU Machine State, MSR