Artesyn BajaPPC-750 User Manual Download Page 22

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Functional Description

1-3

0002M621-15

1.2 Functional Description

Figure 1-1. General System Block Diagram

W83C553

ISA Bridge

SMC

37C935

Ultra I/O

64-bit CPU Bus

PPC750

PowerPC

CPU

MPC106

PCI

Bridge

32256 MB

SDRAM

ISA Bus

Serial B

(HDR3, P2)

PCI

Expansion

Module

J1x

PCI

Expansion

Module

J2x

PMC2 I/O

(optional P0)

PMC1 I/O

(P2)

L2 Cache

1MB

Parallel

(optional P2 config.)

ROM Bus

ROM/Flash

NVRAM,

4MB Flash,

Intel

21143

Fast

Ethernet

ICS 1890

10Base-T

100Base-

Ethernet

RJ45

(P3)

AUI Ethernet

(P2)

Tundra

Universe

VME

A32

D64

32-bit Local PCI Bus

VME64 VMEbus

(P1)

VMEbus, Power

8 MB

Flash

PLD

Interrupt

Control

7-Segment

LED

Serial A

(optional P2 config.)

Serial A, RJ45

(P4)

Summary of Contents for BajaPPC-750

Page 1: ...y backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Vi...

Page 2: ...BajaPPC 750 PowerPC Based Single Board Computer User s Manual May 2002...

Page 3: ...Artesyn Communication Products 8310 Excelsior Dr Madison WI 53717 Web Site www artesyncp com Sales 800 356 9602 Technical Support 800 327 1251 BajaPPC 750 User s Manual Artesyn Part Number 0002M621 15...

Page 4: ...BajaPPC 750 PowerPC Based Single Board Computer User s Manual May 2002...

Page 5: ...Artesyn logo are registered trademarks of Artesyn Technologies and are used by Artesyn Communication Products under licence from Artesyn Technologies All other trademarks are property of their respec...

Page 6: ...ructions may cause harmful interference to radio communica tions However there is no guarantee that interference will not occur in a particular instal lation If this equipment does cause harmful inter...

Page 7: ......

Page 8: ...rial Numbers 2 12 2 2 3 Connectors 2 12 2 2 4 Reset Interrupt Switch 2 13 2 2 5 LED 2 13 2 2 6 Optional VMEbus Configurations 2 14 2 3 BajaPPC 750 Setup 2 14 2 3 1 Providing Power 2 15 2 3 2 Providing...

Page 9: ...Registers 5 3 5 3 1 PCI Command Register 5 4 5 3 2 PCI Status Register 5 5 5 4 PCI Interface 5 6 5 4 1 Device Mapping 5 6 5 4 2 Timing 5 7 5 4 3 Interrupts 5 7 5 4 4 Arbitration 5 7 5 5 PCI Bus Contr...

Page 10: ...mand Status 7 2 7 2 Ethernet Address 7 3 7 3 Default Ethernet Boot Device 7 4 7 4 21143 Errata 7 4 7 5 Ethernet Ports 7 5 7 5 1 Fast Ethernet 7 5 7 5 2 AUI Ethernet 7 5 7 6 Cabling Considerations 7 6...

Page 11: ...Power Up Reset Sequence 10 5 10 2 2 Initializing Memory 10 13 10 3 Monitor Command Reference 10 13 10 3 1 Command Syntax 10 13 10 3 2 Typographic Conventions 10 14 10 4 Boot Commands 10 14 10 4 1 boo...

Page 12: ...ion Example 10 31 10 7 7 Download Port Configuration Example 10 33 10 8 Test Commands 10 34 10 8 1 itctest 10 34 10 8 2 ethertest 10 34 10 8 3 serialtest 10 35 10 8 4 nvramtest 10 35 10 8 5 cachetest...

Page 13: ...51 10 15 3 Cache Control 10 51 10 15 4 MMU Control 10 52 10 15 5 Baud Rate 10 52 10 15 6 Exceptions 10 53 10 15 7 Serial I O 10 54 10 15 8 Initialize Board 10 55 10 15 9 Initialize FIFO 10 55 10 15 10...

Page 14: ...re 2 9 Jumper and Fuse Locations 2 11 Figure 5 1 Single Width PMC Module Configuration 5 2 Figure 5 2 Double Width PMC Module Configuration 5 2 Figure 5 3 PCI Bridge Memory Space 5 6 Figure 6 1 VMEbus...

Page 15: ...se Master Control MAST_CTL 6 10 Register Map 6 4 Universe Miscellaneous Control MISC_CTL 6 11 Register Map 6 5 Universe PCI Slave Image 0 Control LSI0_CTL 6 13 Register Map 6 6 Universe VME Slave Imag...

Page 16: ...0002M621 15 ix Register Map 9 1 Counter Timer Status CTSR 9 2 Register Map 9 2 Counter Timer Mode CTMR 9 4...

Page 17: ...ccess Time Required for the BajaPPC 750 4 5 Table 4 5 Nonvolatile Memory Map 4 8 Table 5 1 MPC106 PCI Interface Configuration Registers 5 3 Table 5 2 PCI Device Identification Mapping 5 6 Table 5 3 J1...

Page 18: ...e 8 7 Serial Port A Pin Assignments P4 RJ45 or Console Adapter 8 13 Table 8 8 Serial Port B Pin Assignments HDR3 Header or Cable Assembly 8 14 Table 8 9 EIA 232 Handshaking Configuration Jumper 8 15 T...

Page 19: ...xii BajaPPC 750 Contents...

Page 20: ...66 MHz or higher The PPC750 has 32 kilobyte data and instruction caches three instructions per clock cycle and a 32 64 bit data bus mode L2 Cache A 1 megabyte Level 2 cache is provided by two synchron...

Page 21: ...with 8 16 24 32 or 64 bit board compatibility The board supports all seven VMEbus interrupts Mailbox Interrupts Mailbox interrupts allow the BajaPPC 750 to be controlled remotely from specific VMEbus...

Page 22: ...HDR3 P2 PCI Expansion Module J1x PCI Expansion Module J2x PMC2 I O optional P0 PMC1 I O P2 L2 Cache 1MB Parallel optional P2 config ROM Bus ROM Flash NVRAM 4MB Flash 8 Intel 21143 Fast Ethernet ICS 18...

Page 23: ...e 16 MB PCI ISA I O Space 64 KB PCI I O Space 4 MB 64 bit Wide Flash 8 MB Config Address Register FF00 0000 Config Data Register PCI Interrupt Ack FEC0 0000 FEE0 0000 FEF0 0000 Flash PLD Registers RTC...

Page 24: ...ter Timer 1 Count Int Ack Reg PLD 9 2 2 9 2 4 FF98 0030 R L2 Cache PMC Bus Mode Register PLD 3 6 1 5 2 FF98 0020 R Board Configuration Register PLD 4 4 1 FF98 0010 R W Flash Bank Select Register PLD 4...

Page 25: ...mark The following table summarizes this compliance Artesyn maintains test reports that provide specific information regarding the methods and equipment used in compliance testing Unshielded external...

Page 26: ...ype Document CPU PPC750 PowerPC 750 RISC Microprocessor User s Manual IBM number GK21 0263 00 PowerPC Microprocessor Family The Programming Environments IBM number G522 0290 00 http www chips ibm com...

Page 27: ...http www tundra com unidex html VME64 Draft Specification Rev 1 10 October 4 1994 VITA Scottsdale AZ VME64 Extensions Draft Standard Draft 1 6 February 7 1997 VITA Scottsdale AZ http www vita com Time...

Page 28: ...re Unless you ground yourself properly static charges can accumulate in your body and cause ESD damage when you touch the board CAUTION Use proper static protection and handle the BajaPPC 750 board on...

Page 29: ...the BajaPPC 750 board are given in Table 2 1 2 2 1 Component Maps and Jumpers The figures on the following pages show the placement for various components on the BajaPPC 750 printed circuit board Fig...

Page 30: ...75 R176 R18 R20 R21 R843 R22 R23 R29 R295 R3 R30 R31 R32 R321 R338 R35 R388 R389 R39 R394 R395 R42 R48 R53 R54 R55 R58 R59 R6 R61 R62 R63 R64 R68 R69 R7 R71 R72 R73 R8 R85 R9 R97 RN1 RN2 RN3 RN4 S1 U1...

Page 31: ...0 R341 R342 R343 R344 R345 R346 R347 R348 R349 R350 R351 R352 R353 R354 R355 R356 R357 R358 R359 R360 R361 R362 R363 R364 R366 R367 R368 R369 R370 R371 R372 R373 R376 R377 R378 R379 R382 R385 R386 R38...

Page 32: ...4 R175 R176 R18 R20 R21 R843 R22 R23 R29 R295 R3 R30 R31 R32 R321 R338 R35 R388 R389 R39 R394 R395 R42 R48 R53 R54 R55 R58 R59 R6 R61 R62 R63 R64 R68 R69 R7 R71 R72 R73 R8 R85 R9 R97 RN1 RN2 RN3 RN4 S...

Page 33: ...2 R333 R336 R337 R339 R340 R341 R342 R343 R344 R345 R346 R347 R348 R349 R350 R351 R352 R353 R354 R355 R356 R357 R358 R359 R360 R361 R362 R363 R364 R366 R367 R368 R369 R370 R371 R372 R373 R376 R377 R37...

Page 34: ...R132 R133 R134 R135 R136 R137 R138 R139 R14 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R15 R150 R151 R152 R153 R154 R155 R156 R157 R158 R159 R16 R160 R161 R162 R163 R164 R165 R166 R167 R168 R1...

Page 35: ...43 R244 R245 R246 R247 R248 R249 R250 R251 R252 R253 R254 R255 R256 R257 R259 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R280 R281 R282 R283 R284 R2...

Page 36: ...P1 VMEbus P0 VMEbus CR1 7 Seg LED P4 EIA 232 RJ45 P3 Ethernet RJ45 U11 PowerPC CPU U23 L2 Cache U24 L2 Cache U22 Universe VME U13 MPC106 PCI U4 21143 Ethernet U17 W83C553 ISA Bridge U20 37C935 Ultra...

Page 37: ...2 10 BajaPPC 750 Setup May 2002 Figure 2 8 Component Map Bottom Board Rev 1 HDR4 Debug U95 4 Meg Flash U90 2 Meg Flash U89 2 Meg Flash U88 2 Meg Flash U87 2 Meg Flash...

Page 38: ...MORY TYPE IN PLCC SOCKET Jumper in Flash default when shipped with Flash in socket Jumper out EPROM default when shipped with EPROM in socket JP3 EIA 232 HANDSHAKING SELECT 1 2 False 12V 2 3 True 12V...

Page 39: ...nfiguration description Be sure to include all the information that appears on the sticker Any custom or user ROM installed including version and serial number ________________________________________...

Page 40: ...two position toggle switch can reset the BajaPPC 750 or provide a level 6 interrupt to the CPU It is located between serial port connector P4 and the LED on the front panel The interrupt position on...

Page 41: ...indicates the standard configuration while a one indicates the optional configuration 2 3 BajaPPC 750 Setup You need the following items to set up and check the operation of the Artesyn BajaPPC 750 Ar...

Page 42: ...2 Providing Air Flow As with any printed circuit board be sure that there is sufficient air flow to the board to prevent overheating The environmental requirements are specified as Operating temp 0 to...

Page 43: ...he transition module console port Set the terminal as follows 9600 baud full duplex Eight data bits no parity Two stop bits for transmit data One stop bit for receive data If your terminal does not ha...

Page 44: ...cillo scope to look for excessive power supply ripple or noise over 50 mVpp below 10 MHz Note that the use of P2 is required to meet the power specifications Check your terminal switches and cables Be...

Page 45: ...ou plan to return the board to Artesyn Communication Products for service call 1 800 327 1251 and ask for our Test Services Department or send e mail to serviceinfo artesyncp com to obtain a Return Me...

Page 46: ...atures for the PowerPC family of microprocessors include Superscalar microprocessor Independent execution units and multiple register files Independent 8 way set associative instruction and data cache...

Page 47: ...egister Map 3 1 at FF98 002016 indicates whether or not the reset was due to a power up condition 0 power up 1 reset After power up a write to the Clear NMI Register at FF9E 000016 sets this bit which...

Page 48: ...LOCK ICFI DCFI SPD IFEM SGE DCFA BTIC res ABE BHT res NOOP TI Register Map 3 2 PPC750 Hardware Implementation Dependent HID0 EMCP Enable machine check pin Initially enabled on the BajaPPC 750 DBP Enab...

Page 49: ...al for detailed bit descriptions I DLOCK Instruction and data cache lock bits ICFI DCFI Instruction and data cache flash invalidate bits SPD Speculative cache access disable IFEM Instruction fetch ena...

Page 50: ...ME Machine check enable Machine checking is enabled initially on the BajaPPC 750 FE0 FE1 These bits define the floating point exception mode Table 3 3 IEEE Floating Point Exception Modes FE0 FE1 FP Ex...

Page 51: ...auses Alignment 00600 Any alignment exception condition DSI 00300 Due to eciwx ecowx Program 00700 Due to a floating point enabled exception Floating point unavailable 00800 Any floating point unavail...

Page 52: ...ers are connected to the most significant long word on the CPU bus Table 3 5 Interrupt Vector Assignments Interrupt Source Mnemonic Priority Hex Vector Counter Timer 2 CT2 Highest 0000 00B8 Counter Ti...

Page 53: ...ffers TLBs The CPU supports the modified exclusive invalid MEI cache coherency protocol Each cache has 128 entries and supports demand paged virtual memory address translation and variable sized block...

Page 54: ...F98 003016 to determine the L2 config uration settings see Register Map 3 6 There are various configuration resistors that set the bit values for this register 0 installed 1 not installed Please refer...

Page 55: ...keying pin 15 CKSTP_OUT 16 GND CKSTP_OUT Checkstop Output When asserted this output signal indicates that the CPU has detected a checkstop condition and has ceased operation This signal also drives th...

Page 56: ...anual for details TA Transfer Acknowledge This signal acknowledges the successful comple tion of a data transfer TS Transfer Start This signal indicates that a bus transaction is starting TEA Transfer...

Page 57: ...3 12 BajaPPC 750 Central Processing Unit May 2002...

Page 58: ...roller for the BajaPPC 750 Table 4 1 lists the control registers associated with the memory interface Chapter 5 describes the PCI bridge Please refer to the MPC106 PCI Bridge Memory Controller User s...

Page 59: ...for that task Otherwise you risk damaging the PLCC device Jumpers on the BajaPPC 750 circuit board configure the memory as shown in Table 4 2 The on board monitor HKMON is standard in the first 512K...

Page 60: ...synchronous DRAM SDRAM The memory chips are 4Mx16 or 8Mx16 3 3 V SDRAM devices arranged in up to eight banks of four devices Currently no configurations utilize more than four banks Revision 22 and hi...

Page 61: ...M timing for any reason able combination of board speed and SDRAM speed can be programmed On the BajaPPC 750 the timing values programmed into the Memory Control Configu 7 6 5 4 3 2 1 0 pwr_up P2_cfg...

Page 62: ...refresh must be performed and the SDRAM controller is unable to perform the refresh during non RAM cycles This happens so infrequently that any performance degradation is usually unnoticeable When the...

Page 63: ...the quartz crystal and lithium cell to be mounted in a socket on top of the SRAM array and supporting circuitry The M48T35 is pin and function compatible with standard JEDEC 32K x 8 SRAMs The real tim...

Page 64: ...refer to M48T35 data sheet for calibration methods ST Stop Bit Writing a one to this bit turns off the oscillator If the M48T35 will be stored for a significant amount of time stopping the oscillator...

Page 65: ...various operating systems to store their boot parameters without affecting each other Please refer to NVRAM Commands Section 10 7 for details on programming the nonvolatile memory Table 4 5 Nonvolatil...

Page 66: ...TE The BajaPPC 750 circuit board selects 3 3 volt module power from either the VMEbus backplane or the onboard regulator depending upon which fuse is installed F4 selects the back plane F3 selects the...

Page 67: ...a double width module may be installed over both sites Each site includes a cutout in the front panel for I O The possible PMC module configurations are shown in Fig 5 1 and Fig 5 2 Figure 5 1 Single...

Page 68: ...le power is applied To check if a PMC module is installed read the L2 Cache PMC Bus Mode Register Register Map 3 6 at FF98 003016 A value of one in Bit 0 indicates that PMC site J1x is occupied and a...

Page 69: ...R Header type 00 0F 1 R BIST Control Built in self test 00 3C 1 R Interrupt Line 00 3D 1 R Interrupt Pin 00 3E 1 R MIN_GNT Burst period length 00 3F 1 R MAX_GNT PCI bus access rate 00 40 1 R MPC106 Bu...

Page 70: ...PCI Status DPE Detected parity error 1 parity error SSE Signalled system error 1 SERR asserted RMA Received master abort 1 transaction terminated by master abort CAUTION You might need to clear the RM...

Page 71: ...ed locally In addition to the MPC106 there are two PMC expansion slots and three PCI devices on the local PCI bus Each PCI device requires its own IDSEL address line as indicated in the table below Ta...

Page 72: ...uisition latency Initialization and time out values should be set up to accom modate any additional latency 5 4 3 Interrupts Each module has four interrupt lines which are routed through the interrupt...

Page 73: ...ta width Since the BajaPPC 750 is a 32 bit board these signals are tied off to indicate the 32 bit data width AD00 AD31 ADDRESS and DATA bus bits 0 31 These three state lines are used for both address...

Page 74: ...tions to complete PAR PARITY This is even parity across AD00 AD31 and C BE0 C BE3 Parity generation is required by all PCI agents This three state signal is stable and valid one clock after the addres...

Page 75: ...4 Ground BUSMODE3 P2 A7 46 AD15 AD13 P2 A23 15 Ground 3 3V P2 C8 47 AD12 Ground P2 C24 16 GNT BUSMODE4 P2 A8 48 AD11 AD10 P2 A24 17 REQ No Connection P2 C9 49 AD9 AD8 P2 C25 18 5V Ground P2 A9 50 5V 3...

Page 76: ...47 AD12 Ground P0 D16 16 GNT BUSMODE4 P0 E7 48 AD11 AD10 P0 C16 17 REQ No Connection P0 D7 49 AD9 AD8 P0 B16 18 5V Ground P0 C7 50 5V 3 3V P0 A16 19 5V AD30 P0 B7 51 Ground AD7 P0 E17 20 AD31 AD29 P0...

Page 77: ...5 12 BajaPPC 750 PMC PCI Interface May 2002...

Page 78: ...can access short standard and extended space addresses As a VMEbus slave the BajaPPC 750 can respond to the full 32 bit range of addresses on the VMEbus The default master and slave images are program...

Page 79: ...ase refer to the Universe User Manual for detailed descriptions of the control bits Slave Enables Slave enables are provided for each VMEbus space to which the BajaPPC 750 responds extended standard a...

Page 80: ...ation Offset 14C 16C Universe Reserved 170 SCYC_CTL Special Cycle Control Register 174 SCYC_ADDR Special Cycle PCI bus Address Register 178 SCYC_EN Special Cycle Swap Compare Enable Register 17C SCYC_...

Page 81: ...ster 214 Universe Reserved 218 DCPP DMA Command Packet Pointer 21C Universe Reserved 220 DGCS DMA General Control and Status Register 224 D_LLUE DMA Linked List Update Enable Register 228 2FC Universe...

Page 82: ...e 1 Base Address Register F1C VSI1_BD VMEbus Slave Image 1 Bound Address Register F20 VSI1_TO VMEbus Slave Image 1 Translation Offset F24 Universe Reserved F28 VSI2_CTL VMEbus Slave Image 2 Control F2...

Page 83: ...ister FB0 VSI5_TO VMEbus Slave Image 5 Translation Offset FB4 Universe Reserved FB8 VSI6_CTL VMEbus Slave Image 6 Control FBC VSI6_BS VMEbus Slave Image 6 Base Address Register FC0 VSI6_BD VMEbus Slav...

Page 84: ...ies posted write transfer count request level and mode release mode and burst size VMEbus timeout and other misc params MISC_CTL 3000 0000 Set VMEbus timeout to 64 s Timer values LMISC Do not alter Ad...

Page 85: ...ignments The SPACE bit assignment for this register is the logical inversion of the SPACE bit for PCI_BS 6 2 3 PCI Configuration Space and Status Register The Universe PCI Configuration Space Control...

Page 86: ...t write 1 to clear Binary 0 no 1 yes S_TA Signalled target abort target terminated transaction write 1 to clear Binary 0 no 1 yes DEVSEL Device select timing read only Binary 01 medium speed device DP...

Page 87: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MAXRTRY PWON VRL VRM VREL VOWN VOWN_ACK Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PABS Reserved BUS_NO Register Map 6 3 Universe Master Con...

Page 88: ...OWN Read only PABS PCI aligned burst size This determines the PCI address boundary where the Universe breaks up a PCI transaction Binary 00 32 bytes 01 64 bytes 10 128 bytes all others reserved BUS_NO...

Page 89: ...emory controller currently issues a retry upon detecting a memory select error the maximum slave window size should be limited to the size of the desired memory mapped region The slave window can make...

Page 90: ...SUPER Reserved VCT Reserved LAS Register Map 6 5 Universe PCI Slave Image 0 Control LSI0_CTL EN Enable the image power up option disable when configuring Binary 0 disabled 1 enabled PWEN Posted write...

Page 91: ...or the maximum slave window size should be limited to the size of the desired memory mapped region The slave window can make any portion of the BajaPPC 750 memory map available on the VMEbus The VMEbu...

Page 92: ...e Universe s MAST_CLT register sets VMEbus ownership see Register Map 6 3 The CWT bits in the Universe s LMISC register at hex offset 18416 affect the performance of the PCI bus and indirectly the VME...

Page 93: ...lave images have a resolution of 64 kilobytes NOTE The address space of a VMEbus slave image must not overlap the Uni verse control and status registers Also slave image spaces must not overlap each o...

Page 94: ...ines the length of BLT MBLT cycles The Universe will attempt block DMA transfers of up to 256 bytes for BLT and 2 kilo bytes for MBLT as limited by the VMEbus specification and VON counter CAUTION Do...

Page 95: ...D for the PCI slave window simply add the memory size to the base address LSIx_BS The VME slave window bound address VSIx_BD may be determined in the same manner See control registers in Section 6 2 v...

Page 96: ...S int UNIV_LSIX_CTL_EN LSI0_BS contains the base address of our window as seen by the processor universeIO LSI0_BS ES int CHRP_PCI_MEM_SPACE_START LSI0_BD contains the end of our window as seen by the...

Page 97: ...ters The Universe also allows for each of the seven interrupt request levels to be gen erated simply by writing to the appropriate field in the VME Interrupt Enable Register VINT_EN at hex offset 3101...

Page 98: ...knowledge IACK cycle and output Upon completion of the cycle it releases the VMEbus allowing the PCI resource to read the interrupt vector and service the output Software interrupts are release on ack...

Page 99: ...cs are completed To de assert the signal write a one to the SYSFAIL bit at 1E16 of the VCSR_CLR register at offset FF416 Refer to the Universe specification for further information At power up all boa...

Page 100: ...o determine if a specific mailbox interrupt is active 1 active 0 inactive Writing a one clears the status bit Two access registers VRAI_BS at offset F7416 and VRAI_CTL at offset F8016 make the mailbox...

Page 101: ...location monitor generates one of four internal interrupts on the PCI bus The interrupt level may be read on the VMEbus as follows 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EN Reserved PGM SUPER...

Page 102: ...rite a one to the status bit and a unique pattern to the tag field of a specific semaphore During subsequent byte wide reads by the process it will be granted ownership of the resource if the pattern...

Page 103: ...aisy chains An input to the BajaPPC 750 the bus grant in signal indicates that it may use the bus if it wants BG0OUT BG3OUT BUS GRANT 0 3 OUT Totem pole signals generated by requesters An output from...

Page 104: ...and A01 to select which byte location s within the 4 byte group are accessed during the data transfer It is also used for D64 transfers RETRY RETRY A line driven by a Slave to indicate to the Master...

Page 105: ...ors The tables on the following pages show the pin assignments NOTE The P0 connector is optional and requires a mating J0 connector on the backplane PMC connector J14 connects directly to P2 PMC con n...

Page 106: ...J24 22 PMC J24 23 PMC J24 24 PMC J24 25 9 GND Reserved Reserved Reserved Reserved Reserved 10 GND Reserved Reserved Reserved Reserved No Connection 11 GND No Connection No Connection No Connection No...

Page 107: ...n GND BR3 A23 GA3 16 GND DTACK AM0 A22 3 3V to PMC 17 No Connection GND AM1 A21 GA4 18 GND AS AM2 A20 3 3V to PMC 19 No Connection GND AM3 A19 No Connection 20 GND IACK GND A18 3 3V to PMC 21 No Conne...

Page 108: ...G2OUT GND 10 SYSCLK BG3IN SYSFAIL 11 GND BG3OUT BERR 12 DS1 BR0 SYSRESET 13 DS0 BR1 LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTACK AM0 A22 17 GND AM1 A21 18 AS AM2 A20 19 GND AM3 A19 20 IACK GND A18 2...

Page 109: ...tion 14 GND PMC J14 28 D16 PMC J14 27 No Connection 15 No Connection PMC J14 30 D17 PMC J14 29 No Connection 16 GND PMC J14 32 D18 PMC J14 31 No Connection 17 ETH_DI PMC J14 34 D19 PMC J14 33 No Conne...

Page 110: ...11 PMC J14 22 A31 P_D2 12 PMC J14 24 GND P_D3 13 PMC J14 26 5V P_D4 14 PMC J14 28 D16 P_D5 15 PMC J14 30 D17 P_D6 16 PMC J14 32 D18 P_D7 17 PMC J14 34 D19 P_ACK 18 PMC J14 36 D20 P_BSY 19 PMC J14 38 D...

Page 111: ...6 34 BajaPPC 750 VMEbus Interface May 2002...

Page 112: ...ems It includes a number of features which enhance its performance and versatility Large independent receive and transmit FIFOs Support for either media independent interface MII for Fast Ethernet or...

Page 113: ...ts should be written with zero to preserve compatibility with future releases Reading the reserved bits will produce unpredictable results Table 7 1 21143 Configuration Register Summary Hex Offset Mne...

Page 114: ...a BajaPPC 750 is 2867 the calculated value is 1867 74B16 Therefore the board s Ethernet address is 00 80 F9 51 07 4B The com plete Ethernet address is stored at byte offset 2016 in serial ROM Table 7...

Page 115: ...ing data line low Bit 2 corresponds to the status of JP1 pins 1 2 bit 1 corresponds to pins 3 4 and bit 0 corresponds to pins 5 6 The remaining DATA bits are pulled high reserved 7 4 21143 Errata The...

Page 116: ...P3 are given below Figure 7 1 Fast Ethernet Connector P3 RJ45 7 5 2 AUI Ethernet The BajaPPC 750 provides for an additional Ethernet interface at VMEbus con nector P2 see Tables 6 9 and 6 10 for pinou...

Page 117: ...ns The BajaPPC 750 Ethernet interface complies with the IEEE P802 3u D3 and ANSI TP PMD v2 0 UTP CAT 5 standards for Fast Ethernet Since the 21143 LAN con troller can operate at up to 100 Mb s UTP CAT...

Page 118: ...ISA Bridge The PCI to ISA bus interface for the BajaPPC 750 is provided by a Winbond Sys tems Laboratory W83C553 integrated circuit The W83C553 ISA bridge features Compliance with revision 2 1 PCI spe...

Page 119: ...sters The following table briefly summarizes the ISA bridge registers Please refer to the Winbond Systems W83C553F System I O Controller with PCI Arbiter Data Book for the bit assignments and other im...

Page 120: ...Pointer2 0D DA W Master Clear2 0E DC W Clear Mask2 0F DE W Write All Mask2 87 83 81 n a 82 8B 89 8A R W Memory Page3 00 40B DMAC1 4D6 DMAC2 W Extended Mode Register 0x 40A R Scatter Gather Interrupt S...

Page 121: ...ord 1 4D0 PIC1 4D1 PIC2 R W Interrupt Edge Level Control 00 Counter Timer I O Registers 40 41 42 R W Counter4 40 41 42 R Counter Status4 43 W Timer Control 7B 78 BIOS Timer 000000 Miscellaneous I O Co...

Page 122: ...ame location Table 8 4 summarizes the Ultra I O configuration registers For a complete description of all the control bits please refer to the SMC Ultra FDC37C93x user s documentation Table 8 3 Ultra...

Page 123: ...63 R W 00 00 00 00 Second Base I O Address 70 R W 00 00 Primary Interrupt Select F0 R W 00 n a IDE2 Mode Register Logical Device 3 Configuration Registers Parallel Port 30 R W 00 00 Activate 60 61 R...

Page 124: ...Device 7 Configuration Registers Keyboard 30 R W 00 00 Activate 70 R W 00 00 Primary Interrupt Select 72 R W 00 00 Second Interrupt Select Logical Device 8 Configuration Registers AUX I O 30 R W 00 00...

Page 125: ...Interrupt Enable Register IER enables specific interrupt sources for the serial ports It is possible to disable all of the Ultra I O serial port interrupts using this register Table 8 5 Addresses for...

Page 126: ...ster Map 8 2 Ultra I O Serial Port Interrupt Identification IIR PEND Interrupt pending 1 none pending 0 pending INT_ID 1 3 Interrupt priority identification Bit 3 is always zero in non FIFO mode 1 1 0...

Page 127: ...tch 0 1 2 3 4 5 6 7 DTR RTS OUT1 OUT2 LOOP 0 0 0 Register Map 8 4 Ultra I O Serial Port Modem Control MCR DTR Data terminal ready 0 nDTR output forced to logic 1 1 nDTR out put forced to logic 0 RTS R...

Page 128: ...not ready 1 serial port ready for transmission TEMT Transmitter empty 0 THR or TSR contains a data character 1 THR and TSR are empty FIFO_ER FIFO error This bit is always zero except in FIFO mode wher...

Page 129: ...of the divisor deter mines the clock as follows 0 clock divided by 3 1 inverse of input oscillator 2 clock divided by 2 50 duty cycle 3 or greater low for 2 bits high for count remainder Table 8 6 Ba...

Page 130: ...bus P2 connector optional configuration Table 8 7 lists the pinouts for the front panel connector A console adapter Fig 8 2 also is available for this connector providing connectivity with a standard...

Page 131: ...omplete description of the serial port signals and associated control registers Table 8 8 Serial Port B Pin Assignments HDR3 Header or Cable Assembly HDR3 Pin Header DB25 Pin Cable Signal HDR3 Pin Hea...

Page 132: ...inout configuration on P2 The following sections briefly describe eight addressable registers that determine the parallel port functions Please refer to the Ultra I O Controller User s Manual for comp...

Page 133: ...ata Register The Status Register latches during the read cycle and contains the following infor mation Table 8 10 Addresses for Ultra I O Parallel Port Registers Register Hex Address Register Hex Addr...

Page 134: ...t error 1 time out error detected 7 6 5 4 3 2 1 0 0 0 PCD IRQE SLCTIN nINIT AUTOFD STROBE Register Map 8 9 Ultra I O Parallel Port Control PCD Parallel Control Direction Only valid in EPP or ECP mode...

Page 135: ...8 18 BajaPPC 750 Serial and Parallel I O May 2002...

Page 136: ...by the interrupt controller which drives the interrupt input to the CPU For details see Section 3 4 on interrupt handling 9 2 Counter Timer Registers Each timer is programmed through three read regist...

Page 137: ...alized to generate 10 00002 millisec ond interrupts 9 2 2 Count Register The Count Register CTCR returns the current contents of the counter When the counter is activated it is loaded with the content...

Page 138: ...to the register that clears the status bits without affecting the timer CInPrg The count in progress bit indicates that the timer has not reached a ter minal count of zero In timer mode this bit is s...

Page 139: ...imer is configured to stop on overflow and overflow has occurred IntrEn When the interrupt enable bit is set it allows the interrupt pending sta tus to generate interrupt requests OvFlEn When the over...

Page 140: ...is play 10 1 1 Start Up Display At power up or after a reset the monitor runs diagnostics and reports the results in the start up display NOTE The results of the power up diagnostic tests are displaye...

Page 141: ...and line and modify commands Each new line is brought up in insert text mode Baja750 Monitor Ver 1 0 Enabling the L1 instruction cache Print Hex Test should 89abcdef 0x89abcdef Memory Size is 0x080000...

Page 142: ...nd start the editor press ESC You can use most common vi commands such as x i a A w cw dw r and e cr To execute the current command and exit the editor press Enter or Return DEL To discard an entire l...

Page 143: ...this case The following commands are available in the debugger Display a list of available commands r b l address Read a byte b or 32 bit long word l from an address w b l address data Write a byte b...

Page 144: ...tics autoboot procedures free memory initialization and if necessary invokes the command line editor Power up sequence If an unexpected interrupt occurs before the console port is ready the LED flashe...

Page 145: ...rite an 8 to the LED display Write and read locations 0x40000 and 0x4000004 with the data pattern 0x05050a0a and its complement DRAM data test flag Table 10 1 reports failures If a failure occurs the...

Page 146: ...ity in the NVRAM parameters 18 Initialize at system level to set up for running compiled C code Enable machine checks in the MPC106 and initialize BSS Relocate the dynamic data section from ROM to its...

Page 147: ...ler and serial port tests Display errors on the console The NVRAM flag Table 10 1 reports any failures 25 Branch execution to StartMonitor which checks the boot device If a boot device BootDev is spec...

Page 148: ...ay 1 4 Second Turn LED Display Off 1 4 Second LED 1 Decrementer Test Error Display Error on LED Yes Enable Instruction Cache No No LED 2 PCI Test Error Display Error on LED LED 3 Initialize UltraIO LE...

Page 149: ...play Error Set Error Flag Disable Parity Error Reporting Continue Test Error Error Type Data Parity Display Error Set Error Flag Disable Parity Error Reporting Continue Test Initialize Stack Start C C...

Page 150: ...d Editor No Yes Yes Disable Instruction Cache No Leave Instruction Cache Enabled Yes Enable Data Cache Leave Data Cache Disabled No Continue ConfigBoard ConfigSerDevs config_mmu Is SkipConfigBoard Set...

Page 151: ...MemBase Key Pressed Start Countdown Copy RomSize bytes from RomBase to LoadAddress Execute at LoadAddress Read long word value at RomBase Is long word a branch instruction No Code in EPROM Start comma...

Page 152: ...al commands which fall into the following categories boot memory flash NVRAM test remote host arithmetic and other commands NOTE The BajaPPC 750 monitor performs argument checking for com mands but no...

Page 153: ...nd command defined in the monitor Each command must begin with a symbol Commands are type checked and argument validated but functions are not checked in any way Commands that are not symbolic are ass...

Page 154: ...CallAddress and then writes 0x596f4f6b character string YoOk to MagicLoc to show that the application is ready for the target 3 Target writes value 0x42796521 character string Bye to MagicLoc to show...

Page 155: ...ed two parameters are passed to the application from the nonvolatile memory group BootParams The parameters are seen by the application as shown below Application unsigned char Device unsigned char Nu...

Page 156: ...wnloaded application from the LoadAddress and DevType fields in the nonvolatile memory group BootParams The DevType field selects one of the download formats specified below The nonvolatile configurat...

Page 157: ...dress source and computes the checksum for that region of memory The checksum is the 16 bit sum of the bytes in the memory block DEFINITION int CheckSumMem unsigned char Addr unsigned long ByteCount 1...

Page 158: ...he data is displayed as hex character values on the left and printable ASCII equivalents on the right Nonprintable ASCII characters are printed as a dot Press any key to interrupt the display If the p...

Page 159: ...ss endaddr for memory locations that are different from the data specified by searchval DEFINITION int FindNotMem char Flag unsigned long SearchVal unsigned long StartAddr unsigned long EndAddr 10 5 9...

Page 160: ...wapmem swapmem source destination bytecount swaps bytecount bytes at the source address with those at the destination address DEFINITION int SwapMem char Src char Dest int ByteCount 10 5 13 testmem te...

Page 161: ...ber of passes and failures The memory test can be interrupted at the start of the next pass by pressing any character Also refer to the functions MemBase and MemTop in Section 10 15 15 DEFINITION int...

Page 162: ...Bank 0 and addressed at FF80 000016 The commands described in sections 10 6 5 through 10 6 7 only affect the 32 megabyte flash devices 10 6 1 flashblkwr flashblkwr source destination bytecount writes...

Page 163: ...iple of 8 bytes wideflashblkwr calls wideflasheraseblk to erase the block s it will write to In the event of a write or erase error it calls wideflashclrstat DEFINITION unsigned long WideFlashBlkWr un...

Page 164: ...this manual Portions of this nonvolatile memory are reserved for factory configuration and identification information and the moni tor The nonvolatile memory support commands deal only with the monito...

Page 165: ...stop bits for transfer 1 Bit 1 Bit 2 Bits ChBaudOnBreak Break character causes baud rate change False True False RstOnBreak Break character causes reset False True False Download Port Select communic...

Page 166: ...inates its bus tenure OnRequest WhenDone OnRequest Never VmeBusTimer Internal timer DTACK must be received before this timer expires 64 s 4 s 16 s 32 s 64 s 128 s 256 s 512 s Off ArbiterMode Select th...

Page 167: ...shortest 0 to long est 7 duration for auto boot countdown 1 0 1 2 3 4 5 6 7 DoPCIConfig Configure module True True False Network future use only BoardIPAddr IP address of board 0 0 0 0 x x x x where 0...

Page 168: ...st fields legal options are displayed in parentheses 6 Press ESC or Q to quit the display 7 Type nvupdate to save the new value or nvopen to cancel the change by reading the old value DevNumber Define...

Page 169: ...onvolatile memory DEFINITION void NVInit int SerNum char RevLev int ECOLev int Writes 10 7 3 nvopen nvopen reads and checks the monitor and Artesyn defined sections If the non volatile sections are no...

Page 170: ...ootDev When the BajaPPC 750 is reset or powered up the monitor checks this field and attempts to boot from the specified device Currently the monitor supports Serial ROM Bus EPROM Flash and Stos as st...

Page 171: ...is displayed 5 Type the new value ROM 6 Press cr to display the LoadAddress field 7 Type the address where execution begins 8 Press cr to display the ROMBase field 9 Type the ROM base address 10 Press...

Page 172: ...o save the new values 10 7 7 Download Port Configuration Example In this example the NVRAM command nvdisplay changes fields in the Down load group which contains fields for port selection baud rate pa...

Page 173: ...ccuracy of each of the two counter timers in both modes In timer mode it sets the timer for 100 milliseconds and verifies that a single interrupt occurs 100 milliseconds later In counter mode the test...

Page 174: ...ies that data can be transmitted and received by the console and download ports This test operates in internal loopback mode and simulta neously tests serial interrupts DEFINITION void serialtest void...

Page 175: ...them easily distinguishable by humans All records contain fields for the length of the record the data in the record and some kind of checksum Some records also contain an address field Most soft ware...

Page 176: ...d format consists of two parts Magic number which is 0x12345670 number of sections Information for each section including the load address unsigned long the section size unsigned long a checksum unsig...

Page 177: ...ksum The extended address record is the upper sixteen bits of the 20 bit address The segment value is assumed to be zero unless one of these records sets it to some thing else When such a record is en...

Page 178: ...rt address segment oooo is the start address offset cs is the checksum EXAMPLE 040000035162000541 In this example the start address segment is 516216 and the start address offset is 000516 so the abso...

Page 179: ...ss is 1216 04003000902BB4FD60 loads byte 9016 to address 4016 loads byte 2B16 to address 4116 loads byte B416 to address 4216 loads byte FD16 to address 4316 00000001FF terminates the file 10 9 5 Moto...

Page 180: ...bit addresses S2 records have 24 bit addresses and S3 records have 32 bit addresses EXAMPLES S10801A00030FFDC95B6 In this example the bytes 0016 3016 FF16 DC16 and 9516 are loaded into memory startin...

Page 181: ...ncluded in the data for this record is the initial start address for the downloaded code EXAMPLES S903003CC0 In this example the start address is 3C16 S8048000007B In this example the start address is...

Page 182: ...ault numeric base is decimal Specify hexadecimal by typing 16 at the end of the value octal by typing 8 or binary by typing 2 The result of the operation is displayed in hex decimal octal and binary D...

Page 183: ...s an unsigned long DEFINITION unsigned long Rand void 10 10 5 sub sub number1 number2 subtracts two integers in hexadecimal binary octal or dec imal default number2 is subtracted from number1 The defa...

Page 184: ...e the PCIshow com mand to display the PCI devices and their base addresses on the screen DEFINITION void config_PCI void 10 11 3 ethernetaddr ethernetaddr returns the Ethernet address of the board in...

Page 185: ...s not available Check the spelling If the topic was a command name use the help command to check the spelling of the command You must use the full command name not an abbreviation Power up Test FAILED...

Page 186: ...s This section describes functions which are specific to the BajaPPC monitor imple mentation 10 14 1 Grackle Read Write SYNOPSIS unsigned char ReadGrackleCfgb unsigned char Offset void WriteGrackleCfg...

Page 187: ...TBL void unsigned long getDEC void void setDEC unsigned long 32 bit unsigned long getSRR0 void unsigned long getPVR void unsigned long get_dbatu_entry int batnum unsigned long get_dbatl_entry int batn...

Page 188: ...ned NOTE The MPC106 supports 8 16 and 32 bit reads in the ROM so readw_bus8 is not necessary However it is included for compatibil ity with other Artesyn products 10 14 5 Display Processor Temperature...

Page 189: ...bit values The atoh function converts an ASCII string to a hex number The atod func tion converts an ASCII string to a decimal number The atoo function con verts an ASCII string to an octal number Th...

Page 190: ...ppropriate bootstrap program The monitor supports the ROM BUS and SERIAL autoboot devices which are not hardware specific The remainder of the devices may or may not be supported by board specific fun...

Page 191: ...oid DESCRIPTION The MMU functions enable or disable instruction and data address transla tion in the MSR register 10 15 5 Baud Rate SYNOPSIS void baud_c unsigned long baud void baud_d unsigned long ba...

Page 192: ...he default unexpected interrupt handler and an optional fixed parameter for the handler This ensures that the board will not hang upon receiving unexpected interrupts The unexpected interrupt han dler...

Page 193: ...and the argument Data is a pointer to the read or write data 10 15 7 Serial I O SYNOPSIS unsigned char get_c void unsigned char get_d void void put_c unsigned char c void put_d unsigned char c int key...

Page 194: ...mmand exe cutes all of these functions The config_MMU function sets the block address translation registers of the processor ConfigSerDevs sets the console and download serial ports as spec ified by t...

Page 195: ...ailable it is written to the address specified by the pointer Ptr and the func tion returns TRUE If no character is available the function returns FALSE 10 15 10 Initialize Ethernet Address SYNOPSIS v...

Page 196: ...r to return to the line editor 10 15 13 Legal Value Check SYNOPSIS void IsLegal unsigned char Type char Str DESCRIPTION This function is used to determine if the specified character string Str contain...

Page 197: ...memory requested if the request can be satisfied and NULL if there is not enough memory to sat isfy the request The function Malloc accepts one argument NumBytes indi cating the number of bytes reque...

Page 198: ...memory usage This function outputs a table showing how much memory is available and how much is used and lost as a result of overhead SEE ALSO MemTop MemBase 10 15 15 Miscellaneous SYNOPSIS unsigned...

Page 199: ...7 Support Functions SYNOPSIS void SetNvDefaults NVGroupPtr Groups int NumGroups void DispGroup NVGroupPtr Group unsigned long EditFlag int NVOp unsigned long NVOpCmd unsigned char Base unsigned long S...

Page 200: ...res and recovers data structures from nonvolatile memory The only requirement of the data structure to be stored in nonvola tile memory is that the first field of the structure be NVInternal which is...

Page 201: ...nonvolatile memory device If errors are encountered during the check save or compare operations an error message is returned from the function NVOp The error codes are listed below SEE ALSO NVFields h...

Page 202: ...the function The function putchar writes the character c from the console device If the serial port does not accept the character the function eventually times out The function KBHit polls the consol...

Page 203: ...inted to by Str1 and Str2 If they are equal it returns TRUE otherwise it returns FALSE Note that this version does not act the same as the UNIX strcmp function CmpStr is not case sensitive and only ma...

Page 204: ...eAddr unsigned long TopAddr void Interact int Mod unsigned char StartAddr unsigned char EndAddr DESCRIPTION The function TestSuite and the memory tests which make up this function verify a memory inte...

Page 205: ...on is to cause the address buffers and multiplexors to change dramati cally The function Interact is used to test byte interaction in the memory region specified by StartAddr and EndAddr The main goal...

Page 206: ...at is a string that contains plain characters to be pro cessed as is and special characters that are used to indicate the format of the next argument in the argument list There must be at least as man...

Page 207: ...10 68 BajaPPC 750 Monitor May 2002...

Page 208: ...rial port 10 17 over a bus interface 10 14 burst cycles 4 5 bus interface VME 6 1 BUSMODE1 4 5 8 byte terminology 1 7 C cache CPU memory 3 8 level 2 3 9 certifications 1 6 character arguments for moni...

Page 209: ...ecord in monitor 10 38 VME 6 25 F Fast Ethernet address 7 3 10 45 AUI 7 5 cabling considerations 7 6 features 7 1 port 7 5 features BajaPPCM 1 1 CPU 3 1 Ethernet 7 1 ISA bridge 8 1 PMC 5 1 flags for m...

Page 210: ...e 10 23 flash clear status 10 23 flash erase block 10 24 get configuration 10 45 initializing from the monitor 10 13 management 10 58 map BajaPPCM 1 4 map NVRAM 4 8 modify 10 21 monitor commands 10 18...

Page 211: ...atoh 10 50 atoo 10 50 atoX 10 50 baud_c 10 52 baud_d 10 52 BitToHex 10 50 BootUp 10 51 ByteAddrTest 10 65 Calloc 10 58 CFree 10 58 ChBaud 10 63 clrHID0 10 48 clrMSR 10 48 CmpStr 10 64 config_MMU 10 5...

Page 212: ...xsprintf 10 66 monitor group BootParams 10 28 10 31 Cache 10 28 Console 10 26 Download 10 26 HardwareConfig 10 29 MailBox 10 27 Manufacturing 10 29 Misc 10 28 10 34 Network 10 28 Service 10 29 VMEbus...

Page 213: ...rning the board to Artesyn 2 18 S screen messages 10 46 SDRAM See DRAM semaphores 6 25 serial I O control from the monitor 10 63 serial number circuit board 2 12 operating system 2 12 user ROM 2 12 se...

Page 214: ...34 timing DRAM 4 4 toggle switch 2 13 troubleshooting 2 17 typographic conventions 10 14 U Ultra 8 4 configuration 8 5 Universe control registers 6 2 initialization values 6 7 interrupt channel 6 20...

Page 215: ...y backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Vi...

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