Artesyn BajaPPC-750, User Manual

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8-16 BajaPPC-750: Serial and Parallel I/O
May 2002
8.4.1 Parallel Port Addressing
The base address for the BajaPPC-750 parallel port is FE00, 0110
16
. The CPU can
read/write the control and data registers. In Enhanced Parallel Port (EPP) mode,
the status register also is read/write. (The EPP registers are available only in EPP
mode. See the
Ultra I/O Controller User’s Manual for details on the EPP registers.)
8.4.2 Parallel Port Registers
The Data Register latches the contents of the data bus upon a write operation and
outputs the results to the PD0–PD7 bits. A reset clears the Data Register.
The Status Register latches during the read cycle and contains the following infor-
mation:
Table 8-10. Addresses for Ultra I/O Parallel Port Registers
Register Hex Address Register Hex Address
Data Base + 0 EPP Data 0 Base + 4
Status Base + 1 EPP Data 1 Base + 5
Control Base + 2 EPP Data 2 Base + 6
EPP Address Base + 3 EPP Data 3 Base + 7
7 6 5 4 3 2 1 0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Register Map 8-7. Ultra I/O Parallel Port Data
7 6 5 4 3 2 1 0
nBUSY nACK PE SLCT nERR 0 0 TMOUT
Register Map 8-8. Ultra I/O Parallel Port Status
nBUSY Busy. Read by CPU as bit 7 of Printer Status Register.
0 = printer is busy, 1 = ready to accept next character
nACK Acknowledge. Read by CPU as bit 6 of Printer Status Register.
0 = character acknowledged, 1 = still processing or character not received