Artesyn BajaPPC-750, User Manual

Page: 126 / 215

Serial Ports 8-9
0002M621-15
The Interrupt Identification Register, IIR, allows the host CPU to determine the
priority and source of an interrupt on a serial port:
The Line Control Register, LCR, controls the format of the serial line:
ERDAI Enable received data available interrupt. 1 = enable
ETHREI Enable transmitter holding register empty interrupt. 1 = enable
ELSI Enable receiver line status interrupt. Error sources are Overrun, Parity,
Framing, and Break. 1 = enable
EMSI Enable modem status interrupt. This bit is set when MSR bits change
state. 1 = enable
0 1 2 3 4 5 6 7
PEND INT_ID 0 0 FIFO_EN
Register Map 8-2. Ultra I/O Serial Port Interrupt Identification, IIR
PEND Interrupt pending. 1 = none pending, 0 = pending
INT_ID[1:3] Interrupt priority identification. Bit 3 is always zero in non-FIFO mode.
1 1 0 = receiver line status (highest priority)
0 1 0 = received data ready
1 0 0 = transmitter holding register empty
0 0 0 = modem status (lowest priority)
FIFO_EN[6:7] Bits are set when FIFO control register bit 0 = 1. Bits 6 and 7 are always
zero in non-FIFO mode (see
Ultra I/O Controller User’s Manual ).
0 1 2 3 4 5 6 7
WLS STB PEN EPS STICK BREAK DLAB
Register Map 8-3. Ultra I/O Serial Port Line Control, LCR
WLS[0:1] Word length select bits. 00 = 5 bits, 10 = 6 bits, 01 = 7 bits, 11 = 8 bits
STB Stop bits. 0 = 1 stop bit, 1 = 1.5 stop bits for 5-bit words or 2 stop bits for
6-,7-, and 8-bit words
PEN Parity enable. 1 = enable