Artesyn ATCA-7480, Installation And Use Manual, Page: 124 / 330

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A )
124
The
UART_CLK
is the
CLK_UART
(48MHz) input divided by the pre-divider set by the Super IO
Configuration Register (Offset 0x29).
The baud rate of the data shifted in/out of the UART is given by:
Baud Rate =
UART_CLK
/ (16X Divisor)
For example, if the pre-divider is 26, the
UART_CLK
is 1.8461538MHz. When the divisor is 12,
the baud rate is 9600.
A divisor value of 0 in the Divisor Latch Register is not allowed.
Table 5-36 Divisor Latch LSB Register (DLL), if DLAB=1
PC IO Address: Base
Bit Description Default Access
7:0 Divisor Latch LSB (DLL) Undef. LPC: r/w
Table 5-37 Divisor Latch MSB Register (DLM), if DLAB=1
LPC IO Address: Base + 1
Bit Description Default Access
7:0 Divisor Latch MSB (DLM) Undef. LPC: r/w