Artesyn ATCA-7480, Installation And Use Manual, Page: 111 / 330

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A)
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5.1.4.2.2 Transmitter Holding Register (THR)
This register holds the next data byte to be transmitted. When the Transmit Shift Register
becomes empty, the contents of the Transmit Holding Register are loaded into the shift
register and the transmit data request (TDRQ) bit in the Line Status Register is set to one.
In FIFO mode, writing to THR puts data to the top of the FIFO. The data at the bottom of the
FIFO is loaded to the shift register when it is empty.
5.1.4.2.3 Interrupt Enable Register (IER)
This register enables four types of interrupts which independently activate the int signal and
set a value in the Interrupt Identification Register. Each of the four interrupt types can be
disabled by resetting the appropriate bit of the IER register. Similarly, by setting the appropriate
bits, selected interrupts can be enabled.
Table 5-25 Transmitter Holding Register (THR) if DLAB=0
LPC IO Address: Base
Bit Description Default Access
7:0 Transmitter Holding register (THR) Undef. LPC: w
Table 5-26 Interrupt Enable Register (IER), if DLAB=0
LPC IO Address: Base + 1
Bit Description Default Access
0 Receive data interrupt enable/disable:
1: receive data interrupt enabled
0: receive data interrupt disabled 0 LPC: r/w
1 Transmitter holding register empty (THRE) interrupt
enable/disable
1: THRE interrupt enabled
0: THRE interrupt disabled 0 LPC: r/w
2 Receiver line status interrupt enable/disable
1: receiver line status interrupt enabled
0: receiver line status interrupt disabled 0 LPC: r/w