Artesyn Embedded Technology ATCA-7490, Installation And Use Manual

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IPMI Feature Set
ATCA-7490 Installation and Use (6806800U11F)
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9.3.10 Payload Power Failure Cause Sensor
The IPMC uses three sensors to monitor the power failure cause of the payload domain. Table
5-51 gives more details about the payload power failure. The Payload Power Failure Registers 1
to 3 are always 0 when the Payload Power Failure status (bit 7) is not set.
The Payload Power Failure Cause Register 2 covers the main board voltages. For more
information, see
Table 5-52 .
The Payload Power Failure Cause Register 3 covers CPU specific voltages. When a CPU is not
mounted (detected via
CPU0_SKTOCC_
and
CPU1_SKTOCC_
) the corresponding power
failure bits will never be set. For more information, see Table 5-53 .
9.4 POST
POST is executed at IPMC startup when either a hard (blade physically extracted/reinserted) or
a cold (IPMI Command) reset is performed. POST verifies the functionality of SRAM, IPMB-0,
EEPROM data storage, FRU-Information, and all devices (primarily sensors) attached to the
IPMC's private master-only I2C bus. A detailed description of POST tests are as follows:

FRU-InformationU - Verifies that the FRU-Information is readable from the external
EEPROM where it is stored. Once read, each section's checksum is computed and
validated.

IPMB-0U - Reads the ready signals coming from the I2C buffers. If this test passes, both
ready signals are active and both IPMB busses (IPMB-A and IPMB-B) are enabled.

EEPROMU - Verifies that the EEPROM contents are readable via I2C. Since the IPMC stores
its runtime and persistent data here, proper operation is crucial.

Master-Only I2CU - Verifies that all expected devices attached to the master-only I2C bus
are accessible.
To obtain results of POST, the IPMC supports the IPMI standard command,
Get Self Test
Results
with OEM extensions. This IPMI command can be run at anytime.