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Maps and Registers

ATCA-7365-CE Installation and Use (6806800L73N)

169

6.3.4.2.3 Interrupt Enable Register (IER)

This register enables four types of interrupts which independently activate the int signal and 
set a value in the Interrupt Identification Register. Each of the four interrupt types can be 
disabled by resetting the appropriate bit of the IER register. Similarly, by setting the appropriate 
bits, selected interrupts can be enabled.

Table 6-29 Interrupt Enable Register (IER), if DLAB=0 

LPC IO Address: Base + 1

Bit

Description

Default

Access

0

Receive data interrupt enable/disable:
1: receive data interrupt enabled
0: receive data interrupt disabled

0

LPC: r/w

1

Transmitter holding register empty 
(THRE) interrupt enable/disable
1: THRE interrupt enabled
0: THRE interrupt disabled

0

LPC: r/w

2

Receiver line status interrupt 
enable/disable
1: receiver line status interrupt enabled
0: receiver line status interrupt disabled

0

LPC: r/w

3

Modem status interrupt enable/disable:
1: modem status interrupt enabled
0: modem status interrupt disabled

0

LPC: r/w

7:4

Reserved

0

LPC: r

Summary of Contents for ATCA-7365-CE

Page 1: ...ATCA 7365 CE Installation and Use P N 6806800L73N May 2016 ...

Page 2: ...o an Artesyn website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Artesyn It is possible that this publication may contain reference to or information about Artesyn products machines and programs programming or services that are not available in your country Such references or information must not be ...

Page 3: ... Inspecting the Blade 43 2 2 Environmental and Power Requirements 44 2 2 1 Environmental Requirements 44 2 2 2 Power Requirements 47 2 3 Blade Layout 49 2 4 Switch Settings 50 2 5 Installing the Blade Accessories 52 2 5 1 DIMM Memory Modules 53 2 5 2 PMEM and SATA Module 55 2 5 3 USB 2 0 Flash Module 56 2 6 Installing and Removing the Blade 57 2 6 1 Installing the Blade 58 2 6 2 Removing the Blade...

Page 4: ...ers 87 4 2 3 Connecting to the Blade 87 4 3 Changing Configuration Settings 87 4 4 Boot Options 89 4 4 1 Supported Boot Devices 89 4 4 2 Selecting The Boot Device 89 4 4 3 By Boot Selection Menu 91 4 4 4 iSCSI Setup for Base and Fabric Ethernet 92 4 4 4 1 iSCSI Boot Configuration 93 4 4 4 2 iSCSI Port Configuration 94 4 4 4 3 ISCSI Port Selection 95 4 4 4 4 iSCSI Challenge Handshake Authentication...

Page 5: ...n ROM Execution 113 4 5 6 Security 114 4 5 7 Save Exit 114 4 6 CPU Performance Settings 114 4 7 Memory Configuration 115 4 7 1 Independent Channel Mode 115 4 7 2 Spare Channel Mode 116 4 7 3 Mirrored Channel Mode 116 4 7 4 Lockstep Channel Mode 116 4 8 Restoring BIOS Default Settings 117 4 9 Shelf Slot Power Requirement 117 4 10 LED Usage 118 4 11 Upgrading the BIOS 118 4 12 BIOS Error Logging 118...

Page 6: ...2 Processor 142 5 3 Memory 142 5 3 1 Persistent memory PMEM Module 143 5 4 Chipset 143 5 5 I O Controller 143 5 6 Firmware Flashes 144 5 7 Ethernet Ports 144 5 8 Storage Controller 145 5 9 Embedded Flash Disk 145 5 9 1 SATA Embedded Flash Solid State Disc SSD 145 5 10 BIOS 146 5 11 IPMC 146 5 12 Serial Redirection 147 5 13 Serial over LAN 147 5 14 Control Logic 148 5 15 Front Board Faceplate 148 5...

Page 7: ...mmable Baud Rate Generator 180 6 4 FPGA Register Mapping 181 6 4 1 LPC I O Register Map 181 6 4 2 IPMC SPI Register Map 182 6 4 3 Module Identification Register 183 6 4 4 Version Register 184 6 4 5 Serial Redirection Control Register 184 6 4 6 Serial over LAN SOL Control Register 185 6 4 7 Serial Line Routing Register 186 6 4 8 IPMC Power Level Register 186 6 4 9 SPD PROM MUX Control Register 187 ...

Page 8: ... Control Register 204 6 4 17 IPMC E Keying Status Register 205 6 4 18 IPMC E Keying Control Register 205 6 4 19 IPMC GPIO Register 206 6 4 20 LED Status and Control Register 207 6 4 21 NMI Status and Control Register 208 6 4 22 Telecom Clock Supervision Registers 208 6 4 22 1 Telecom Clocking Status Registers 208 6 4 22 2 Telecom Timer Registers 210 6 4 23 Miscellaneous Status Control Registers 21...

Page 9: ... 3 Set Serial Interface Properties Command 244 8 4 4 Get Debug Level Command 245 8 4 5 Set Debug Level Command 246 8 4 6 Get Hardware Address Command 247 8 4 7 Set Hardware Address Command 247 8 4 8 Get Handle Switch Command 248 8 4 9 Set Handle Switch Command 249 8 4 10 Get Payload Communication Time Out Command 249 8 4 11 Set Payload Communication Time Out Command 250 8 4 12 Enable Payload Contr...

Page 10: ...re Upgrade 275 10 1 1 Overview 275 10 1 2 Installing the Ipmitool 275 10 1 2 1 Update Procedure 275 10 1 3 Interface 276 10 1 3 1 KCS Interface 276 10 1 3 2 IPMB 0 276 10 1 3 3 IPMI over LAN BASE 276 10 2 IPMC Upgrade 277 10 3 BIOS FPGA Upgrade 278 10 4 Upgrade Package 280 A Replacing Battery 281 A 1 Replacing the Battery 281 B Related Documentation 285 B 1 Artesyn Embedded Technologies Embedded C...

Page 11: ... Chipset North Bridge 101 Table 4 8 Chipset North Bridge Intel R VT for Directed I O Configuration 102 Table 4 9 Chipset North Bridge IOH Thermal Sensors 103 Table 4 10 Chipset South Bridge 103 Table 4 11 Chipset South Bridge USB Configuration 103 Table 4 12 Advanced SATA Configuration 104 Table 4 13 Advanced USB Configuration 105 Table 4 14 Super IO Configuration Serial Port 0 Configuration 106 T...

Page 12: ...mory Information Definition 128 Table 4 41 CPU Failure Event Format 128 Table 4 42 Correctable Memory Log Disabled Event Format 129 Table 4 43 Memory Information Definition 129 Table 4 44 Log Area Reset Cleared Event Format 129 Table 4 45 System Boot Event Format 130 Table 4 46 System Boot Event Format 130 Table 4 47 Status Code Type Definition 131 Table 4 48 Status Code Value Definition 131 Table...

Page 13: ... 20 Logical Device Base IO Address LSB Register 164 Table 6 21 Logical Device Common Decode Ranges 165 Table 6 22 Logical Device Primary Interrupt Register 165 Table 6 23 Logical Device 0x74 Reserved Register 166 Table 6 24 Logical Device 0x75 Reserved Register 166 Table 6 25 Logical Device 0xF0 Reserved Register 166 Table 6 26 UART Register Overview 167 Table 6 27 Receiver Buffer Register RBR if ...

Page 14: ... 195 Table 6 57 RTM SPI Write Register 195 Table 6 58 RTM SPI Read Register 196 Table 6 59 External Interrupt Status Register 196 Table 6 60 Processor Hot Status Control Register 197 Table 6 61 Telecom Status Control Register 198 Table 6 62 Address Map of Interrupt Mask and Map Registers 198 Table 6 63 Interrupt Mask and Map Registers 200 Table 6 64 Flash Status Register 201 Table 6 65 Default Boo...

Page 15: ...Table 8 7 Supported Chassis Device Commands 223 Table 8 8 Configurable System Boot Option Parameters 223 Table 8 9 System Boot Options Parameter 96 224 Table 8 10 System Boot Options Parameter 97 225 Table 8 11 System Boot Options Parameter 98 226 Table 8 12 System Boot Options Parameter 100 Data Format 227 Table 8 13 System Boot Options Parameter 100 SET Command Usage 228 Table 8 14 System Boot O...

Page 16: ...Command Description 252 Table 8 40 Hang IPMC Command Description 252 Table 8 41 Graceful Reset Command Description 253 Table 8 42 Get Payload Shutdown Time Out Command Description 254 Table 8 43 Set Payload Shutdown Time Out Command Description 255 Table 8 44 Get Module State Command Description 255 Table 8 45 Enable Module Site Command Description 257 Table 8 46 Disable Module Site Command Descri...

Page 17: ...t 75 Figure 3 14 Location of USB Flash Module Connector 76 Figure 3 15 USB Flash Module Connector Pin Assignment 77 Figure 3 16 Location of AdvancedTCA Connectors 78 Figure 3 17 P10 Backplane Connector Pinout 79 Figure 3 18 P20 Backplane Connector Pinout Rows A to D 80 Figure 3 19 P20 Backplane Connector Pinout Rows E to H 81 Figure 3 20 P23 Backplane Connector Pinout Rows A to D 81 Figure 3 21 P2...

Page 18: ...Interrupt Structure on ATCA 7365 153 Figure 6 2 IOH36D PCIe Port Mapping on ATCA 7365 156 Figure 7 1 SOL Overview 213 Figure 8 1 System Boot Options Parameter 100 Information Flow Overview 227 Figure 9 1 Location of Temperature Sensors 267 Figure 10 1 IPMC Component Elements 277 Figure 10 2 SPI Bus Connection 279 Figure A 1 Location of On board Battery 281 ...

Page 19: ...re accessories switch settings installation and removal procedures Controls Indicators and Connectors on page 63 describes external interfaces of the blade This includes connectors and LEDs BIOS on page 85 describes the features and setup of BIOS Functional Description on page 141 describes the functional blocks of the blade in detail This includes a block diagram description of the main component...

Page 20: ...ic Input Output System CAS Column Address Strobe CMOS Complementary Metal Oxide Semiconductor DDR Double Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DPLL Digital Phase Locked Loop DRAM Dynamic Random Access Memory ECC Error Correction Code EMC Electromagnetic Compatibility EMV Elektromagnetische Vertraeglichkeit EN European Norm ESCD Extended System Configuration Data ESD Ele...

Page 21: ...nt Interface ISA Industry Standard Architecture ISO International Organization for Standardization LCCB Line Card Clock Building Block LFM Linear Feet per Minute LPC Low Pin Count MAC Media Access Control MTD Memory Technology Device MVCGE MontaVista Carrier Grade Edition NEBS Network Equipment Building System NMI Non Maskable Interrupt NVRAM Non volatile Random Access Memory OEM Original Equipmen...

Page 22: ...le RoHS Restriction of the use of Certain Hazardous Substances SAS Serial Attached SCSI SATA Serial ATA SCSI Small Computer System Interface SDR Sensor Data Record SDRAM Synchronous Dynamic Random Access Memory SELV Safety Extra Low Voltages SMI Serial Management Interface SOL Serial over LAN SPD Serial Presence Detect SPI Serial Peripheral Interface SRAM Static Random Access Memory SROM Serial Re...

Page 23: ...enoutputandcoderelatedelements or commands in body text Courier Bold Used to characterize user input and to separate it from system output Reference Used for references and for table and figure descriptions File Exit Notation for selecting a submenu text Notation for variables and keys text Notation for software buttons to click on the screen and parameter description Repeated item for example nod...

Page 24: ...ntered Pay attention to important information Notation Description Part Number Publication Date Description 6806800L73N May 2016 Removed Declaration of Conformity Updated Copyrights page 6806800L73M September 2015 Updated the sections Standard Compliances on page 38 Installation on page 28 and Installation on page 32 6806800L73L June 2015 Updated the section Environmental Requirements on page 44 6...

Page 25: ... in Installation on page 28 and Installation on page 32 Updated Table 2 4 Updated Standard Compliances on page 38 EMC on page 27 and EMV on page 32 6806800L73C September 2011 Updated Chapter 4 BIOS on page 85 Added Chapter 4 iSCSI Setup for Base and Fabric Ethernet on page 92 Updated Table CPU Configuration on page 98 Updated Table BIOS Supported IPMI Events on page 121 Updated Table Result Second...

Page 26: ...ATCA 7365 CE Installation and Use 6806800L73N About this Manual 26 About this Manual ...

Page 27: ...e telecommunication industry and industrial control Only personnel trained by Artesyn or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipme...

Page 28: ...cordance with this guide may cause harmful interference to radio communications Operating the system in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before ...

Page 29: ...Operation Ensure that the display devices that are permanently connected to the VGA interface provide a fire enclosure according to the IEC EN UL CSA 60950 1 requirements All other devices that are connected only for service purposes to the VGA interface needs supervision during operation and must be disconnected after maintenance Blade Damage Blade surface High humidity and condensation on the bl...

Page 30: ...o malfunction if their setting is changed Therefore do not change settings of switches marked as reserved The setting of switches which are not marked as reserved has to be checked and changed before blade installation Blade Damage Setting resetting the switches during operation can cause blade damage Therefore check and change switch settings before you install the blade Battery Blade Damage Wron...

Page 31: ...nötigen sollten wenden Sie sich bitte an die für Sie zuständige Geschäftsstelle von Artesyn Das System erfüllt die für die Industrie geforderten Sicherheitsvorschriften und darf ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb dürfen nur von durch Artesyn ausgebildetem oder im Bereich Elektron...

Page 32: ...mte Kabel So stellen Sie sicher dass ausreichend Schutz vor Störstrahlung vorhanden ist Die Blades müssen mit der Frontblende installiert und alle freien Steckplätze müssen mit Blindblenden abgedeckt sein Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkstörungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Maßnahmen durchzuführe...

Page 33: ...iegenden OSP Verkabelung Die Zugabe von primären Schutz nicht ausreichenden Schutz um diese Schnittstellen metallisch mit OSP Verdrahtung verbinden Die intra Gebäude Port s des Gerätes oder einer Unterbaugruppe müssen abgeschirmte innerGebäudeVerkabelung Verdrahtung die an beiden Enden geerdet ist zu verwenden Betrieb Stellen Sie sicher daß Geräte die dauerhaft mit der VGA Schnittstelle verbunden ...

Page 34: ...B verursachen In diesem Fall ist Leitung A immer noch unter Spannung auch wenn sie vom Versorgungskreislauf getrennt ist und umgekehrt Prüfen Sie deshalb immer ob die Leitung spannungsfrei ist bevor Sie Ihre Arbeit fortsetzen um Schäden oder Verletzungen zu vermeiden Schaltereinstellungen Fehlfunktion des Blades Schalter die mit Reserved gekennzeichnet sind können mit produktionsrelevanten Funktio...

Page 35: ...liche Explosionen und Beschädigungen des Blades zur Folge haben Verwenden Sie deshalb nur den Batterietyp der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung Umweltschutz Entsorgen Sie alte Batterien und oder Blades Systemkomponenten RTMs stets gemäß der in Ihrem Land gültigen Gesetzgebung und den Empfehlungen des Herstellers ...

Page 36: ...ATCA 7365 CE Installation and Use 6806800L73N Sicherheitshinweise 36 ...

Page 37: ...1066 MHz LVDDR3 memory support 1 35V for better thermal performance and reduced power consumption Intel 5520 I O hub spanning 36 PCIe Gen2 lanes 5 Gbps 4 GB onboard USB flash module assembly option with capacity up to 16GB available upon request PCIe Generation 2 with 5 Gbps Dual Gb Ethernet AdvancedTCA base interface Dual 10 1Gb Ethernet AdvancedTCA fabric interface PICMG opt 9 and 1 Additional G...

Page 38: ...C requirements on system level predefined Artesyn Embedded Technologies system ISO 8601 Y2K compliance PICMG 3 01 and 3 1 1 Environmental conditions and supply voltage do not entirely follow the PICMG 3 0 but are adapted to data center application requirements Defines mechanics blade dimensions power distribution power and data connectors and system management The product has been designed to meet...

Page 39: ...00L73N 39 1 3 Mechanical Data Thefollowingtableprovidesdetailsabouttheblade smechanicaldata suchasdimensionsand weight Table 1 2 Mechanical Data Feature Value Dimensions width x height x depth 30 mm x 351 mm x 312 mm 8U form factor Weight of blade 3 8 kg ...

Page 40: ...Introduction ATCA 7365 CE Installation and Use 6806800L73N 40 1 4 Product Identification The following figure shows the location of the serial number label Figure 1 1 Serial Number Location ...

Page 41: ...cial ATCA Blade Dual Intel Xeon E5620 QUAD CORE 2 4 GHZ 6X 4GB 10G support ROHS 6 6 Table 1 4 Blade Accessories Accessory Description ATCA 7360 MEM 2G 2 GB DDR3 VLP memory module for ATCA 736X product series ATCA 7360 MEM 4G 4 GB DDR3 VLP memory module for ATCA 736X product series ATCA 7360 MEM 8G 8 GB DDR3 VLP memory module for ATCA 736X product series RTM ATCA 7360 RTMfortheATCA 736Xproductserie...

Page 42: ...persistent memory 16MB SRAM 64MB Flash for the ATCA 736X product series2 RJ45 DSUB ATCA7140 RJ 45 DSUB cable for the ATCA 7140 7150 7350 736X SA BBS WR30 7360 CD BBS SW and WR PNE3 0 for ATCA 7360 7365 1 HDD kit option for RTM ATCA 7360 and RTM ATCA 7360 L 2 Persistent memory and solid state disk mutually exclusive Table 1 4 Blade Accessories continued Accessory Description ...

Page 43: ...k for damage and report any damage or differences to the customer service 3 Remove the desiccant bag shipped together with the blade and dispose of it according to your country s legislation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure that you are worki...

Page 44: ...istics meeting at least the CP TA B 4 cooling profile The environmental requirements of the blade may be further limited down due to installed accessories such as hard disks or mezzanine modules with more restrictive environmental requirements Operating temperatures refer to the temperature of the air circulating around the blade and not to the actual component temperature Blade Damage Blade Surfa...

Page 45: ...ssories Temperature Change 0 25 C min according to NEBS Standard GR 63 CORE 0 25 C min Relative Humidity 5 to 90 non condensing according to Artesyn internal environmental requirements 5 to 95 non condensing according to Artesyn internal environmental requirements Vibration 0 1 gfrom5to100Hzandbackto5Hz at a rate of 0 1 octave minute 5 20 Hz at 0 01 g2 Hz 20 200 Hz at 3 0 dB octave Random 5 20 Hz ...

Page 46: ...9 CE30 Q51 MHS4 P23 CE31 Q77 Q50 R3627 R3628 R3629 R3630 R3635 R3636 R3651 R3652 F10 F7 F8 F11 MHS3 R1597 R1598 R1615 Q55 Q51 C3692 C3686 R3616 R3615 L83 C4053 MHS4 R2719 C4715 Q78 Q77 C3710 C3704 C3698 C3934 L93 C4529 C4530 C4531 C4532 C4533 C4534 J1 C4561 C4562 C4563 C4564 C4490 C4497 C4498 C4435 C4436 C4765 C4766 C4767 C3144 R2718 C4698 C4713 C4714 Q54 Q50 C3725 C3720 C3715 C3687 L82 C4527 C452...

Page 47: ...n the installed hardware accessories If you want to install accessories on the blade the load of the respective accessory has to be added to that of the blade In the following table you will find typical examples of power requirements with and without accessories installed For information on the accessories power requirements refer to the documentation delivered together with the respective access...

Page 48: ...h software simultaneously exercising as many functions and interfaces as possible This includes a particular load software provided by Intel designed to stress the processors to reach their theoretical maximum power specification Any difference in the system configuration or the software executed by the processors may affect the actual power dissipation Depending on the actual operating configurat...

Page 49: ...Preparation and Installation ATCA 7365 CE Installation and Use 6806800L73N 49 2 3 Blade Layout The following figure shows the location of components on the ATCA 7365 CE blade Figure 2 2 ATCA 7365 CE Blade Layout ...

Page 50: ...erved The setting of switches which are not marked as Reserved has to be checked and changed before blade installation Blade Damage Setting resetting the switches during operation can cause blade damage Therefore check and change switch settings before you install the blade For normal operation all switches must be OFF Switches are used only for repair manual maintenance and critical crisis recove...

Page 51: ...e and ME working in S0 S1 default ON Flash security descriptor and ME disabled for debugging only SW2 1 Serial Line 1 and 2 Routing OFF FPGA COM 1 to faceplate FPGA COM 2 to RTM default ON FPGA COM 1 to RTM FPGA COM 2 to faceplate Note IPMC COM1 2 routing selection has precedence For details see Serial Output Commands on page 236 SW2 2 IPMC Debug Console Routing OFF IPMC debug console at 3 pin hea...

Page 52: ...ush button OFF Reset push button enabled default ON Reset push button disabled SW3 4 ICH10 TCO Timer system reboot feature OFF ICH10 TCO Timer system reboot feature enabled default ON ICH10 will disable the TCO Timer system reboot feature SW4 1 Reserved OFF Default SW4 2 ICH10 TCO Timer system reboot feature OFF ICH10 TCO Timer system reboot feature enabled default ON system is strapped to the No ...

Page 53: ...MM are allowed The reason is the thermal limit budget of the blade and the high variationofthepowerconsumptionsofdifferentDIMMMtypes Forthermalreasons no4 rank DIMMs and no dual Die DIMM are allowed ATCA 7365 CE supports low voltage DDR3 memory This is available upon request DIMM modules used within one channel must be based on the same memory technology To achieve proper functionality in all use ...

Page 54: ...able repeat steps 2 to 3 to install further modules Removal Procedure To remove a DIMM module proceed as follows 1 Remove the blade from system as described in Installing and Removing the Blade on page 57 2 Open the locks of socket at both sides The memory module is automatically lifted up 3 Remove module from socket 4 Repeat steps 2 to 3 in order to remove further memory modules Damage of Circuit...

Page 55: ...y to ICH10 SATA Port 5 The extension module is mechanically fastened to the blade with two screws The location of the two corresponding mounting holes as well as the S F memory module connector is shown in Figure 2 2 on page 49 The PMEM and SATA module are accessory kits and are not part of the default ATCA 7365 The following procedure describes the steps to install remove the PMEM SATA module Ins...

Page 56: ...lade from the system as described in Installing and Removing the Blade on page 57 2 Remove the two screws holding the PMEM SATA module 3 Remove the PMEM SATA module from the blade 4 Reinstall the blade into the system as described in Installing and Removing the Blade on page 57 2 5 3 USB 2 0 Flash Module The blades provides a USB 2 0 flash module with a capacity of 4 GB or 16 GB The corresponding ...

Page 57: ...re To install a USB flash module proceed as follows 1 Remove blade from system as described in Removing the Blade on page 61 2 Insert new flash module in socket see figure Figure 2 2 on page 49 3 Tighten the screw on the left side of the flash module 2 6 Installing and Removing the Blade The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelves Dam...

Page 58: ...CA shelf proceed as follows Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Blade Malfunctioning Incorrect blade installation and removal can result in blade malfunctioning When plugging the blade in or removi...

Page 59: ...op and bottom ejector handles are in the outward position by squeezing the lever and the latch together 2 Insert blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf Ensure that the guiding module of shelf and blade are aligned properly 3 Apply equal and steady pressure to the blade to carefully slide the blade into the shelf until you feel resistan...

Page 60: ... completely installed the blue LED starts to blink This indicates that the blade announces its presence to the shelf management controller 6 Wait until the blue LED is switched off then tighten the faceplate screws which secure the blade to the shelf The switched off blue LED indicates that the blade s payload has been powered up and that the blade is active 7 Connect cables to the faceplate if ap...

Page 61: ... the faceplate Do not rotate the handle fully outward The blue LED blinks indicating that the blade power down process is ongoing 2 Wait until the blue LED is illuminated permanently then unlatch the upper handle and rotate both handles fully outward Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the...

Page 62: ...faceplate cables if applicable 4 Unfasten the screws of the faceplate until the blade is detached from the shelf 5 Remove the blade from the shelf Data Loss Removing the blade with the blue LED still blinking causes data loss Wait until the blue LED is permanently illuminated before removing the blade ...

Page 63: ...9 C3534 D54 R1247 C1481 R1219 C4340 C1463 C1453 R1235 R1236 R1238 R1243 R1223 J220 T220 C3026 J117 L20 R2753 R2755 R2770 R2772 R2777 R2779 C4668 C4669 C4670 C4672 C4675 C4678 C4683 C4686 R1240 R2809 R2811 C4682 L49 L51 Q28 R2790 R2810 R2812 P39 Q29 C4730 Q87 C4202 L97 R3499 C3148 R2722 C4326 C4324 C4321 C4320 C2101 R1681 C4297 C4296 R1677 C4318 R3627 R3628 R3639 R3640 R3630 R3635 R3652 R3629 R3636...

Page 64: ...trols Indicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 64 3 2 Faceplate The following figure illustrates the connectors keys and LEDs available on the faceplate Figure 3 2 Faceplate ...

Page 65: ...Controls Indicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 65 Figure 3 3 Faceplate with VGA Module ...

Page 66: ...Controls Indicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 66 3 2 1 LEDs The following figure illustrates all LEDs available on the faceplate Figure 3 4 Location of Faceplate LEDs ...

Page 67: ...n red amber and is programmable through IPMC Its default color is green and its local control state is off It permits override control by higher layer software such as middle ware or applications as specified in PICMG 3 0 specification ATN Attention This LED has amber color and is programmable through IPMC Its local control state is off It permits override control by higher layer software such as ...

Page 68: ...FRU State Machine During blade installation Permanently blue On board IPMC powers up Blinking blue Blade communicates with shelf manager OFF Blade is active During blade removal Blinking blue Blade notifies shelf manager of its desire to deactivate Permanently blue Blade is ready to be extracted Table 3 1 FacePlate LEDs continued LED Description Figure 3 5 Location of FacePlate Reset Key You canno...

Page 69: ...Ethernet Connector The blade provides one Ethernet 1000Base T interface connector at its faceplate It is intended for blade configuration and constitutes besides the two AdvancedTCA Base interfaces a third Ethernet interface to access the blade The location of the Ethernet connector is shown in the following figure The pinout of the connector is as follows Figure 3 6 Location of Ethernet Connector...

Page 70: ...ard switch 2 1 allows to swap COM1 with COM2 and thus make COM2 accessible via the faceplate connector instead Note that the BIOS serial redirection feature uses COM1 as access interface Therefore swapping the serial interfaces via SW2 1 also changes the serial connector that you need to access to make use of the serial redirection feature The location of the connector is shown in the following fi...

Page 71: ...e USB 2 0 standard and correspond to the blade s USB interfaces 3 and 4 Their location is shown in the following figure The pinout of each USB connector is given in the following Figure 3 10 Location of USB Connectors Figure 3 11 USB Connector Pinout Exceeding the maximum USB current rating of 500mA per Port will result in ATCA 7360 protecting itself through a controlled board shutdown ...

Page 72: ...age 150 Table 3 2 VGA 7360 Module Connector Pinout Pin Signal Pin Signal 1 GND 2 GND 3 1 8V 4 PCIE_TX 5 1 8V 6 PCIE_TX 7 GND 8 GND 9 3 3V 10 PCIE_RX 11 3 3V 12 PCIE_RX 13 GND 14 GND 15 5V 16 PCIE_CLK100MHz 17 PCIE_RST 18 PCIE_CLK100MHz 19 GND 20 GND Table 3 3 FacePlate VGA Connector Signals Pin Signal Pin Signal Pin Signal 11 6 GND 1 RED 12 SDA 7 GND 2 GREEN 13 HSYNC 8 GND 3 BLUE 14 VSYNC 9 5V 4 1...

Page 73: ...owing types of signals PCI interface signals I2C signals for connection with on board IDROM device Four configuration pins used for memory configuration 1 SATA port connection ICH10 port 5 Power supply 5V and 3 3V Ensure that the display devices that are permanently connected to the VGA interface provide a fire enclosure according to the IEC EN UL CSA 60950 1 requirements All other devices that ar...

Page 74: ...ndicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 74 The location of the PMEM SFMEM module connector is illustrated in the following figure Figure 3 12 Location ofPMEM SFMEM Module Connector ...

Page 75: ...Controls Indicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 75 The pinout of this connector is illustrated in the following figure Figure 3 13 PMEM SATA Module Connector Pinout ...

Page 76: ...nectors ATCA 7365 CE Installation and Use 6806800L73N 76 3 3 2 USB Flash Module Connector The location of the flash memory module connector is illustrated in the following figure Figure 3 14 Location of USB Flash Module Connector ...

Page 77: ...s Indicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 77 You can find the pin assignment of the flash connector in the following figure Figure 3 15 USB Flash Module Connector Pin Assignment ...

Page 78: ...ncedTCA Backplane Connectors The AdvancedTCA backplane connectors reside in the three zones 1 to 3 as specified by the AdvancedTCA standard and are called P10 P20 and 23 and P30 and 32 The pinouts of all these connectors are given in this section Figure 3 16 Location of AdvancedTCA Connectors ...

Page 79: ...wer feed for the blade VM48_x_CON and RTN_x_CON Power enable ENABLE_x IPMB bus signals IPMB0_x_yyy Geographic address signals HAx Ground signals SHELF_GND and GND Reserved signals Zone 2 contains the two connectors P20 and P23 They carry the following types of signals Telecom clock signals CLKx_ Base interface signals BASE_ Figure 3 17 P10 Backplane Connector Pinout ...

Page 80: ...tional in the AdvancedTCA specification and are unused on the blade If the AdvancedTCA specification defines these signals as input signals they are terminated on the blade and marked as TERM_ in the following pinouts In all other cases the pins are unconnected and consequently marked as n c The pinouts of P20 and P23 are as follows Figure 3 18 P20 Backplane Connector Pinout Rows A to D ...

Page 81: ...Controls Indicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 81 Figure 3 19 P20 Backplane Connector Pinout Rows E to H Figure 3 20 P23 Backplane Connector Pinout Rows A to D ...

Page 82: ...ains the two connectors P30 and P32 They are used to connect an RTM to the blade and carry the following signals Serial RS232_x_yyyy Serial ATA SATAx_yyy USB USBxy PCI Express PCIEx_yyy IPMI IPMB1_xxx ISMB_xxx Power VP12_RTM V3P3_RTM VP5_RTM Figure 3 21 P23 Backplane Connector Pinout Rows E to H ...

Page 83: ...7365 CE Installation and Use 6806800L73N 83 SAS Update channels General control signals BD_PRESENTx RTM_PRSNT_N RTM_RST_KEY RTM_RST Figure 3 22 P30 Backplane Connector Pinout Rows A to D Figure 3 23 P30 Backplane Connector Pinout Rows E to H ...

Page 84: ...Controls Indicators and Connectors ATCA 7365 CE Installation and Use 6806800L73N 84 Figure 3 24 P32 Backplane Connector Pinout Rows A to D Figure 3 25 P32 Backplane Connector Pinout Rows E to H ...

Page 85: ...he blade is based on the AMI UEFI BIOS with several Artesyn Embedded Technologies extensions integrated Its main features are Initialize CPU chipset and memory Initialize PCI devices Setup utility for setting configuration data IPMC support Serial console redirection for remote blade access Boot operation system The BIOS complies with the following specifications UEFI Specification 2 0 Plug and Pl...

Page 86: ...mal PC keyboard input The serial console redirection feature can be configured via a setup utility 4 2 1 Requirements for Serial Console Redirection For serial console redirection the following is required Terminal or terminal emulation which supports a VT100 mode NULL modem cable Terminal emulation programs such as TeraTermPro can be used In order to use TeraTermPro using the function keys the ke...

Page 87: ...terminal The following communication parameters are used by default Baud rate 9600 Flow control None VT 100 8 data bits No parity 1 stop bit 4 2 3 Connecting to the Blade Procedure To connect to the blade using the serial console redirect feature 1 Configure terminal to communicate using the same parameters as in BIOS setup 2 Connect terminal to NULL modem cable 3 Connect NULL modem cable to COM p...

Page 88: ... bottom of the menu Additionally an item specific help is displayed on the right side of the menu window Figure 4 1 Main Menu Make sure that BIOS is properly configured prior to installing the operating system and its drivers If you save changes in setup the next time the blade boots up BIOS will configure the system according to the setup selections stored If those values cause the system boot to...

Page 89: ...e SATA interface available only when SSD SATA is assembled Storage devices connected to the SAS controller by RTM Network Front Panel Ethernet Base Ethernet and Ethernet on RTM Storage devices connected to the Fiber Channel module by RTM iSCSI block devices connected to Base or Fabric Ethernet 4 4 2 Selecting The Boot Device There are two possibilities to determine the device from which BIOS attem...

Page 90: ... devices from which BIOS attempts to boot the operating system 3 Enter the submenu Option ROM Execution to enable disable booting from specific devices Changes have to be saved and the board has to be rebooted when changing the Option ROM Execution If BIOS is not successful at booting from one device it tries to boot from the next device on the list Figure 4 2 Boot Menu ...

Page 91: ...nu 1 From the menu select Save Exit 2 Override existing boot sequence by selecting another boot device from the boot override list Figure 4 3 Save and Exit Menu If the selected device does not load the operating system BIOS resets the board and reverts to the previous boot sequence ...

Page 92: ...om the menu select Boot 2 Under the Option ROM Execution sub menu select the iSCSI item of Fabric Network Boot setup option 3 Save and Exit the BIOS setup 4 To enter iSCSI setup press Ctrl D when the following message is displayed Intel R iSCSI Remote Boot version 2 7 53 Copyright c 2003 2010 Intel Corporation All rights reserved Press ESC key to skip iSCSI boot initialization Press Ctrl D to run ...

Page 93: ...allation and Use 6806800L73N 93 4 4 4 1 iSCSI Boot Configuration The following figure depicts the iSCSI Boot Configuration screen Enter Initiator and Target network configuration parameter Figure 4 5 iSCSI Boot Configuration ...

Page 94: ...BIOS ATCA 7365 CE Installation and Use 6806800L73N 94 4 4 4 2 iSCSI Port Configuration The following figure depicts the iSCSI Port Configuration screen Figure 4 6 iSCSI Port Configuration ...

Page 95: ...t Selection screen Enter Initiator and Target network configuration parameter The following table provides information about Ethernet Port Mapping Figure 4 7 iSCSI Port Selection Table 4 2 Ethernet port mapping Network Device iSCSI Option ROM Device Base1 Dev 10C9 Loc 1 0 0 Base2 Dev 10C9 Loc 1 0 1 Fabric1 Dev 10FC Loc 4 0 0 ...

Page 96: ...priority hot keys Key Function P Selected device is primary boot device S Selected device is secondary boot device D Disable selected device B Blink LED not supported Enter Enter the Port configuration menu for the selected device Table 4 2 Ethernet port mapping continued Network Device iSCSI Option ROM Device ...

Page 97: ...Configuration The following figure depicts the iSCSI CHAP Configuration screen Enter Challenge Handshake Authentication Protocol configuration parameter 4 5 BIOS Setup Configuration 4 5 1 Main The following table contains description about the options that can be configured on Main Figure 4 8 iSCSI CHAP Configuration ...

Page 98: ...Item Values Description Hyper threading Enabled Default Disabled Enabled for OS optimized for Hyper Threading Technology Disabled for other OS not optimized for Hyper Threading Technology When Disabled only one thread per enabled core is enabled Active Processor Core All Default 1 2 3 4 5 Number of cores to enable in each processor package LimitCPUIDMaximum Enabled Disabled Default If set to enabl...

Page 99: ...rformance Optimization for Server workloads See CPU Performance Settings on page 114 Intel Virtualization Enabled Default Disabled When enabled a VMM can utilize the additional hardware capabilities provided by Intel Virtualization Technology Turbo Mode Enabled Default Disabled Enable Disable Turbo Mode Turbo Mode allows processor cores to run faster than the marked frequency if the physical proce...

Page 100: ...Socket 0 CPU Information Show CPU 0 Information CPU String Stepping and Microcode Version Socket 1 CPU Information Show CPU 1 Information CPU String Stepping and Microcode Version Table 4 5 CPU Configuration continued Item Values Description Table 4 6 Memory Configuration Item Values Description DIMM Information Submenu for displaying DIMM presence and size information MemoryMode Independent Defau...

Page 101: ...a significant chance of further corruption to an uncorrectable error The Integrated Memory Controller will issue a Patrol Scrub in the background at a rate sufficient to write every line once a day DemandScrub Enable Disable Default Enable Disable Demand Scrubbing Feature If a single ECC memory error is detected during normal read write operation the correct data and ECC check bits will be written...

Page 102: ...etect RTM is set to Enable Table 4 7 Chipset North Bridge continued Item Values Description Table 4 8 Chipset North Bridge Intel R VT for Directed I O Configuration Item Values Description Intel R VT d Enable Disable Default Enable Disable Intel Virtualization Technology for Directed I O VT d extends Virtualization Technology by providing hardware support for I O device virtualization Interrupt Re...

Page 103: ...les disables integrated North Bridge thermal sensors Recommended value Disable Low Threshold 70 127 Default 90 Low temperature threshold for thermal sensor High Threshold 70 127 Default 100 High temperature threshold for thermal sensor Catastrophic Threshold 70 127 Default 110 Critical temperature threshold for thermal sensor Table 4 10 Chipset South Bridge Item Values Description Front Panel Ethe...

Page 104: ...s Description Table 4 12 Advanced SATA Configuration Item Values Description SATA Mode Disable IDE Mode Default AHCIMode RAID Mode Select the SATA Mode Disable Disable the SATA controller IDE Mode SATA controller works in IDE compatible mode AHCI Mode STATA controller works in AHCI Mode RAID Mode STATA controller works in RAID Mode Additionally a SATA RAID Option Rom is loaded SATA Controller 0 Di...

Page 105: ...ulation Enabled Default Disabled Enables I O port 60h 64h emulation support This should be enabled for the complete USB keyboard legacy support for non USB aware OS Device Reset timeout 10 40 seconds Default 20 sec USB mass storage device Start Unit command timeout 10 20 30 40 seconds ControllerTimeout 1 20 seconds Default 20 sec The time out value for Control bulk interrupt transfer 1 5 10 20 sec...

Page 106: ...rial Port Enabled Default Disabled Enable or Disable Serial Port COM 0 ChangeSettings Auto IO 3F8h IRQ 4 Default IO 3F8h IRQ 3 4 5 6 7 10 11 12 IO 2F8h IRQ 3 4 5 6 7 10 11 12 IO 3E8h IRQ 3 4 5 6 7 10 11 12 IO 2E8h IRQ 3 4 5 6 7 10 11 12 Select IO port and Interrupt settings for COM 0 Table 4 15 Advanced Serial Port Console Redirection Item Values Description Console Redirection Enabled Default Dis...

Page 107: ...sy lines may require lower speeds Data Bits 7 8 Default Data Bits Parity None Default Even Odd Mark Space A parity bit can be sent with the data bits to detect some transmission errors Even parity bit is 0 if the number of 1 s in the data bits is even Odd parity bit is 0 if number of 1 s in the data bits is odd Mark parity bit is always 1 Space Parity bit is always 0 Mark and Space Parity do not a...

Page 108: ...e options that can be configured for MBIOS Event Log Settings Table 4 17 Advanced UEFI Network Stack Item Values Description UEFINetworkstack Enable Disable Default Enable Disable the UEFI network stack This is needed for UEFI network boot PXE and iSCSI Table 4 18 Advanced Runtime Error Logging Item Values Description Runtime Error Logging Enabled Default Disabled Enable Disable Runtime Error Logg...

Page 109: ...lt Erase Immediately Choose options for reactions to a full SMBIOS Event Log This option does not take effect until the computer is restarted LogEFIOEMErrors Enabled Default Disabled Enable or disable the logging of EFI Error Codes as OEM Codes Convert OEM Codes Enabled Default Disabled Enable or disable the converting of EFI Error Codes to Standard SMBIOS Types EFI Errors which cannot be translat...

Page 110: ...tion POST Timer FRB2 Enable Disable Default Enable or Disable FRB2 timer POST timer This watchdog monitors BIOS initialization tasks FRB2 Timer timeout 3 4 5 6 minutes Default 6 minutes Enter value Between 3 to 6 min for FRB2 Timer Expiration value Not available if Frb2 Timer is disabled FRB2 Timeout Action Do Nothing Reset Default Power Down Power Cycle Configure how the system should respond if ...

Page 111: ... if O S Boot Watchdog Timer is disabled Table 4 22 IPMI IPMI Watchdog Configuration continued Item Values Description Table 4 23 IPMI System Event Log Item Values Description LogEFIStatusCodes Disabled Both Default Error code Progress code Configure the logging of EFI Status Codes to IPMI Firmware Progress Error events and other Status Error IPMI events See chapter 4 10 3 IPMI Error Logging Table ...

Page 112: ...is enabled Target Port 0 Target Port Not available when DHCP is enabled Boot LUN 0 Hexadecimal representation of the LUNumber Examples are 4752 3A4F 6b7e 2F99 6734 9 156f 127 4186 9 Not available when DHCP is enabled CHAP Type None Default One Way Mutual Select the CHAP Challenge Handshake Authentication Protocol type Save Changes Press Enter to Save Changes Back To Previous Page Press Enter to Re...

Page 113: ...oot is required BaseNetworkBoot Enabled Default Disabled Controls execution of the Option ROM for both Base Network Ethernet controller Select Enabled when Base Network Boot is required FabricNetworkBoot Enabled Default Disabled Controls execution of the Option ROM for both Fabric Network Ethernet controller Select Enabled when Fabric Network Boot is required ARTMNetworkBoot Enabled Disabled Defau...

Page 114: ...ecommends different settings of the CPU prefetcher for Westmere EP Xeon 56xx CPUs See Advanced CPU Configuration on page 98 Table 4 27 Save Exit Item Description Save Changes and Exit Exit BIOS setup after saving the changes Discard Changes and Exit Exit BIOS setup without saving any changes Save Changes and Reset Reset the system after saving the changes Discard Changes and Reset Reset system set...

Page 115: ...different CPU settings in order to select the best configuration 4 7 Memory Configuration The Intel Xeon processor 5600 series supports four different memory RAS Reliability Availability and Serviceability Modes Independent Channel Mode Spare Channel Mode Mirrored Channel Mode and Lockstep Channel Mode 4 7 1 Independent Channel Mode In independent mode all three channels are operating independentl...

Page 116: ...ross channels DIMM organization in each slot of one channel must be identical to the DIMM in the corresponding slot of the other channel When mirroring is enabled the memory image in Channel 0 is maintained the same as Channel 1 DIMMs in Channel 2 are unused Uncorrectable errors are logged and signaled as correctable but change the channel state to Disabled and the working partner to Redundancy Lo...

Page 117: ...t location of SW4 3 Install and power up the blade See Installing and Removing the Blade on page 57 for the exact procedure 4 Wait until the blade has completely booted and is up and running 5 Remove the blade from the system again See Installing and Removing the Blade on page 57 for the exact procedure 6 Set switch SW4 3 and SW4 4 to OFF Now the BIOS default settings are restored 4 9 Shelf Slot P...

Page 118: ...ade kit contains documentation which describes in detail how to upgrade the BIOS Update tool for Linux is provided with Basic Blade Services BBS For details on how to upgrade BIOS from Linux please refer to Basic Blade Services Software for the ATCA 7365 Programmer s Reference The BIOS can also be upgraded via IPMI HPM 1 Hardware Platform Management IPM Controller Firmware Upgrade Please refer to ...

Page 119: ...able memory error is always logged Error Logging Limit The number of logged correctable memory errors for a DIMM is limited If the last entry in the log is SMBIOS Correctable memory log disabled and IPMI Memory event Correctable ECC logging limit reached No further correctable errors are logged for this DIMM Table 4 28 Logged Error Events Error SMIBIOS IPMI Correctable Correctable ECC Memory Error...

Page 120: ...Enable Inject Errors in Event Logs SMBIOS Event Log Settings in BIOS setup The following errors are injected short before the OS is booted No Console found IPMI Boot Parameter Checksum error CPU Self test failure Bad battery These errors are logged to SMBIOS error log IPMI error log local SEL and Shelf manager and to the console ...

Page 121: ...U BIST Error 22h PCI Out Of Resource 50h IPMI Boot Parameter Default Area Read Error 51h IPMI Boot Parameter Default Area Locked 52h IPMI Boot Parameter Default Area Checksum Error 53h IPMI Boot Parameter User Area Read Error 54h IPMI Boot Parameter User Area Locked 55h IPMI Boot Parameter User Area Checksum Error 56h IPMI Boot Parameter User Area Write Error 60h North Bridge Error 62h No Space fo...

Page 122: ... Offset 00h No bootable media no boot device found Battery 29h Offset 01h Battery failed System Firmware Progress 0Fh Offset 00h System Firmware Error 70h Front Panel Network not detected 78h Base Network not detected 79h Base Network reduced PCI performance 7Ah Base Network Device Error 80h Fabric Network not detected 81h Fabric Network reduced PCI performance 82h Fabric Network Device Error 88h ...

Page 123: ...m the DMI structure System Event Log Type 15 The DMI table can be read by the Linux tool dmidecode The Log Change Token in SMBIOS Type 15 structure is not supported The following SMBIOS Events are supported Single bit ECC memory error Multi bit ECC memory error POST Error PCI Parity Error PCI System Error CPU Failure Correctable memory log disabled Log Area Reset Cleared System boot OEM Event EFI ...

Page 124: ...C Memory Error event format Offset Name Format Description 00h Event Type BYTE Event Type 01h 01h Length BYTE always 0Ch 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time 08h 0Bh Memory Information UINT32 OEM extension Table 4 31 Memory Information Definition Bit Description 0 7 reserved 8 15 DIMM number per Channel 0 1 16 23 DIMM channel 0 2 24 31 CPU ...

Page 125: ...elds contain the BCD representation of the date and time 08h 0Bh Memory Information UINT32 OEM extension Table 4 33 Memory Information Definition Bit Description 0 7 reserved 8 15 DIMM number per Channel 0 1 16 23 DIMM channel 0 2 24 31 CPU Socket 0 1 Table 4 32 Multi bit ECC Memory Error Event Format continued Offset Name Format Description Table 4 34 POST Error Event Format Offset Name Format De...

Page 126: ...8 OEM IPMI failure 29 OEM IPMI Boot Parameter read write error 30 OEM IPMI Boot Parameter checksum error 31 OEM IPMI Boot Parameter locked Table 4 36 Result Second DWORD supported POST Errors Bit Description 0 OEM unspecified error 1 OEM North Bridge error 2 OEM CPU error This bit will be set additionally when a SMBIOS CPU Failure event is logged 3 Front Panel Network Error 4 Base Network Error 5 ...

Page 127: ...ble 4 37 PCI ParitY Error Event Format Offset Name Format Description 00h Event Type BYTE Event Type 09h 01h Length BYTE Always 0Ch 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time 08h 0Bh PCI Information UINT32 OEM extension Table 4 38 PCI Information Definition Bit Description 0 7 Reserved 8 15 PCI Function 16 23 PCI Device 24 31 PCI Bus number Table...

Page 128: ...ed 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time 08h 0Bh PCI Information UINT32 OEM extension Table 4 40 Memory Information Definition Bit Description 0 7 Reserved 8 15 PCI Function 16 23 PCI Device 24 31 PCI Bus number Table 4 39 Multi bit ECC Memory Error Event Format continued Offset Name Format Description Table 4 41 CPU Failure Event Format Off...

Page 129: ...h 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time 08h 0Bh Memory Information UINT32 OEM extension Table 4 43 Memory Information Definition Bit Description 0 7 Reserved 8 15 DIMM number per Channel 0 1 16 23 DIMM channel 0 2 24 31 CPU Socket 0 1 Table 4 44 Log Area Reset Cleared Event Format Offset Name Format Description 00h Event Type BYTE Event Type...

Page 130: ...ormat Offset Name Format Description 00h Event Type BYTE Event Type 17h 01h Length BYTE Always 08h 02h 07h Date Time Fields BYTE These fields contain the BCD representation of the date and time Table 4 46 System Boot Event Format Offset Name Format Description 00h Event Type BYTE Event Type E0h 01h Length BYTE Always 14h 02h 07h Date Time Fields BYTE These fields contain the BCD representation of ...

Page 131: ...gy framework download htm 4 12 4 10 1Artesyn OEM Extensions Class Computing Unit Table 4 47 Status Code Type Definition Bit Description 0 7 Type 2 Error Code 8 23 Reserved 24 31 Severity 4 Minor 8 Major Table 4 48 Status Code Value Definition Bit Description 0 15 Operation code 16 23 SubClass code 24 31 Class code Table 4 49 Class Code Bit Description 0h Computing Unit 1h Peripheral 2h IO Bus 3h S...

Page 132: ... has booted a OS the reading of the POST code sensor returns no valid status code 800Dh North Bridge Error Table 4 51 SubClass EFI_COMPUTING_UNIT_FIRMWARE_PROCESSOR 02h IPMI Operation Code Description 8100h IPMI Boot Parameter USER area read error 8101h IPMI Boot Parameter DEFAULT area read error 8102h IPMI Boot Parameter USER area write error 8103h IPMI Boot Parameter DEFAULT area write error 810...

Page 133: ...0 0x4F PEI execution after memory detection 0x50 0x5F PEI errors 0x60 0xCF DXE execution up to BDS 0xD0 0xDF DXE errors 0xE0 0xE8 S3 Resume PEI 0xE9 0xEF S3 Resume errors PEI 0xE8 0xEF Memory initialization errors 0xB0 0xBF Additional Memory Initialization Status Codes 0xE8 0xEE Additional Memory Error Status Codes Table 4 53 SEC Status Codes Status Code Description 0x0 Not used Progress Codes 0x1...

Page 134: ...ot loaded Table 4 54 PEI Status Codes Status Code Description Progress Codes 0x10 PEI Core is started 0x15 Pre memory North Bridge initialization is started 0x19 Pre memory South Bridge initialization is started 0x2F Memory initialization other 0x31 Memory Installed 0x32 CPU post memory initialization is started 0x33 CPU post memory initialization Cache initialization 0x34 CPU post memory initiali...

Page 135: ...arly memory controller initialization 0xB6 Check DIMM population 0xB7 Channel initialization 0xB8 Channel training 0xB9 Run Build In Self Test 0xBA Initialize memory map 0xBB Setup RAS configuration 0xBF Memory initialization complete PEI Error Codes 0x53 Memory initialization error No usable memory detected 0x55 Memory not installed 0x56 Invalid CPU type or Speed 0x57 CPU mismatch 0x58 CPU self t...

Page 136: ...ed 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5 0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB 0xFF Reserved for future AMI error codes Table 4 55 DXE Status Codes Status Code Description 0x60 DXE Core is started 0x61 NVRAM initialization 0...

Page 137: ...ialize Boot Variables 0x90 Boot Device Selection BDS phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resources 0x97 Console Output devices connect 0x98 Console input devices connect 0x99 Super IO Initialization 0x9A USB initialization...

Page 138: ...B2 Legacy Option ROM Initialization 0xB3 System Reset 0xB4 USB hot plug 0xB5 PCI bus hot plug 0xB6 Clean up of NVRAM 0xB7 Configuration Reset reset of NVRAM settings DXE Error Codes 0xD0 CPU initialization error 0xD1 North Bridge initialization error 0xD2 South Bridge initialization error 0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error Out of Resources...

Page 139: ...0xD8 Invalid password 0xD9 Error loading Boot Option LoadImage returned error 0xDA Boot Option is failed StartImage returned error 0xDB Flash update is failed 0xDC Reset protocol is not available Table 4 55 DXE Status Codes continued Status Code Description ...

Page 140: ...BIOS ATCA 7365 CE Installation and Use 6806800L73N 140 ...

Page 141: ...Ie x4 PCIe x4 PCIe x4 PCIe x4 PCIe x4 Zone 3 X F M R 10 100 1000Base T ICH10 PHY 82567 PMEM SATA Module SATA 4GB SSD ESI PCI SATA SATA USB2 0 ICH10 Port 0 2 USB2 0 ICH10 Port 6 SPI Debug Socket Rec SPI SPI FPGA COM COM_RTM Port80 LED IPMC RS232 COM_IPMC KCS LPC 82599 Niantic P20 P21 P22 P23 P24 CLK INTERRUPT 82572 82576 Kawela 1000Base BX SMB Serial over LAN Pass Through XF 2x 10GBase BX4 2x 1000B...

Page 142: ...l Advanced Technologies Execute Disable Bit Intel 64 Technology Enhanced Intel SpeedStep Technology Intel Virtualization Technology Intel VT and Simultaneous Multi Threading SMT 5 3 Memory The Xeon CPU features an integrated memory controller The memory controller provides three memory channels that allow flexible memory configurations DDR3 DIMM technology is exclusively supported Different types ...

Page 143: ... x4 PCIe lanes routed to the Zone 3 connector The chipset is connected to the ICH10R I O Controller via the Enterprise Southbridge Interface ESI 5 5 I O Controller The ICH10R provides extensive I O interface support and the BOOT path to SPI Boot Flash devices for the processor ICH10R is connected to the system through the Enterprise Southbridge Interface ESI of the Xeon 5520 chipset The following ...

Page 144: ...ces If booting BIOS from primary flash SPI0 fails a hardware mechanism automatically changes the flash device select logic to boot from the recovery flash SPI1 The image that the processor will boot from after next reset is determined by the IPMC It can be selected via dedicated IPMI OEM command 5 7 Ethernet Ports The blade utilizes various Ethernet controllers that serve the ATCA Base I F Fabric ...

Page 145: ...d disk located in a logically paired ATCA slot 5 9 Embedded Flash Disk The ATCA 7365 CE blade by default provides an onboard USB Flash module 4GB solid state disk The disk can keep data application SW and OS boot images Booting from the device is supported The flash disk controller provides a wear leveling algorithm to improve the longevity of the flash device 5 9 1 SATA Embedded Flash Solid State...

Page 146: ...ing either IPMB or KCS interface The IPMC supports the initiation of a graceful shutdown of the host CPU The IPMC can force the CPU to reset It also controls the power and reset of the payload As part of the power control logic circuitry is provided that controls the correct power up and power down sequencing of all payload specific power domains to prevent latch up and damage of devices The IPMC ...

Page 147: ...al console the IPMC serial console is also available on the faceplate serial connector It can be selected via specific IPMI OEM command 5 13 Serial over LAN Serial Over LAN SOL enables suitably designed blades and servers to transparently redirect a serial character stream of a baseboard UART to from a remote client via LAN over RMCP sessions This enables users at remote consoles to access the ser...

Page 148: ... Front Board Faceplate The blade s faceplate provides the following interfaces and control elements Two USB 2 0 ports Serial console port to connect to either payload or IPMC serial I F Out of Service In Service Attention and Hot Swap LEDs One 1000Base T Ethernet port Recessed reset button The blade design provides the possibility to cover unused faceplate elements like LEDs or push button behind ...

Page 149: ...gmented Table 5 2 SMBus Devices Device Name Device Type Address SPD EEPROM 24C02 1010 000x b A0 SPD EEPROM 24C02 1010 001x b A2 SPD EEPROM 24C02 1010 010x b A4 SPD EEPROM 24C02 1010 011x b A6 SPD EEPROM 24C02 1010 100x b A8 SPD EEPROM 24C02 1010 101x b AA SPD EEPROM 24C02 1010 000x b A0 SPD EEPROM 24C02 1010 001x b A2 SPD EEPROM 24C02 1010 010x b A4 SPD EEPROM 24C02 1010 011x b A6 SPD EEPROM 24C02...

Page 150: ...city This provides 300 hours of RTC SRAM backup The default battery is an external 3V lithium battery with a capacity of 200mAh which provides 3 years of backup 5 19 VGA Module The VGA 7360 module is based on XGI Volari Z11M graphics controller and delivers the following features on a standard DSUB 15 pin analog VGA graphics connector at the faceplate High Performance 2D Accelerator 8 MB Integrate...

Page 151: ...e figure below shows the front and back views of the VGA 7360 module 5 19 1 2D Graphics Engine TheVolariZ11Mgraphicscontrollerincorporatesapowerful64 bitgraphicsenginetoenhance the performance of 2D operations The capabilities of the graphics engine include but are not limited to BitBlt Color Expansion Enhanced Color Expansion Line Drawing Transparent BitBlt and Rectangle Fill Figure 5 2 VGA 7360 ...

Page 152: ...urce data in command queue Bitblt 5 19 2 Supported VGA graphics modes The Volari Z11M provides a 24 bit true color Digital Analog Converter DAC The maximum frequency of the RGB is 230 MHz The maximum resolution the DAC supports is 1600x1200 60Hz video mode 16 bit high color or 1280x1024 85Hz video mode true color 32 bit All Standard VGA modes are supported The color palette with 256 24 bit entries...

Page 153: ...side the ICH10R supports 16 interrupts eight external signal inputs The IO APIC device inside the ICH10R supports 24 interrupt sources In APIC mode the ICH10R supports only Front side bus interrupt delivery not the serial APIC mode ThefollowingfigureandtablessummarizetheinterruptsourcesandmappingsforATCA 7365 APIC mode is configured through BIOS after boot up phase which is done in legacy PIC mode...

Page 154: ...rupts via SERIRQ Table 6 1 APIC Mode Interrupt Mapping IRQ Interrupt Source 0 Cascade from 8259 1 1 2 8254 Counter 0 Timer 0 legacy mode 3 4 5 6 7 8 RTC Timer 1 legacy mode 9 Option for TCI TCO 10 Option for TCI TCO 11 Timer 2 Option for TCI TCO 12 Timer 3 13 FERR logic 14 SATA Primary legacy mode 15 SATA Secondary legacy mode 16 PIRQ A 17 PIRQ B 18 PIRQ C 19 PIRQ D 20 PIRQ E GPIO 21 PIRQ F GPIO 2...

Page 155: ...via SERIRQ PIRQ 6 Floppy IRQ6 via SERIRQ PIRQ 7 Parallel Generic IRQ7 via SERIRQ PIRQ Slave 8 Internal RTC Internal RTC Timer 1 HPET 9 Generic IRQ9 via SERIRQ SCI TCO or PIRQ 10 Generic IRQ10 via SERIRQ SCI TCO or PIRQ 11 Generic IRQ11 via SERIRQ SCI TCO or PIRQ or Timer 2 HPET 12 PS 2 Mouse IRQ11 via SERIRQ SCI TCO or PIRQ or Timer 3 HPET 13 Internal State Machine output based on processor FERR a...

Page 156: ...n 5520 Tylersburg IOH36 D PCI Express ports have the naming convention as shown in Figure IOH36D PCIe Port Mapping on ATCA 7365 on page 156 Table 6 3 PCI Express Port Mapping Port 1 2 3 4 5 6 7 8 9 10 x2 x2 x4 x4 x4 x4 x4 x4 x4 x4 x4 x8 x8 x8 x8 x16 x16 Figure 6 2 IOH36D PCIe Port Mapping on ATCA 7365 ...

Page 157: ...e Default depends on external logic level Table 6 5 Register Access Type Access Description r Read only w Write only r w Read and write w1c Write 1 to clear ignore bit while reading r w1c Read and write 1 to clear write 0 has no effect r w1s Read and write 1 to set write 0 has no effect r w1t Read and write 1 to toggle write 0 has no effect LPC The prefix LPC signals that the access is restricted ...

Page 158: ...and within the address ranges of COM1 or COM2 only when enabled during Super IO configuration are decoded by the LPC core 6 3 1 1 2 LPC Memory Decoding The LPC interface never responds to LPC Memory accesses 6 3 1 1 3 LPC Firmware Decoding The LPC interface never responds to LPC Firmware accesses Table 6 6 LPC I O Register Map Overview Base Address Address Size Address Range Name Description 0x4E ...

Page 159: ...0 The two nibbles of the register are converted to 7 segment codes and are displayed as two hex values by two 7 segment LED Displays The IPMC may read the POST code using the SPI interface with the signal IPMC_SPI_SS_FPGA_ asserted and the SPI address 0x7F Table 6 7 IPMC SPI Register SPI Address Range Address Range Name Description 0x00 0x7F REGISTERS FPGA Registers Table 6 8 POST Code Register LP...

Page 160: ...hen the Super IO is in the Configuration State When the Super IO is not in the Configuration State reads return 0xFF and write data is ignored 6 3 3 1 Entering the Configuration State The device enters the Configuration State by the following contiguous sequence 1 Write 68 to Configuration Index Port 2 Write 08 to Configuration Index Port 6 3 3 2 Configuration Mode The system sets the logical devi...

Page 161: ...failure 6 3 3 3 1 Global Control Configuration Registers The Super IO Global Registers lie in the address range 0x00 0x2F All eight bits of the ADDRESS Port are used for register selection All unimplemented registers and bits ignore writes and return zero when read The INDEX PORT is used to select a configuration register in the chip The DATA PORT is then used to access the selected register These...

Page 162: ... logical device This allows access to the control and configuration registers for each logical device 0 LPC r w Table 6 13 Super IO Device Identification Register Index Address 0x20 Bit Description Default Access 7 0 Device ID 0 LPC r Table 6 14 Super IO Device Revision Register Index Address 0x21 Bit Description Default Access 7 0 Device Revision 0x01 LPC r Table 6 15 Super IO LPC Control Registe...

Page 163: ...register These registers are then accessed through the DATA PORT The Logical Device registers are accessible only when the device is in the Configuration state Table 6 16 Global Super IO SERIRQ and Pre divide Control Register Index Address 0x29 Bit Description Default Access 0 SERIRQ enable 0 disabled Serial interrupts disabled 1 enabled Logical devices participate in interrupt generations 0 LPC r...

Page 164: ...ult Access 0 Logical Device Enable 0 disabled Currently selected device is inactive 1 enabled The currently selected device is enabled 1 LPC r w 7 1 Reserved 0 LPC r Table 6 19 Logical Device Base IO Address MSB Register Index Address 0x60 Bit Description Default Access 7 0 Logical Device Base IO Address MSB 0 LPC r w Table 6 20 Logical Device Base IO Address LSB Register Index Address 0x61 Bit De...

Page 165: ...F COM1 0x2F8 0x2FF COM2 0x2E8 0x2EF COM3 0x3E8 0x3EF COM4 Table 6 22 Logical Device Primary Interrupt Register Index Address 0x70 Bit Description Default Access 3 0 Interrupt level is used for Primary Interrupt 0x0 No interrupt selected 0x1 IRQ1 0x2 IRQ2 0x3 IRQ3 0x4 IRQ4 0x5 IRQ5 0x6 IRQ6 0x7 IRQ7 0x8 IRQ8 0x9 IRQ9 0xA IRQ10 0xB IRQ11 0xC IRQ12 0xD IRQ13 0xE IRQ14 0xF IRQ15 1 LPC r w 7 4 Reserved...

Page 166: ...ng this register to a non zero value and setting any combination of bits 0 4 in the corresponding UART IER and the occurrence of the corresponding UART event that is Modem Status Change Receiver Line Error Condition Transmit Data Request Receiver Data Available or Receiver Time Out and setting the OUT2 bit in the MCR Table 6 23 Logical Device 0x74 Reserved Register Index Address 0x74 Bit Descripti...

Page 167: ...e 6 26 UART Register Overview LPC IO Address DLAB Bit value Description Base 0 Receiver Buffer RBR Read Only Base 0 Transmitter Holding THR Write Only Base 1 0 Interrupt Enable Register IER Base 2 X Interrupt Identification Register IIR Read Only Base 2 X FIFO Control Register FCR Write Only Base 3 X Line Control Register LCR Base 4 X Modem Control Register MCR Base 5 X Line Status Register LSR Re...

Page 168: ...e top of the FIFO 6 3 4 2 2 Transmitter Holding Register THR This register holds the next data byte to be transmitted When the Transmit Shift Register becomes empty the contents of the Transmit Holding Register are loaded into the shift register and the transmit data request TDRQ bit in the Line Status Register is set to one 1 In FIFO mode writing to THR puts data to the top of the FIFO The data a...

Page 169: ...able 6 29 Interrupt Enable Register IER if DLAB 0 LPC IO Address Base 1 Bit Description Default Access 0 Receive data interrupt enable disable 1 receive data interrupt enabled 0 receive data interrupt disabled 0 LPC r w 1 Transmitter holding register empty THRE interrupt enable disable 1 THRE interrupt enabled 0 THRE interrupt disabled 0 LPC r w 2 Receiver line status interrupt enable disable 1 re...

Page 170: ...ger level was reached in non FIFO mode RBR has data 2 Receiver Time out occurred It happens in FIFO mode only when there is data in the receive FIFO but no activity for a time period 3 Transmitter requests data In FIFO mode the transmit FIFO is half or more than half empty in non FIFO mode THR is read already 4 Modem Status One or more of the modem input signals has changed state Table 6 31 Interr...

Page 171: ...le 6 31 Interrupt Identification Register IIR continued LPC IO Address Base 1 Bit Description Default Access Table 6 32 FIFO Control Register FCR LPC IO Address Base 2 Bit Description Default Access 0 FIFO enable disable 1 Transmitter and Receiver FIFO enabled 0 FIFO disabled 0 LPC w 1 Receiver FIFO reset 1 Bytes in receiver FIFO and counter are reset Shift register is not reset bit is self cleari...

Page 172: ... contents of the Line Control Register The read capability simplifies system programming and eliminates the need for separate storage in system memory 7 6 Receiver FIFO interrupt trigger level 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes 0 LPC w Table 6 32 FIFO Control Register FCR continued LPC IO Address Base 2 Bit Description Default Access Table 6 33 Line Control Register LCR LPC IO Address Bas...

Page 173: ...and checked as cleared When bits 3 and 5 are set and bit 4 is cleared the parity bit is transmitted and checked as set If bit 5 is cleared stick parity is disabled 1 Stick parity enabled 0 Stick parity disabled 0 LPC r w 6 Break control bit Bit 6 is set to force a break condition that is a condition where TXD is forced to the spacing cleared state When bit 6 is cleared the break condition is disab...

Page 174: ... RTS output in high state 0 LPC r w 2 User output control signal OUT1 1 OUT1 output in high state 0 OUT1 output in low state Not supported 0 LPC r w 3 User output control signal OUT2 1 OUT2 output in high state 0 OUT2 output in low state Not supported 0 LPC r w 4 Local loop back diagnostic control Whenloopbackisactivated TransmitterTXDissethigh Receiver RXD is disconnected Output of Transmitter Sh...

Page 175: ...just been received In FIFO mode these three bits of status are stored with each received character in the FIFO LSR shows the status bits of the character at the top of the FIFO When the character at the top of the FIFO has errors the LSR error bits are set and are not cleared until software reads LSR even if the character in the FIFO is read and a new character is now at the top of the FIFO 5 Auto...

Page 176: ... Default Access 0 Receiver data ready DR indicator DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO DR is cleared by reading all of the data in the RBR or the FIFO 1 New data received 0 No new data 0 LPC r 1 Overrun error OE indicator When OE is set it indicates that before the character in the RBR was read it was overwritten by the next c...

Page 177: ...ronize after a framing error To accomplish this it is assumed that the framing error is due to the next start bit The ACE samples this start bit twice and then accepts the input data 1 Framing error occurred 0 No framing error 0 LPC r 4 Break Interrupt BI indicator When BI is set it indicates that the received data input was held low for longer than a full word transmission time A full word transm...

Page 178: ...TSR THRE is cleared concurrent with the loading of the THR by the CPU In the FIFO mode THRE is set when the transmit FIFO is empty it is cleared when at least one byte is written to the transmit FIFO 1 THR Transmit FIFO empty 0 THR Transmit FIFO contains data 0 LPC r 6 Transmitter Empty TEMT indicator TEMT bit is set when the THR and the TSR are both empty When either the THRortheTSRcontainsadatac...

Page 179: ...When DDSR is set and the modem status interrupt is enabled a modem status interrupt is generated 1 Change in state of DSR input since last read 0 No change in state of DSR input since last read 0 LPC r w 2 Trailing edge of the ring indicator TERI detector TERI indicates that the RI input to the chip has changed from a low to a high level When TERI is set and the modem status interrupt is enabled a...

Page 180: ... Upon loading either of the Divisor latches a 16 bit baud counter is immediately loaded This prevents long counts on initial load Access to the Divisor latch can be done with a word write 6 Complement of the ring indicator RI input When the ACE is in the diagnostic test mode LOOP MCR4 1 this bit is equal to the MCR bit 2 OUT1 Not supported Ext LPC r 7 Complement of the data carrier detect DCD inpu...

Page 181: ...PC I O Register Map The FPGA registers may be accessed via LPC I O cycles in the I O address range REGISTERS See Table 6 40 For LPC register access use the base address 0x600 and add the Address Offset An LPC I O write access to an address not listed in this table or not marked with an X in the LPC I O column is ignored A corresponding read access delivers always zero Note LPC I O Address 0x600 Ad...

Page 182: ...x x Serial Line Routing Registers 0x06 x x IPMC Power Level Register 0x08 x x SPD PROM MUX Control Register 0x10 x x BIOS Reset Source Register 0x11 x x Reset Mask Register 0x12 x x BIOS IPMC Watch dog timeout Register 0x13 x BIOS Push Button Enable Register 0x14 x x OS Reset Source Register 0x15 x x OS IPMC Watch dog timeout Register 0x16 x IPMC Watch dog timeout Register 0x17 x IPMC Reset Source...

Page 183: ... 0x4B x IPMC GPIO Register 0x50 x x LED Status and Control Register 0x58 x x NMI Status and Control Register 0x60 0x66 x Telecom Clocking Registers 0x6F x x Miscellaneous Status Control Register 0x7D x x LPC Scratch Register 0x7E x x IPMC Scratch Register 0x7F x x POST codes from host 1 For LPC I O accesses add the LPC I O Base Address 0x600 Table 6 40 FPGA Register Map Overview continued Address ...

Page 184: ...e corresponding port to serial IPMC interface in case of SOL Table 6 42 Version Register Address Offset 0x01 Bit Description Default Access 7 0 Specifies FPGA version 1 Initial Value r BIOS should never set both status bits Table 6 43 Serial Redirection Control Register Address Offset 0x03 Bit Description Default Access 0 COM1 used for serial redirection 0 COM1 not used for serial redirection 1 CO...

Page 185: ...ial port 2 COM2 to the IPMC When both control bits are enabled bit 1 is ignored Table 6 44 Serial over LAN Control Register Address Offset 0x04 Bit Description Default Access 0 SOL over COM1 enable 0 disabled 1 enabled COM1 is forwarded to IPMC PWR_GOOD 0 LPC r w IPMC r 1 SOL over COM2 enable 0 disabled 1 enabled COM2 is forwarded to IPMC PWR_GOOD 0 LPC r w IPMC r 7 2 Reserved 0 r ...

Page 186: ...EL_SERIAL 1 0 which are controlled by switches SW2 2 and SW2 1 Switch setting may be overwritten by IPMC Software 00 COM1 to Faceplate and COM2 to RTM 01 COM1 to RTM and COM2 to Faceplate 10 Reserved 11 Reserved Ext SW2 21 SW2 1 00 OFF OFF 01 OFF ON 10 ON OFF 11 ON ON 1 The Signal SEL_SERIAL 1 is reserved The switch SW2 2 should always be OFF and IPMC should not overwrite the default value r 7 2 R...

Page 187: ... is driven high Ext SMBUS_MUX1_IN LPC r IPMC r w 6 BIOS_POST_CMPLT_OUT 3 0 BIOS_POST_CMPLT_IN is driven low 1 BIOS_POST_CMPLT_IN is driven high Ext BIOS_POST_CMPLT_IN LPC r IPMC r w 7 SPD PROM MUX locked by BIOS 1 The output signals XXX_OUT are directly controlled by the corresponding input signals XXX_IN 0 The output signals XXX_OUT are controlled by the corresponding bits 4 to 6 0 LPC r w IPMC r...

Page 188: ...ctive at the same time OS should never write to this register Table 6 48 BIOS Reset Source Register Address Offset 0x10 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 LPC r w1c IPMC r 1 XDP0_BRD_PWROK CPU Debugger System reset request 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 2 PB_RST_ face plate push button reset 1 Reset occurred PWR_GOOD 0 LPC r w...

Page 189: ...catesthattheassociatedresetisenabled Azeroindicates that the associated reset source is masked 7 IPMC_RST_ REQ_ Payload Reset from IPMC 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r Table 6 48 BIOS Reset Source Register continued Address Offset 0x10 Bit Description Default Access Table 6 49 Reset Mask Register Address Offset 0x11 Bit Description Default Access 0 Reserved PWR_GOOD 1 r 1 Spare switch...

Page 190: ...on Enable Register The BIOS needs to write to this register to enable the Front Panel push button reset the RTM push button reset and the IPMC reset OS should never write to this register Table 6 50 BIOS IPMC Watchdog Timeout Register Address Offset 0x12 Bit Description Default Access 0 BIOS IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred PWR_GOOD 0 LPC r w1c IPMC r 1 BIOS IPMC Pre Timeout ...

Page 191: ... two reset sources go active at the same time Table 6 51 BIOS Push Button Enable Register Address Offset 0x13 Bit Description Default Access 7 0 BIOS Push Button Enable Register LPC w BIOS should never write to this register Table 6 52 Reset Source Register Address Offset 0x14 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 LPC r w1c IPMC r 1 XDP0_BRD_P...

Page 192: ..._ CPU Debugger reset 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r 7 IPMC_RST_ REQ_ Payload Reset from IPMC 1 Reset occurred PWR_GOOD 0 LPC r w1c IPMC r Table 6 52 Reset Source Register continued Address Offset 0x14 Bit Description Default Access BIOS should never write to this register Table 6 53 OS IPMC Watchdog Timeout Register Address Offset 0x15 Bit Description Default Access 0 OS IPMC Watchdo...

Page 193: ...S IPMC Watchdog Timeout Register and Table 6 53 OS IPMC Watchdog Timeout Register are set IPMC needs to clear the IPMC watchdog timeout bit to arm IPMC watchdog timeout event recognition Table 6 54 IPMC Watchdog Timeout Register Address Offset 0x16 Bit Description Default Access 0 IPMC Watchdog Timeout 0 No IPMC Watchdog Timeout 1 IPMC Watchdog Timeout occurred PWR_GOOD 0 IPMC r w 1 IPMC Pre Timeo...

Page 194: ...e same time Table 6 55 IPMC Reset Source Register Address Offset 0x17 Bit Description Default Access 0 PWR_GOOD Payload Power on reset 1 Reset occurred PWR_GOOD 1 IPMC r w1c 1 XDP0_BRD_PWROK CPU Debugger System reset request 1 Reset occurred PWR_GOOD 0 IPMC r w1c 2 PB_RST_ face plate push button reset 1 Reset occurred PWR_GOOD 0 IPMC r w1c 3 XDP1_DBRST_ CPU Debugger reset 1 Reset occurred PWR_GOOD...

Page 195: ...ction The write access terminates when SPI transaction has finished A write access to the RTM SPI Address Command Register with the Command Bit 0 Write starts a SPI write transaction The value of the RTM SPI Write Register is written to the SPI device At the moment there is no ARTM with an SPI interface defined Table 6 56 RTM SPI Address Command Register Address Offset 0x18 Bit Description Default...

Page 196: ...upt Status Register The RTM Interrupt Status Register will be located in the RTM SPI address space The host can access the RTM register using the RTM SPI Master Interface No RTM interrupt sources are defined yet 6 4 12 2 External Interrupt Status Register The following table shows the External Interrupt Status Register information Table 6 58 RTM SPI Read Register Address Offset 0x19 Bit Descriptio...

Page 197: ...MISO is low One or more RTM interrupt sources are active When RTM SPI Master face is active the current level is latched Ext LPC r 1 When an interrupt is active the corresponding status bit is read 1 Table 6 59 External Interrupt Status Register continued Address Offset 0x20 Bit Signal1 Description Default Access Table 6 60 Processor Hot Status Control Register Address Offset 0x21 Bit Signal Descr...

Page 198: ...ll interrupt sources need to be of type level active low Each Interrupt source has an Interrupt Mask and Map Register Table 6 61 Telecom Status Control Register Address Offset 0x22 Bit Signal Description Default Access 0 CH1_CLK1A_I N Clock CLK1A of Chassis 1 has changed state from static to toggle or toggle to static 0 LPC r w1c 1 CH1_CLK1B_I N Clock CLK1A of Chassis 1 has changed state from stat...

Page 199: ...x26 THERM_SEN1 IRQ request from 82599 Thermsen1 0x27 THERM_ALERT_ IRQ request from IOH Thermo sensor 0x28 APB_ALARM A 48V input alarm low voltage etc 0x29 RTM_SPI_MISO RTM interrupt sources 0x2A CPU0_PRCHT_ CPU0 Processor hot interrupt 0x2B CPU1_PRCHT_ CPU1 Processor hot interrupt 0x2C Telecom Status Control Register Active when at least one Status bit bit 0 1 or 2 is set 0x2D Table 6 62 Address M...

Page 200: ...er 8 IRQ7 0x09 Frame number 9 IRQ8 0x0A Frame number 10 IRQ9 0x0B Frame number 11 IRQ1 0x0C Frame number 12 IRQ11 0x0D Frame number 13 IRQ12 0x0E Frame number 14 IRQ13 0x0F Frame number 15 IRQ14 0x10 Frame number 16 IRQ15 0x11 Frame number 17 IOCHK_ 0x12 Frame number 18 INTA_ 0x13 Frame number 19 INTB_ 0x14 Frame number 20 INTC_ 0x15 Frame number 21 INTD_ 0x16 0x1F Frame number 22 31 IRQ Frame Num...

Page 201: ... 0 SW1 1 OFF 1 SW1 1 ON LPC r 1 Recovery Boot SPI Flash Write protection Status See RecoveryBootSPIFlashWriteEnableregister howto disable write protection 0 Recovery Boot SPI Flash is unprotected 1 Recovery Boot SPI Flash is protected Ext BOOT_REC_WP_2 0 SW1 2 OFF 1 SW1 2 ON LPC r 3 2 Reserved 0 LPC r 4 TSOP or PLCC Boot select Signal BOOT_TSOP 0 TSOP selected 1 PLCC selected Ext 0 SW1 3 OFF 1 SW1...

Page 202: ... default is latched from SW1 2 when ICH_PLTRST_ is deasserted Table 6 65 Default Boot SPI Flash Write Enable Address Offset 0x41 Bit Description Default Access 7 0 Default Boot SPI Flash Write enable disable A write value 0xC3 enables the Boot Block All other values disable the Boot Block LPC w Table 6 66 Recovery Boot SPI Flash Write Enable Address Offset 0x42 Bit Description Default Access 7 0 R...

Page 203: ...0 OFF Normal BIOS execution Default 0 OFF 1 ON BIOS Crisis recovery Ext 1 SW4 4 ON 0 SW4 4 OF r 1 ON 0 OFF Load BIOS defaults 1 ON 1 ON Port 80 codes to COM1 7 2 Reserved 0 r Table 6 67 BIOS Boot Mode Register continued Address Offset 0x43 Bit Description Default Access Table 6 68 SFMEM Module Configuration Register Address Offset 0x45 Bit Description Default Access 3 0 Control output signals SFME...

Page 204: ... driven low 1 UC1_EQ_TX is tri state 0 LPC r w IPMC r 2 Control output Signal UC2_EQ_RX 0 UC2_EQ_RX is driven low 1 UC2_EQ_RX is tri state 0 LPC r w IPMC r 3 Control output Signal UC2_EQ_TX 0 UC2_EQ_TX is driven low 1 UC2_EQ_TX is tri state 0 LPC r w IPMC r 4 Control output Signal UC3_EQ_RX 0 UC3_EQ_RX is driven low 1 UC3_EQ_RX is tri state 0 LPC r w IPMC r 5 Control output Signal UC3_EQ_TX 0 UC3_...

Page 205: ... 6 IPMC_FAB2_10G_SEL_ Ext LPC r 7 Reserved 0 r Table 6 71 IPMC E Keying Control Register Address Offset 0x4A Bit Description Default Access 0 Shut off the Intel82567 Faceplate GB Eth PHY 0 FP_LAN_DISABLE_ driven low Disabled 1 FP_LAN_DISABLE_ driven high Enabled 1 LPC r w IPMC r w 1 Shut off the Intel8257x BASE Eth Controller 0 BASEIF_DEV_OFF_ driven low Device is OFF 1 BASEIF_DEV_OFF_ driven high...

Page 206: ...high Enabled 1 LPC r w IPMC r w 6 Enable Disable Update Channel ATCA Zone2 Port0 0 UPDCIF_LAN_DIS_ driven low Disabled 1 UPDCIF_LAN_DIS_ driven high Enabled 1 LPC r w IPMC r w 7 Disable Enable USB Port 8 to RTM 0 RTMUSB_ENABLE_ driven low Enabled 1 RTMUSB_ENABLE_ driven high Disabled PWR_GOOD 1 LPC r w IPMC r w Table 6 71 IPMC E Keying Control Register continued Address Offset 0x4A Bit Description...

Page 207: ...riven high 1 LED_GREEN_ is driven low 0 LPC r w IPMC r 1 Control red LED output Signal LED_RED_ 0 LED_RED_ is driven high 1 LED_RED_ is driven low 0 LPC r w IPMC r 2 Control user LED output Signal LED_USER1_ 0 LED_USER1_ is driven high 1 LED_USER1 is driven low 0 LPC r w IPMC r 3 Control user LED output Signal LED_USER2_ 0 LED_USER2_ is driven high 1 LED_USER2 is driven low 0 LPC r w IPMC r 5 4 Re...

Page 208: ...e 6 74 NMI Status and Control Register Address Offset 0x58 Bit Description Default Access 0 Diagnostic NMI Status 0 LPC r w1c IPMC r w 1 Diagnostic NMI Status 0 LPC r IPMC r w 2 Watchdog NMI Status 0 LPC r w1c IPMC r w 3 Watchdog NMI Status 0 LPC r IPMC r w 7 4 Reserved 0 r Table 6 75 Telecom Backplane Clocking Status Register Address Offset 0x66 Bit Description Default Access 0 0 CH1_CLK1A_INisst...

Page 209: ...the result is always 0xFFFF 7 2 Reserved 0 r Table 6 76 Telecom Backplane Clocking Latch Register Address Offset 0x67 Bit Description Default Access 7 0 Latch clock period measurements for CH1_CLK1A and CH1_CLK1B Write data is discarded LPC w Table 6 77 Telecom CH1_CLK1A clock period MSB Register Address Offset 0x61 Bit Description Default Access 7 0 MSB of CH1_CLK1A clock period PWR_GOOD 0xFF LPC...

Page 210: ...disabled when loaded with 0 MSB and LSB Timer registers are 0 The Telecom Timer can be programmed from 1 to 65535 which allows timeout values from 125 micro seconds to 8 191875 sec based on an 8kHz input clock When a timeout occurs the timer is 0 the timeout bit is set See Table 6 61 Telecom Status Control Register The Telecom Timer is reloaded with the timer start value stored in Telecom Timer LS...

Page 211: ...ellaneous Status Control Registers Table 6 81 Telecom Timer MSB Register Address Offset 0x65 Bit Description Default Access 7 0 MSB of Telecom Timer start value PWR_GOOD 0 LPC r w Table 6 82 Telecom Timer LSB Register Address Offset 0x64 Bit Description Default Access 7 0 LSB of Telecom Timer start value PWR_GOOD 0 LPC r w Table 6 83 CPLD Version and Spare Signal Status Register Address Offset 0x6...

Page 212: ...able provides information about Scratch Registers Table 6 84 LPC Scratch Register Address Offset 0x45 Bit Description Default Access 7 0 LPC Scratch bits PWR_GOOD 0 LPC r w IPMC r Table 6 85 IPMC Scratch Register Address Offset 0x45 Bit Description Default Access 7 0 IPMC Scratch bits PWR_GOOD 0 LPC r w IPMC r ...

Page 213: ...e sideband interface of the Intel 82576 in pass through mode is used to transmit receive its terminal characters via the base interface Only a payload baud rate of 9600 baud is supported You can configure the SOL parameters via standard IPMI commands or via an open source tool called ipmitool 7 2 Installing the ipmitool You can download the open source ipmitool from http ipmitool sourceforge net a...

Page 214: ... SOL Parameters You can configure the following SOL parameters You can use standard IPMI commands or the ipmitool to modify the parameters 7 3 1 Using Standard IPMI Commands This example shows how to setup the SOL configuration parameter with standard IPMI commands Ipmicmd is used on the local IPMC and the IP is configured Table 7 1 SOL Parameters Parameter Description Set LAN Configuration Parame...

Page 215: ...s Commit ipmicmd k f 0 c 1 5 0 2 smi 0 7 3 2 Using ipmitool The example below shows how to setup a LAN configuration parameter for a potential SOL session with ipmitool for Base Ethernet Channel 1 channel 5 n0s70 ipmitool lan set 5 ipaddr 172 16 0 221 Setting LAN IP Address to 172 16 0 221 n0s70 The following example shows how to query the LAN parameters that are currently in use for a potential S...

Page 216: ...Gateway IP 172 16 0 1 Default Gateway MAC 00 00 00 00 00 00 RMCP Cipher Suites 1 2 3 3 Cipher Suite Priv Max Not Available root localhost ipmitool lan print 6 Set in Progress Set Complete Auth Type Support Auth Type Enable Callback User Operator Admin OEM IP Address Source Unspecified IP Address 172 17 1 220 Subnet Mask 255 255 0 0 MAC Address 00 00 00 00 00 00 Default Gateway IP 172 17 0 1 ...

Page 217: ...ts detailed above are fulfilled 2 Compile and install the ipmitool on your target which is destined for opening the SOL session on the ATCA 7365 CE For details refer to Installing the ipmitool on page 213 3 Apply an IP address to the ATCA 7365 CE SOL interface for details refer to Configuring SOL Parameters on page 214 4 If necessary change user and password Default user is soluser and password is...

Page 218: ...ATCA 7365 SOL interface ipmitool C 1 I lanplus H 172 16 0 221 U soluser P solpasswd k gkey sol activate For details on the command parameters refer to the ipmitool documentation available on http ipmitool sourceforge net To access BIOS setup screen it is necessary to reset the payload SOL session is only available if the payload is powered on and initialized by the BIOS ...

Page 219: ...s providing a system interface Table 8 1 Supported Global IPMI Commands Command NetFn Request Response CMD Comments Get Device ID 0x06 0x07 0x01 Cold Reset 0x06 0x07 0x02 Warm Reset 0x06 0x07 0x03 Get Self Test Results 0x06 0x07 0x04 Get Device GUID 0x06 0x07 0x08 Master Write Read 0x06 0x07 0x52 Only for accessing private I2C buses Table 8 2 Supported System Interface Commands Command NetFn Reque...

Page 220: ... 0x07 0x42 Set User Access 0x06 0x07 0x43 Get User Access 0x06 0x07 0x44 Set User Name 0x06 0x07 0x45 Get User Name 0x06 0x07 0x46 Set User Password 0x06 0x07 0x47 Set User Payload Access 0x06 0x07 0x4C Get User Payload Access 0x06 0x07 0x4D Set Channel Security Keys 0x06 0x07 0x5C Table 8 2 Supported System Interface Commands continued Command NetFn Request Response CMD Table 8 3 Supported Watchd...

Page 221: ...ormation Table 8 4 Supported SEL Device Commands Command NetFn Request Response CMD Get SEL Info 0x0A 0x0B 0x40 Reserve SEL 0x0A 0x0B 0x42 Get SEL Entry 0x0A 0x0B 0x43 Add SEL Entry 0x0A 0x0B 0x44 Clear SEL 0x0A 0x0B 0x47 Get SEL Time 0x0A 0x0B 0x48 Set SEL Time 0x0A 0x0B 0x49 Table 8 5 Supported FRU Inventory Commands Command NetFn Request Response CMD Get FRU Inventory Area Info 0x0A 0x0B 0x10 R...

Page 222: ... 0x05 0x23 Set Sensor Hysteresis 0x04 0x05 0x24 Get Sensor Hysteresis 0x04 0x05 0x25 Set Sensor Threshold 0x04 0x05 0x26 Most of the threshold based sensors have fixed thresholds Before using this command check whether threshold setting is supported by using the Get Device SDR command Get Sensor Threshold 0x04 0x05 0x27 Set Sensor Event Enable 0x04 0x05 0x28 Get Sensor Event Enable 0x04 0x05 0x29 ...

Page 223: ...OEM specific which can be used for different purposes When using the Get Set System Boot Options commands except for parameter 100 use the response request data fields with the Set Selector and the Block Selector set to 0x00 When using the Get Set System Boot Option for the parameter 100 the Set Selector and the Block Selector have a specific meaning Details are given in System Boot Options Parame...

Page 224: ...1 FPGA configuration stream load 0 Load configuration stream from default boot flash 1 Load configuration stream from backup boot flash Note The new FPGA configuration stream is loaded into the FPGA at the next power up of the payload Bit 0 Default backup boot flash selection 0 Boot from default boot flash 1 Boot from backup boot flash Note The newly selected boot flash is connected to the payload...

Page 225: ...a Byte Description 1 IPMC POST Type Data 1 Set Selector This is the processor ID for which the boot option has to be set 2 Data 2 IPMC POST Type Selector This parameter is used to specify the IPMC POST Type that the IPMC will execute 0x00 Short POST 0x01 Long POST 0x02 to 0xFF Not used The System Boot Options parameter 97 is non volatile During blade production its data is initialized to 0xFF and ...

Page 226: ...tes the boot process accordingly The boot parameters in the IPMC storage area have higher priority than the same boot options which may be configured in the firmware itself for example using the setup menu The storage area is divided into two parts the default area and the user area The user area can be read and written by an IPMI user and by default is the area which the boot firmware reads out a...

Page 227: ...n setting or reading the System Boot Options parameter 100 On some blades with particular firmware types changing a boot parameter in the firmware setup menu changes the boot parameter in the user area as well if the same parameter is defined both in the user area and the set up menu Details are given below Figure 8 1 System Boot Options Parameter 100 Information Flow Overview Table 8 12 System Bo...

Page 228: ... checksum over the boot parameters data section LSB first For backward compatibility reasons the checksums 0x0000 and 0xFFFF are accepted as valid They indicate that no checksum has been calculated and stored Table 8 13 System Boot Options Parameter 100 SET Command Usage Byte Description Request Data 1 Bit 7 when set to 1 the storage area on the IPMC is locked i e no other software can access it T...

Page 229: ...ons Parameter 100 GET Command Usage Byte Description Request Data 1 Bit 7 reserved Set to 0 Bits 6 0 must contain the value 100 indicating this OEM system boot option 2 Set Selector 0 User area 1 Default area 3 Block Selector Zero based index of the 16 byte block which you want to read from Index 0 refers to the first block of 16 bytes which includes the first two bytes which indicate the boot par...

Page 230: ...the number of previously performed successful read accesses This is supported by HPI for details refer to the System Management Interface Based on HPI B User s Guide related to your system environment When used in the System Boot Options parameter 100 the boot parameters and their values are case sensitive All boot options listed in the following table are set by the BIOS setup menu and can be con...

Page 231: ...e Gen1 on PCIe x4x4x8 frontnet_boot Boot from Front Panel Network off on basenet_boot Boot from Base Network off on artm_net_boot Boot from ARTM Network off on artm_sas_boot Boot from ARTM SAS device off on artm_fc_boot Boot from ARTM FC device off on boot_order Boot priority order device1 devcice2 device8 See boot_order Devices uefi UEFI Media path Format NAME DevicePath This parameter contains a...

Page 232: ... fabricnet0 Fabric Ethernet Interface Channel 1 fabricnet1 Fabric Ethernet Interface Channel 2 usb1 USB frontpanel 1 usb2 USB frontpanel 2 usbonboard USB onboard HDD usbartm USB artm usbkey USB key usbcdrom USB cdrom usbhdd USB hdd usbfdd USB floppy disk efishell Built in UEFI shell uefi UEFI Media path place holder which points to the corresponding uefi parameter Up to 10 boot devices are support...

Page 233: ...D Set LAN Configuration Parameters 0x0C 0x0D 0x01 Get LAN Configuration Parameters 0x0C 0x0D 0x02 Set SOL Configuration Parameters 0x0C 0x0D 0x21 Get SOL Configuration Parameters 0x0C 0x0D 0x22 Table 8 18 Supported PICMG 3 0 Commands Command NetFn Request Response CMD Comments Get PICMG Properties 0x2C 0x2D 0x00 Get Address Info 0x2C 0x2D 0x01 FRU Control 0x2C 0x2D 0x04 The blade supports the cold...

Page 234: ...nk Info 0x2C 0x2D 0x18 Set AMC Port State 0x2C 0x2D 0x19 Get AMC Port State 0x2C 0x2D 0x1A Get FRU Control Capabilities 0x2C 0x2D 0x1E Get target upgrade capabilities 0x2C 0x2D 0x2E Get component properties 0x2C 0x2D 0x2F Abort firmware upgrade 0x2C 0x2D 0x30 Initiate upgrade action 0x2C 0x2D 0x31 Upload firmware block 0x2C 0x2D 0x32 Finish firmware upload 0x2C 0x2D 0x33 Get upgrade status 0x2C 0x...

Page 235: ... or PICMG 3 0 specification but are introduced by Artesyn serial output commands The firmware upgrade commands supported by the blade are implemented according to the PICMG HPM 1 Revision 1 0 specification The boot block can be updated with PICMG HPM 1 specific commands Before sending any of these commands the shelf management software must check whetherthereceivingIPMIcontrollersupportsArtesynspe...

Page 236: ...5 See Set Serial Output Command on page 236 Get Serial Output 0x2E 0x2F 0x16 See Get Serial Output Command on page 237 Table 8 20 Request Data of Set Serial Output Command Byte Data Field 1 LSB of Artesyn Embedded Technologies IANA Enterprise number A value of 0xCD has to be used 2 Second byte of Artesyn Embedded Technologies IANA Enterprise number A value of 0x65 has to be used 3 MSB of Artesyn E...

Page 237: ...h serial output source goes to a particular serial port connector 6 Serial output selector 0 BIOS 2 IPMC debug console All other values are reserved Table 8 20 Request Data of Set Serial Output Command continued Byte Data Field Table 8 21 Response Data of Set Serial Output Command Byte Data Field 1 Completion code 2 LSB of Artesyn IANA Enterprise number 3 Second byte of Artesyn IANA Enterprise num...

Page 238: ...econd byte of Artesyn IANA Enterprise number A value of 0x65 has to be used 3 MSB of Artesyn IANA Enterprise number A value of 0x00 has to be used 4 Serial connector type 0 Faceplate connector 1 Backplane connector All other values are reserved Note Only the faceplate connector is supported No connector on the RTM available 5 Serial connector instance number A sequential number that starts from 0 ...

Page 239: ...ardware Address Table 8 32 on page 247 0x2E 0x2F 0x06 Get Handle Switch Table 8 33 on page 248 0x2E 0x2F 0x07 Set Handle Switch Table 8 34 on page 249 0x2E 0x2F 0x08 Get Payload Communication Time Out Table 8 35 on page 249 0x2E 0x2F 0x09 Set Payload Communication Time Out Table 8 36 on page 250 0x2E 0x2F 0x0A Enable Payload Control Table 8 37 on page 251 0x2E 0x2F 0x0B Disable Payload Control Tab...

Page 240: ...nded for debugging purposes and or operation in a non ATCA environment In standalone mode the carrier IPMC automatically activates and deactivates the on carrier payload and modules whenever it does not violate any carrier limitations Manual standalone Manual standalone mode is equivalent to standalone mode with only one exception carrier IPMC control over the on carrier payload is automatically d...

Page 241: ...a threshold crossing Bits 2 1 Mode The current IPMC modes are defined as 0 Normal 1 Standalone for a description refer to Table 8 25 2 Manual Standalone for a description refer to Table 8 25 Bit 0 Control If set to 0 the IPMC control over the payload is disabled 6 Bits 4 7 Metallic Bus 2 Events These bits indicate pending Metallic Bus 2 requests arrived from the shelf manager 0 Metallic Bus 2 Quer...

Page 242: ...ts 0 3 Clock Bus 1 Events These bits indicate pending Clock Bus 1 requests arrived from the shelf manager 0 Clock Bus 1 Query 1 Clock Bus 1 Release 2 Clock Bus 1 Force 3 Clock Bus 1 Free 8 Bits 4 7 Reserved Bits 0 3 Clock Bus 3 Events These bits indicate pending Clock Bus 3 requests arrived from the shelf manager 0 Clock Bus 3 Query 1 Clock Bus 3 Release 2 Clock Bus 3 Force 3 Clock Bus 3 Free Tabl...

Page 243: ...rprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud R...

Page 244: ...rprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Interface ID 0 Serial Debug Interface 5 Bit 7 Echo On If this bit is set the IPMC enables echo for the given serial interface Bits 6 4 Reserved Bits 3 0 Baud Rate ID The baud rate ID defines the interface baud rate as follows 0 9600 bps 1 19200 bps 2 38400 bps 3 57600 bps unsupported 4 115200 bps unsupport...

Page 245: ...nable If set to 1 the IPMC provides a trace of IPMB L messages that are arriving to going from the IPMC via IPMB L Bit 6 n a Bit 5 KCS Dump Enable If set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Aler...

Page 246: ...f set to 1 the IPMC provides a trace of KCS messages that are arriving to going from the IPMC via KCS Bit 4 IPMB Dump Enable If set to 1 the IPMC provides a trace of IPMB messages that are arriving to going from the IPMC via IPMB O Bit 3 n a Bit 2 Alert Logging Enable If set to 1 the IPMC outputs important alert messages onto the serial debug interface Bit 1 Low level Error Logging Enable If set t...

Page 247: ...ta 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 5 Hardware Address Table 8 32 Set Hardware Address Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterpr...

Page 248: ... 2 0A byte 3 40 byte 4 00 Table 8 32 Set Hardware Address Command Description continued Type Byte Data Field Table 8 33 Get Handle Switch Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 FRU ID specify as 0 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x0...

Page 249: ...1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 FRU ID specify as 0 5 Handle Switch Status 0x00 The handle switch is open 0x01 The handle switch is closed 0x02 The handle switch state is read from hardware Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2...

Page 250: ...ut may vary from 0 1 to 25 5 seconds Table 8 35 Get Payload Communication Time Out Command Description continued Type Byte Data Field Table 8 36 Set Payload Communication Time Out Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Payload Time out Payload communication time out ...

Page 251: ...ata 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 38 Disable Payload Control Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A...

Page 252: ...LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Reset Type Code 0x00 Cold IPMC reset to the current mode 0x01 Cold IPMC reset to the Normal mode 0x02 Cold IPMC reset to the Standalone mode for more details refer to Table 8 25 0x03 ColdIPMCresettotheManualStandalonemode for more details refer to Table 8 25 0x04 Reset the IPMC and enter Upgrade mode Response Data 1 Completion Code 2 4 PPS IANA Privat...

Page 253: ...ad upon receiving the Graceful Reset command or time out If the IPMC participation is necessary the payload must request the IPMC to perform a payload reset The Graceful Reset command is also used to notify the IPMC about the completion of the payload shutdown sequence 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 40 Han...

Page 254: ...he payload Interface to notify the IPMC that the payload shutdown is complete To avoid deadlocks that may occur if the payload software does not respond the IPMC provides a special time out for the payload shutdown sequence If the payload does not send the Graceful Reset command within a definite period of time the IPMC assumes that the payload shutdown sequence is finished and resets the payload ...

Page 255: ...prise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 5 Time Out measured in hundreds of milliseconds LSB first Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 Table 8 44 Get Module State Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private...

Page 256: ...r is disabled 1 Management power is enabled Bit 3 0 Management power is bad 1 Management power is good Bit 4 0 Payload power is disabled 1 Payload power is enabled Bit 5 0 Payload power is bad 1 Payload power is good Bit 6 0 IPMB L buffer is not attached 1 IPMB L buffer is attached Bit 7 0 IPMB L buffer is not ready 1 IPMB L buffer is ready Table 8 44 Get Module State Command Description continued...

Page 257: ...Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 4 Module Site ID Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Table 8 46 Disable Module Site Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private ...

Page 258: ...ld the carrier SDR repository Table 8 47 Reset Carrier SDR Repository Command Description Type Byte Data Field Request Data 1 3 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 1 0A byte 2 40 byte 3 00 Response Data 1 Completion Code 2 4 PPS IANA Private Enterprise ID 0x00400A 16394 Pigeon Point Systems LSB Byte first byte 2 0A byte 3 40 byte 4 00 ...

Page 259: ...yn Embedded Technologies r Board part number Defined by Artesyn Embedded Technologies r Product info area Product manufacturer ARTESYN r Product name Product name of the specific blade variant r Product serial number Defined by Artesyn Embedded Technologies r Product part number Defined by Artesyn Embedded Technologies r Multi record info area Blade Point To Point Connectivity Record Area This mul...

Page 260: ...cord format version Write as 2h 2 1 Record Length 3 1 Record Checksum zero checksum 4 1 Header Checksum zero checksum 5 1 LSB of Manufacturer ID Write as CDh 6 1 Second Byte of Manufacturer ID Write as 65h 7 1 MSB of Manufacturer ID Write as 00h 8 1 Artesyn Record ID 01h for Artesyn MAC Address Record 9 1 Record Format Version 00h for this specification 10 1 Number of MAC Address Descriptors N 11 ...

Page 261: ...nt to point connectivity record area Table 9 4 Interface Type Assignments Interface Type Description 01h ATCA Base Interface or AMC MicroTCA Common Options Region 02h ATCA Fabric Interface or AMC MicroTCA Fat Pipe Region 03h Front Panel 04h AMC MicroTCA Extended Fat Pipe Region The fibre channel interfaces link type extension 2 described in the point to point connectivity record area are physicall...

Page 262: ... Link Type Link Type Extension Link Descriptor Value 1 0 0 Base Interface 1 0 SET 1 NOT SET 2 NOT SET 3 NOT SET 0x01 0 2 0 0 Base Interface 2 0 SET 1 NOT SET 2 NOT SET 3 NOT SET 0x01 1 3 0 1 Fabric Interface 1 0 SET 1 SET 2 SET 3 SET 0x02 1 4 0 1 Fabric Interface 1 0 SET 1 NOT SET 2 NOT SET 3 NOT SET 0x02 0 5 0 1 Fabric Interface 2 0 SET 1 SET 2 SET 3 SET 0x02 1 6 0 1 Fabric Interface 2 0 SET 1 NO...

Page 263: ...terface 2 0 NOT SET 1 SET 2 NOT SET 3 NOT SET 0xF2 0 10 0 2 Update Channel Interface 2 0 NOT SET 1 NOT SET 2 SET 3 NOT SET 0xF3 0 11 0 2 Update Channel Interface 2 0 NOT SET 1 NOT SET 2 NOT SET 3 SET 0xF4 0 Table 9 5 Contents of the Blade Point to Point Connectivity Record Area continued No Link Grouping ID Interface Channel Number Ports Link Type Link Type Extension Link Descriptor Value ...

Page 264: ...pport No While the blade is powered it supports only one power level Dynamic power configuration No The power level is fixed and does not change Number of power draw levels 2 The amount of possible power levels Early Power Draw Levels Watt Complete early power level including IPMC Steady state Power Draw Levels Watt 2 0 GHz 6x4GB DDR3 RTM 180 220 Watts Max 260 Watts Complete steady power consumpti...

Page 265: ...ystem Boot Initiated 0x14 CPU0 temp Temperature 0x27 CPU1 temp Temperature 0x28 CPU Status Processor 0x26 DDR 1 temp Temperature 0x19 DDR 2 temp Temperature 0x1A DDR 3 temp Temperature 0x1B DDR 4 temp Temperature 0x1C DDR 5 temp Temperature 0x1D DDR 6 temp Temperature 0x1E DDR 7 temp Temperature 0x1F DDR 8 temp Temperature 0x20 DDR 9 temp Temperature 0x21 DDR 10 temp Temperature 0x22 DDR 11 temp T...

Page 266: ...hysical Link 0x03 IPMC POST Management Subsystem Health 0x0F IPMC temp Temperature 0x25 OS Boot OS Boot 0x12 Top Edge Temp Sensor Temperature 0x0E POST code Artesyn specific Discrete Digital 0x17 PWR Entry Temp Temperature 0x2D PWR Entry Status OEM reserved 0x2E Power Good Entity Presence 0x16 Reset Source Artesyn specific Discrete Digital 0x18 VCC CPU0 Voltage 0x0B Version change Version Change 0...

Page 267: ...mation and Sensor Data Records ATCA 7365 CE Installation and Use 6806800L73N 267 The following figure shows the locations of all temperature sensors available on board Figure 9 1 Location of Temperature Sensors ...

Page 268: ...4 M4 0x5 M5 0x6 M6 0x7 M7 Asrt Auto 1 Hotswap_RTM Hot Swap 0xF0 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 7 4 Cause 3 0 Previous State FRU ID 0x0 M0 0x1 M1 0x2 M2 0x3 M3 0x4 M4 0x5 M5 0x6 M6 0x7 M7 Asrt Auto 2 Version change Version Change 0x2B Sensor specific discrete 0x6F 0x7 Change type 0xFF 0x7 Software or F W change successful Asrt Auto 3 IPMB Physical Physical IPMB 0 0xF1...

Page 269: ... lc Asrt Deass Auto 10 1 2V Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 11 VCC CPU0 Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 12 1 5V DDR3 Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 13 Bottom Edge Temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 14 Top Edge Temp Temp 0x01 Th...

Page 270: ...ensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0xFF 0xFF 0x0 A boot completed 0x1 C boot completed 0x2 PXE boot completed 0x3 Diagnostic boot completed 0x4 CD_ROM boot completed 0x5 ROM boot completed 0x6 boot completed Asrt Auto 19 Boot Error Boot Error 0x1E Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0xFF 0xFF 0x0 No Bootable media Asrt Auto Table 9 8 Sensor Data Records continue...

Page 271: ...d Boot 0x4 Cold Boot 0x5 Warm Boot 0x6 Reserved Asrt Auto 22 Power Good Entity Presence 0x25 Sensor specific discrete 0x6F 0x0 0x1 0xFF 0xFF 0x0 Entity Present 0x1 Entity Absent Asrt Auto 23 POST code OEM 0xD2 Sensor specific discrete 0x6F 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x0 No events for this sensor Reading according to EFI BIOS port80 status codes Asrt Auto Table 9 8 Sensor Data Records continue...

Page 272: ...uto 28 DDR 4 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 29 DDR 5 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 30 DDR 6 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 31 DDR 7 temp Temp 0x01 Threshold 0x01 reading threshold unr uc unc Asrt Deass Auto 32 DDR 8 temp Temp 0x01 Threshold 0x01 reading threshold unr...

Page 273: ...d 0x01 reading threshold uc unc Asrt Deass Auto 41 48v A Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 42 48v B Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Auto 43 48v Amps Current 0x03 Threshold 0x01 reading threshold No Thresholds Auto 44 HoldUp Cap Volts Voltage 0x02 Threshold 0x01 reading threshold unr uc lnr lc Asrt Deass Au...

Page 274: ...r specific discrete 0x6F 0x4 0x5 0xFF 0xFF 0x4 PCI PERR 0x5 PCI SERR Asrt Auto 49 Battery Battery 0x29 Sensor specific discrete 0x6F 0x1 0xFF 0xFF 0x1 Battery failed Asrt Auto 50 48V A Supply Power Supply 0x08 Sensor specific discrete 0x6F 0x0 0x1 See IPMI Spec 0xFF 0x0 Presence detected 0x1 Power Supply Failure detected Asrt Deass Auto 51 48V B Supply Power Supply 0x08 Sensor specific discrete 0x...

Page 275: ...ed to use the Pigeon Point System modified Ipmitool 10 1 2 Installing the Ipmitool Install Procedure 1 Get the Pigeon Point System Ipmitool from the package Ipmitool 1 8 9 pps 7 tgz 2 Extract the source code Prompt tar xzvf Ipmitool 1 8 9 pps version tgz 3 Go to the directory where you have extracted the Ipmitool Prompt cd path Ipmitool 1 8 9 pps version 4 Build the Ipmitool Prompt configure make ...

Page 276: ...PM 1 upgrade The images and the Ipmi tool need to be on the payload to be upgraded Example Prompt ipmitool hpm upgrade file 10 1 3 2 IPMB 0 This interface represents the backplane IPMI bus and allows remote firmware upgrade The count of the simultaneous upgrades is limited because of the bus speed Example from shelf manger Prompt ipmitool t 0x92 hpm upgrade file Example with RMCP Prompt ipmitool I...

Page 277: ... of the firmware in the flash depending on the current value of the special partition status byte that is stored in the internal IPMC EEPROM The boot loader can fall back to the backup copy by booting the alternate partition The boot loader manages two firmware partitions the active and backup partition It is responsible for detecting if the active firmware is invalid or has failed If the active f...

Page 278: ...thisdevicemustalsobepossible This leads to the fact that an automatic boot bank switching via the IPMC is not possible which is a requirement for HPM 1 to activate Payload always has access to the active boot bank and the IPMC always has access to the inactive boot bank All HPM 1 commands are directed to the inactive boot bank this includes get component properties The following figure shows the c...

Page 279: ...lation and Use 6806800L73N 279 FPGA and BIOS upgrade may last from fifteen minutes up to two hours The time varies with the selected programming interface A power cycle is required after the BIOS FPGA update Figure 10 2 SPI Bus Connection ...

Page 280: ... img HPM file contains the boot loader and firmware image atca 7360 hpm 1 boot img HPM file contains only the boot loader image atca 7360 hpm 1 ipmc img HPM file contains only the firmware image 9806865F07E_A736BIOS 120 bin hpm HPM file contains the version 1 2 0 BIOS image atca7360_spi_13 bin hpm HPM file contains the version 0 13 FPGA image Ipmitool 1 8 9 pps 7 tgz PPS modified Ipmitool necessar...

Page 281: ...C4465 C2048 C4594 C4595 C4596 C4597 C4599 C4600 C4512 Q38 L78 Q42 C3529 C3534 D54 R1247 C1481 R1219 C4340 C1463 C1453 R1235 R1236 R1238 R1243 R1223 J220 T220 C3026 J117 L20 R2753 R2755 R2770 R2772 R2777 R2779 C4668 C4669 C4670 C4672 C4675 C4678 C4683 C4686 R1240 R2809 R2811 C4682 L49 L51 Q28 R2790 R2810 R2812 P39 Q29 C4730 Q87 C4202 L97 R3499 C3148 R2722 C4326 C4324 C4321 C4320 C2101 R1681 C4297 C...

Page 282: ...Loss If the battery does not provide enough power anymore the RTC is initialized and the data in the NVRAM is lost Therefore replace the battery before seven years of actual battery use have elapsed Data Loss Replacing the battery always results in data loss of the devices which use the battery as power backup Therefore back up affected data before replacing the battery Data Loss If installing ano...

Page 283: ...ttery proceed as follows 1 Remove battery 2 Install the new battery following the positive and negative signs PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder To prevent this damage do not use a screw driver to remove the battery from its holder ...

Page 284: ...Replacing Battery ATCA 7365 CE Installation and Use 6806800L73N 284 ...

Page 285: ...atest copies of our product documentation 1 Go to www artesyn com computing support product technical documentation php 2 Under FILTER OPTIONS click the Document types drop down list box to select the type of document you are looking for 3 In the Search text box type the product name and click GO Table B 1 Artesyn Embedded Technologies Embedded Computing Publications Document Title Publication Num...

Page 286: ...information is subject to change without notice Table B 2 Manufacturer s Documents Company Document Title Intel 6300ESB I O Controller Datasheet 82546EB GB Gigabit Ethernet Controller Documentation 6700PXH 64 bit PCI to PCI bridge Datasheet E7520 Memory Controller Datasheet IPMI V1 5 Specifications Intel XeonTM Processor Technical Documents LSI Logic LSIFC929XL Dual Channel PCI X to Fibre Channel ...

Page 287: ......

Page 288: ...esyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies Inc All other product or service names are the property of their respective owners 2016 Artesyn Embedded Technologies Inc ...

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