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ARTERY AT32F425 Series, Reference Manual

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ARTERY AT32F425 Series Reference Manual Download Page 377

  AT32F425

 

Series  Reference  Manual

 

2022.03.30

 

Page 377 

 

Ver 2.01

 

The INCOMPISOIN interrupt in the  OTGFS_GINTSTS register is a global interrupt. Therefore, when 
more than one synchronous endpoints are in active state, the application must determine which one of 
the synchronous IN endpoints has not yet completed data transfers. 
To achieve this, read the DSTS and DIEPCTLx bits of all synchronous endpoints. If the current endpoing 
has been enabled, and the read value of the SOFFN bit in the OTGFS_DSTS register is equal to the 
target frame number of the endpoint, it indicates that this endpoint has not finished data transfers. The 
application must keep track of nd update the target frame number of the synchronous endpoint. 
If data transfer is not yet complete on an endpoint, then Odd/Even bits have to be toggled.   

Next: 
(1) When the  DPID is set to 1 (an odd frame) in the  OTGFS_DIEPCTLx register, write 1 to the 

SETD0PID bit in the OTGFS_DIEPCTLx register makes it an even frame, then data transmission starts 
when there is an IN token input in the next frame. 

(2) When the DPID is set to 0 in the OTGFS_DIEPCTLx register, write 1 to the SETD1PID bit in the 

OTGFS_DIEPCTLx register makes it an odd frame, then data transmission starts when there is an IN 
token input in the next frame. 

20.5.4.18 

Incomplete synchronous OUT data transfers 

To initialize the controller after power-on reset, the application must perform the steps list in OTGFS 
Initializtion. Before communicating with a host, the controller must follow the steps defined in Endpoint 
Initializtion to initialize endpoints. This section describes the application programming sequence when 
the controller drops synchronous OUT data packets. 

【

Internal data flow

】

 

1. For synchronous OUT endpoints, the XFERC interrupt (in the OTGFS_DOEPINTx register) may not 
always be generated. If the controller drops synchronous OUT data packets, the application may fail to 
detect the XFERC interrupt in the OTGFS_DOEPINTx register. 

 

When the receive FIFO cannot accommodate the complete ISO OUT data packet, the controller 

drops the received ISO OUT data. 

 

When the synchronous OUT data packet is received with CRC errors. 

 

When the synchronous OUT token received by the controller is corrupted. 

 

When the application is very slow in reading the receive FIFO 

2. When the controller detects the end of periodic frames before transfer complete to all synchronous 
OUT  endpoints,  an  interrupt  of  incomplete  synchronous  OUT  data  is  generated,  indicating  that  an 
XFERC interrupt in the OTGFS_DOEPINTx register is not set on at least one of the synchronous OUT 
endpoints. At this point, the endpoint with the incomplete data transfer remains enabled, but no valid 
transfers are in progress on this endpoint.   

【

Application programming sequence

】

 

1.  The  assertion  of  the  incomplete  synchronous  OUT  data  interrupt  indicates  that  at  least  one 
synchronous OUT endpoint has an incomplete data transfer in the current frame. 
2. If this occurs because the synchronous OUT data is not completely read out from the endpoint, the 
application  must  empty  all  synchronous  OUT  data  (data  and  status)  in  the  receive  FIFO  before 
proceeding. 

 

When all data are read from the receive FIFO, the application can detect the XFERC interrupt in 

the OTGFS_DOEPINTx register. In this case, the application must re-enable the endpoint to receive 
the synchronous OUT data in the enxt frame by following the steps listed in “SETUP/Data IN/Status 
OUT” 
3. When it receives an incomplete synchronous OUT data interrupt, the application must read the control 
registers of all synchronous OUT endpoints to determine which one of the endpoints has an incomplete 
data transfer in the current frame. An endpoint transfer is regarded as incomplete if both of the following 
conditions are met: 

 

OTGFS_DOEPCTLx. Even/Odd frame bit= OTGFS_DSTS.SOFFN[0] 

 

OTGFS_DOEPCTLx. Endpoint enable = 0x1 

4.

。

The pervious step must be performed before the SOF interrupt of the GINTSTS register is detected 

to ensure that the current frame number is not changed. 
5.  For  synchronous  OUT  endpoints  with  incomplete  transfers,  the  application  must  drop  the  data  in 
memory, and disable the endpoint through the endpoint disable bit in the OTGFS_DOEPCTLx register. 

Summary of Contents for AT32F425 Series

Page 1: ...ll Up to 55 Fast I O Interfaces All mappable to 16 external interrupt vectors Almost 5 V tolerant Up to 3 Timers TMR 1 x 16 bit 7 channel advanced timer 6 channel PWM output with dead time generator a...

Page 2: ...sh memory size register 38 1 3 2 Device electronic signature 38 2 Memory resources 39 2 1 Internal memory address map 39 2 2 Flash memory 40 2 3 SRAM memory 40 2 4 Peripheral address map 41 3 Power co...

Page 3: ...APB peripheral clock enable register CRM_AHBEN 58 4 3 7 APB2 peripheral clock enable register CRM_AHB2EN 59 4 3 8 APB1 peripheral clock enable register CRM_AHB1EN 60 4 3 9 Battery powered domain contr...

Page 4: ...ADDR 79 5 7 7 User system data register FLASH_USD 79 5 7 8 Erase program protection status register FLASH_EPPS 80 5 7 9 Flash security library status register0 SLIB_STS0 80 5 7 10 Flash security libra...

Page 5: ...RVR x A B C D F 91 6 3 4 GPIO pull up pull down register GPIOx_PULL x A B C D F 91 6 3 5 GPIO input register GPIOx_IDH x A B C D F 92 6 3 6 GPIO output register GPIOx_IDH x A B C D F 92 6 3 7 GPIO set...

Page 6: ...er register EXINT_ SWTRG 101 8 3 6 Interrupt status register EXINT_ INTSTS 101 9 DMA controller DMA 102 9 1 Introduction 102 9 2 Main features 102 9 3 Function overview 102 9 3 1 DMA configuration 102...

Page 7: ...15 11 4 I2C interface 116 11 4 1 I2 C timing control 118 11 4 2 Data transfer management 119 11 4 3 I2C master communication flow 120 11 4 4 I2 C slave communication flow 125 11 4 5 SMBus 129 11 4 6 S...

Page 8: ...DMA transfer introduction 150 12 5 1 Transmission using DMA 150 12 5 2 Reception using DMA 150 12 6 Baud rate generation 151 12 6 1 Introduction 151 12 6 2 Configuration 151 12 7 Transmitter 152 12 7...

Page 9: ...mitter 168 13 2 9 Receiver 168 13 2 10 Motorola mode 169 13 2 11 TI mode 171 13 2 12 Interrupts 172 13 2 13 IO pin control 172 13 2 14 Precautions 173 13 3 I2S functional description 173 13 3 1 I2 S i...

Page 10: ...1 4 2 TMR6 and TMR7 control register2 TMRx_CTRL2 189 14 1 4 3 TMR6 and TMR7 DMA interrupt enable register TMRx_IDEN 189 14 1 4 4 TMR6 and TMR7 interrupt status register TMRx_ISTS 189 14 1 4 5 TMR6 an...

Page 11: ...rol register TMRx_DMACTRL 211 14 2 4 18 TMR2 and TMR3 DMA data register TMRx_DMADT 211 14 3 General purpose timer TMR9 to TMR14 211 14 3 1 TMR13 and TMR14 introduction 211 14 3 2 TMR13 and TMR14 main...

Page 12: ...VT 233 14 4 4 7 TMR15 channel mode register1 TMR15_CM1 233 14 4 4 8 TMR15 Channel control register TMR15_CCTRL 235 14 4 4 9 TMR15 counter value TMR15_CVAL 237 14 4 4 10 TMR15 division value TMR15_DIV...

Page 13: ...and TMR17 break register TMRx_BRK 252 14 5 4 14 TMR16 and TMR17 DMA control register TMRx_DMACTRL 253 14 5 4 15 TMR16 and TMR17 DMA data register TMRx_DMADT 253 14 6 Advanced control timers TMR1 253...

Page 14: ...14 6 4 21 TMR1 channel mode register3 TMR1_ CM3 278 14 6 4 22 TMR1 channel 5 data register TMR1_C5DT 278 15 Window watchdog timer WWDT 279 15 1 WWDT introduction 279 15 2 WWDT main features 279 15 3 W...

Page 15: ...r register ERTC_DIV 294 17 4 6 ERTC wakeup timer register ERTC_WAT 295 17 4 7 ERTC alarm clock A register ERTC_ALA 295 17 4 8 ERTC write protection register ERTC_WP 295 17 4 9 ERTC subsecond register...

Page 16: ...age monitoring 307 18 4 7 Status flag and interrupts 308 18 5 ADC registers 308 18 5 1 ADC status register ADC_STS 308 18 5 2 ADC control register1 ADC_CTRL1 309 18 5 3 ADC control register2 ADC_CTRL2...

Page 17: ...STS 333 19 7 1 4 CAN receive FIFO 0 register CAN_RF0 335 19 7 1 5 CAN receive FIFO 1 register CAN_RF1 336 19 7 1 6 CAN interrupt enable register CAN_INTEN 336 19 7 1 7 CAN error status register CAN_ES...

Page 18: ...pin configuration 344 20 4 OTGFS interrupts 345 20 5 OTGFS functional description 345 20 5 1 OTGFS initialization 345 20 5 2 OTGFS FIFO configuration 346 20 5 2 1 Device mode 346 20 5 2 2 Host mode 34...

Page 19: ...ous IN data transfers 378 20 5 4 20 Periodic IN interrupt and synchronous data transfers 378 20 6 OTGFS control and status registers 380 20 6 1 CSR register map 380 20 6 2 OTGFS register address map 3...

Page 20: ...0 15 where x channel number 400 20 6 4 9 OTGFS host channelx interrupt register OTGFS_HCINTx x 0 15 where x channel number 401 20 6 4 10 OTGFS host channelx interrupt mask register OTGFS_HCINTMSKx x 0...

Page 21: ...FS device IN endpoint x transfer size register OTGFS_DIEPTSIZx x 1 7 where x is endpoint number 415 20 6 5 18 OTGFS device IN endpoint transmit FIFO status register OTGFS_DTXFSTSx x 1 7 where x is end...

Page 22: ...22 Infrared timer IRTMR 424 23 Debug DEBUG 425 23 1 Debug introduction 425 23 2 Debug and Trace 425 23 3 I O pin control 425 23 4 DEGUB registers 425 23 4 1 DEBUG device ID DEBUG_IDCODE 425 23 4 2 DE...

Page 23: ...Figure 6 2 IOMUX structure 86 Figure 8 1 External interrupt Event controller block diagram 99 Figure 9 1 DMA block diagram 102 Figure 9 2 Re arbitrae after request acknowledge 103 Figure 9 3 PWIDTH by...

Page 24: ...LK 172 Figure 13 15 SPI interrupts 172 Figure 13 16 I2S block diagram 173 Figure 13 17 I2S full duplex structure 174 Figure 13 18 I2S slave device transmission 175 Figure 13 19 I2 S slave device recep...

Page 25: ...Overflow event when PRBEN 0 212 Figure 14 35 Overflow event when PRBEN 1 213 Figure 14 36 Input output channel 1 main circuit 213 Figure 14 37 Channel 1 input stage 213 Figure 14 38 Capture compare c...

Page 26: ...56 Figure 14 81 Counter timing with prescaler value changing from 1 to 4 256 Figure 14 82 Overflow event when PRBEN 0 257 Figure 14 83 Overflow event when PRBEN 1 257 Figure 14 84 Counter timing diagr...

Page 27: ...25 Figure 19 9 32 bit identifier list mode 325 Figure 19 10 16 bit identifier mask mode 325 Figure 19 11 16 bit identifier list mode 325 Figure 19 12 Transmit mailbox status 327 Figure 19 13 Receive F...

Page 28: ...ltiplexed function configuration with GPIOD_MUX register 89 Table 6 5 Port E multiplexed function configuration with GPIOE_MUX register 89 Table 6 6 Pins owned by hardware 90 Table 6 7 GPIO register m...

Page 29: ...us encoder signals 258 Table 14 16 TMR1 register map and reset value 265 Table 14 17 Complementary output channel CxOUT and CxCOUT control bits with break function 274 Table 15 1 Minimum and maximum t...

Page 30: ...terfaces such as SPI I2C USART UART CAN bus controller USB2 0 full speed interface HICK with automatic clock calibration ACC 12 bit ADC programmable voltage monitor PVM and other peripherals Cortex M4...

Page 31: ...ller Flash Controller Flash SRAM OTGFS APB2 Bridge APB1 Bridge APB2 Bus Freq Max 96MHz APB1 Bus Freq Max 96MHz CRM TMR2 TMR3 TMR6 TMR7 TMR13 TMR14 SPI2 I2 S2 ERTC PWC SPI3 I2 S3 USART4 WWDT I2 C1 I2 C...

Page 32: ...P ROM Table WIC Interrupts and Power control SWD SBUS DBUS IBUS 1 1 2 Bit band With the help of bit band read and write access to a single bit can be performed using common load store operations The C...

Page 33: ...irst For a read operation read one word in the bit band region and then move the targeted bit to the right to LSB before returning LSB For a write opearation first move the targeted bit to the left to...

Page 34: ...making code more concise its important function is also reflected in multi task environment When it comes to multiple taks it turns the read modify write operations into a hardware supported atomic op...

Page 35: ...006C 12 19 Configu rable ADC ADC gloabal interrupt 0x0000_0070 13 20 Configu rable TMR1_BRK TMR1_UP TMR1_TRG TMR1_COM TMR1 interrupt 0x0000_0074 14 21 Configu rable TMR1_CH TMR1 capture compare interr...

Page 36: ...main stack pointer MSP from address 0x0000_0000 Get the initial value of the program counter PC from address 0x0000_0004 This value is a reset vector and LSB must be 1 Then take the instructions from...

Page 37: ...T1 and BOOT0 are used to set the specific memory from which CODE starts BOOT1 BOOT0 00 10 CODE starts from the main Flash memory BOOT1 BOOT0 11 CODE starts from Boot code BOOT1 BOOT0 11 CODE starts fr...

Page 38: ...1 3 Device characteristics information Table 1 5 List of abbreviations for registers Register abbr Base address Reset value F_SIZE 0x1FFF F7E0 0xXXXX UID 31 0 0x1FFF F7E8 0xXXXX XXXX UID 63 32 0x1FFF...

Page 39: ...r system memory according to BOOT pins configuration 0x0000_0000 0x07FF_FFFF 0x0800_0000 Flash Memory 0x0800_FFFF Reserved 0x0801_0000 0x1FFF_E400 Boot Memory User System Data 0x1FFF_F800 0x1FFF_F3FF...

Page 40: ...0800 0x0800 0BFF Page 63 0x0800 FC00 0x0800 FFFF Information block 4 KB boot loader 0x1FFF E400 0x1FFF F3FF 512 B user system data 0x1FFF F800 0x1FFF F9FF Flash memory organization 32 KB The main mem...

Page 41: ...x4001 73FF Reserved 0x4001 6C00 0x4001 6FFF Reserved 0x4001 6800 0x4001 6BFF Reserved 0x4001 6400 0x4001 67FF Reserved 0x4001 6000 0x4001 63FF Reserved 0x4001 5C00 0x4001 5FFF Reserved 0x4001 5800 0x4...

Page 42: ...4000 43FF Reserved 0x4000 3C00 0x4000 3FFF SPI3 I2 S3 0x4000 3800 0x4000 3BFF SPI2 I2 S2 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF Watchdog timer WDT 0x4000 2C00 0x4000 2FFF Window watc...

Page 43: ...igure 3 1 Block diagram of each power supply Wake Up Logic I O Ring VSSA VREF From 2 4 V up to VDDA VREF VDD VDDA VSS VSSA VSS VDD LDO POR VDD Power domain 1 2v Power domain VDD Power domain VDDA Powe...

Page 44: ...gure 3 2 Power on reset Low voltage reset waveform Reset VDD VLVR VPOR Temporization tRESTTEMPO VPOR VLVR hysteresis 3 4 Power voltage monitor PVM The PVM is used to monitor the power supply variation...

Page 45: ...EXIT 1 the MCU enters Sleep mode as soon as the system exits the lowest priority interrupt service routine by executing the WFI instruction In Sleep mode all clocks and LDO work normally except CPU cl...

Page 46: ...SLEEPDEE bit in the Cortex M4 system control register Set the LPSEL bit in the power control register PWC_CTRL Clear the SWEF bit in the power control status register PWC_CTRLSTS Execute a WFI WFE ins...

Page 47: ...sleepdeep 0 Enter DEEPSLEEP mode 1 Enter Standby mode Bit 0 VRSEL 0x0 rw LDO state select in deepsleep mode 0 Enabled 1 Low power consumption mode 3 7 2 Power control status register PWC_CTRLSTS Bit...

Page 48: ...ot in Standby mode 1 Device is in Standby mode Note This bit is set by hardware enter Standby mode and cleared by POR LVR or by setting the CLSEF bit Bit 0 SWEF 0x0 ro Standby wake up event flag 0 No...

Page 49: ...XT The HEXT includes two clock sources crystal ceramic resonator and bypass clock The HEXT crystal ceramic resonator is connected externally to a 4 25 MHz HEXT crystal that produces a highly accurate...

Page 50: ...eased before it becomes stable 4 1 2 System clock After a system reset the HICK oscillator is selected as system clock The system clock can make flexible switch among HICK oscillator HEXT oscillator a...

Page 51: ...ontroller specifies a stable flag for each clock source As a result when a clock source is enabled it is possible to determine if the clock is stable by checking the flag pertaining to the clock sourc...

Page 52: ...er on if VDD has been powered off Software reset affects only the battery powered domain 4 3 CRM registers These peripheral registers have to be accessed by bytes 8 bits half words 16 bits or words 32...

Page 53: ...XT becomes stable 0 HEXT is not ready 1 HEXT is ready Bit 16 HEXTEN 0x0 rw High speed external crystal enable This bit is set and cleared by software It can also be cleared by hardware when entering S...

Page 54: ...0001 Reser ved 0010 LICK 0011 LEXT 0100 SCLK 0101 HICK 0110 HEXT 0111 PLL 2 1100 PLL 4 1101 USB 1110 ADC Bit 27 Bit 23 22 USBDIV 0x0 rw USB division The PLL clock after division is used as USB clock 0...

Page 55: ...by 128 1010 SCLK divided by 8 1110 SCLK divided by 256 1011 SCLK divided by 16 1111 SCLK divided by 512 Bit 3 2 SCLKSTS 0x0 R0 System clock select status 00 HICK 01 HEXT 10 PLL 11 Reserved Kept at its...

Page 56: ...XT stable interrupt enable 0 Disabled 1 Enabled Bit 8 LICKSTBLIEN 0x0 rw LICK stable interrupt enable 0 Disabled 1 Enabled Bit 7 CFDF 0x0 ro Clock Failure Detection flag This bit is set by hardware wh...

Page 57: ...MR1 reset 0 Does not reset TMR1 1 Reset TMR1 Bit 10 Reserved 0x0 resd Kept at its default value Bit 9 ADC1RST 0 rw ADC1 reset 0 Does not reset ADC1 1 Reset ADC1 Bit 8 2 Reserved 0x0 resd Kept at its d...

Page 58: ...reset TMR14 1 Reset TMR14 Bit 7 TMR13RST 0 rw TMR13 reset 0 Does not reset TMR13 1 Reset TMR13 Bit 6 Reserved 0x0 resd Kept at its default value Bit 5 TMR7RST 0 rw TMR7 reset 0 Does not reset TMR7 1 R...

Page 59: ...PB2 peripheral clock enable register CRM_AHB2EN Access by words half words and bytes When accessing peripherals on the APB1 wait states are inserted until the end of th peripheral access on APB2 bus B...

Page 60: ...able 0 Disabled 1 Enabled Bit 20 Reserved 0x0 resd Kept at its default value Bit 19 USART4EN 0 rw USART4 clock enable 0 Disabled 1 Enabled Bit 18 USART3EN 0 rw USART3 clock enable 0 Disabled 1 Enabled...

Page 61: ...rce is selected it cannot be changed until the BPDRST bit is reset 00 No clock 01 LEXT 10 LICK 11 Divided HEXT with the ERTC_DIV bit in the CRM_CFG Bit 7 3 Reserved 0x00 resd Kept at its default value...

Page 62: ...Reserved 0x0000 resd Kept at its default value Bit 22 GPIOFRST 0 rw GPIOF reset 0 Does not reset GPIOF 1 Reset GPIOF Bit 21 Reserved 0x0 resd Kept at its default value Bit 20 GPIODRST 0 rw GPIOD reset...

Page 63: ...tion factor PLL pre divider factor 1000MHz 2MHz PLL input clock PLL pre divider factor 16MHz 4 3 13 Additional register1 CRM_MISC1 Access 0 to 3 wait states accessible by words half words or bytes Bit...

Page 64: ...s a clock source of SCLKSEL the SCLK frequency is 0 Fixed 8 MHz that is HICK 6 1 48M or 8M depending on HICKDIV bit Bit 8 HICK_TO_USB 0x0 rw USB 48MHz clock source select 0 USB 48M clock source is PLL...

Page 65: ...0x1FFF E400 0x1FFF F3FF 512 B user system data 0x1FFF F800 0x1FFF F9FF User system data area The system data will be read from the information block of Flash memory whenever a system reset occurs and...

Page 66: ...808 7 0 EPP0 7 0 Flash erase write protection byte 0 in the FLASH_EPPS 7 0 This field is used to protect page0 page31 of main Flash memory Each bit takes care of 4 KB pages 1KB page 0 Erase write prot...

Page 67: ...memory block can be locked by setting the OPLK bit in the FLASH_CTRL register 5 2 2 Erase operation Erase operation must be done before programming Flash memory erase includes page erase and mass eras...

Page 68: ...FLASH_STS register to confirm that there is no other programming operation in progress Set the BANKERS and ERSTR bit in the FLASH_CTRL register to enable mass erase Wait until the OBF bit becomes 0 i...

Page 69: ...in progress Set the FPRGM bit in the FLASH_CTRL register so that the Flash memory programming instructions can be received Write the data word half word byte to be programmed to the designated address...

Page 70: ...n area Bootloader code area can also be programmed as the extension area of the main Flash memory to store user application code When used as main Flash memory extension area it behaves like the main...

Page 71: ...FLASH_CTRL register by software 5 4 2 Erase operation Erase operation must be done before programming User system data area can perform erase operation independently Below should be followed during p...

Page 72: ...the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress Set the USDPRGM bit in the FLASH_CTRL register so that the programming instructions for the us...

Page 73: ...d PRGMERR bit and ODF bit in FLASH_STS End 5 4 4 Read operation User system data area can be accessed through AHB bus of the CPU 5 5 Flash memory protection Flash memory includes access and erase prog...

Page 74: ...lash memory access limits when Flash access protection is enabled Table 5 4 Flash memory access limit Block Protection level Access limits In debug mode or boot from SRAM and boot loader code area Boo...

Page 75: ...ted To enable write access to this register security library must be unlocked first by writing 0xA35F6D24 to the SLIB_UNLOCK register and checking the SLIB_ULKF bit in the SLIB_MISC_STS register to ve...

Page 76: ...for security library code or user code is performed on a page level CRC verify procedure as follows Checkk the OBF bit in the FLASH_STS register to confirm that there is no other programming operatio...

Page 77: ...Bit 6 PFT EN2 0 rw Pretch enable2 0 Prefetch buffer 2 is disabled 1 Prefetch buffer 2 is enabled Bit 5 PFT_ENF 1 rw Prefetch enable 0 Prefetch buffer is disabled 1 Prefetch buffer is enabled Bit 3 HFC...

Page 78: ...n progress It is cleared when operation is completed 5 7 5 Flash control register FLASH_CTRL Bit Register Reset value Type Description Bit 31 18 Reserved 0x0000 resd Kept at its default value Bit 17 L...

Page 79: ...scription Bit 31 27 Reserved 0x00 resd Kept at its default value Bit 26 FAP_HL 0 ro Flash access protection high level The status of the Flash access protection is determined by bit 26 and bit 1 0 Fla...

Page 80: ...ing on the setting of SLIB_STS1 used as security library code Bit 2 EM_SLIB_ENF 0 ro Extension memory sLib enable flag When this bit is set it indicates that the bootloader code area is used as the Fl...

Page 81: ...RR 0 ro Security library password error This bit is set by hardware when the password is incorrect and the setting value of the password clear register is different from 0xFFFF FFFF Note When this bit...

Page 82: ...d return 0 when being read 5 7 17 Security library address setting register SLIB_SET_RANGE For Flash security library address setting only Bit Register Reset value Type Description Bit 31 22 SLIB_ES_S...

Page 83: ..._MODE_SET For boot loader code area only Bit Register Reset value Type Description Bit 31 8 Reserved 0x000000 wo Kept at its default value Bit 7 0 BTM_MODE_SET 0x00 wo Boot memory mode setting 0Xff Bo...

Page 84: ...ndividual weak pull up pull down capability Each pin s output drive capability and output signal slope is configureable by software Each pin can be configured as external interrupt input Each pin can...

Page 85: ...r 6 2 5 General purpose output configuration Mode IOMC OM HDRV ODRV 1 0 PUPD Push Pull without pull up pull down 01 0 000 Output mode normal sourcing sinking strength 001 Output mode large sourcing si...

Page 86: ...ng pull up and pull down input To enable multiplexed function output the port is configured as multiplexed function output mode push pull or open drain mode by setting GPIOx_CFGR or GPIOx_OMODE regist...

Page 87: ...K TMR2_C H1_ETR USART3_ CK USART3 _RX PA6 SPI1_ MISO I2S1_M CK TMR3_CH 1 TMR1_B KIN USART3_ RX USART3 _CTS TMR16_C H1 I2S2_MCK TMR13_CH 1 PA7 SPI1_ MOSI I2S1_S D TMR3_CH 2 TMR1_C H1N USART3_T X TMR14_...

Page 88: ...SD TMR3_CH 2 TMR16_ BKIN I2C1_SMB A USART1 _CK USART2 _RTS_D E SPI2_MOS I I2S2_SD PB6 USART1 _TX I2C1_SCL TMR16_ CH1N USART4 _CK I2S1_MCK SPI3_CS I2S3_WS PB7 USART1 _RX I2C1_SDA TMR17_ CH1N USART4 _CT...

Page 89: ...I2C1_SDA TMR1_ CH2 I2S2_MCK SPI2_SCK I2S2_CK PC8 TMR3_ CH3 TMR1_ CH3 PC9 TMR3_ CH4 I2C2_SDA TMR1_ CH4 OTG_FS_ NOE I2C1_SDA PC10 USART 4_TX USART3_TX SPI3_SCK I2S3_CK PC11 USART 4_RX USART3_RX I2Sext_...

Page 90: ...WC_CTRLSTS 13 1 Once enabled PB5 pin acts as WKUP6 of PWC PB15 PWC_CTRLSTS 14 1 Once enabled PB15 pin acts as WKUP7 of PWC PC5 PWC_CTRLSTS 12 1 Once enabled and PC13 is not occupied the PC15 can be us...

Page 91: ...OM 0x0000 rw GPIOx output mode configuration x 0 15 These field is used to configure the output mode of the GPIOx 0 Push pull reset state 1 Open drain 6 3 3 GPIO drive capability register GPIOx_ODRVR...

Page 92: ...ise the corresponding ODT register bit remains unchanged which acts as ODT register bit operations 0 No action to the correspoinding ODT bits 1 Clear the correspoinding ODT bits Bit 15 0 IOSB 0x0000 w...

Page 93: ...plexed function IOs 0000 MUX0 0001 MUX1 0010 MUX2 0011 MUX3 0100 MUX4 0101 MUX5 0110 MUX6 0111 MUX7 1000 1111 Reserved 6 3 11 GPIO port bit clear register GPIOx_CLR x A B C D F Bit Register Reset valu...

Page 94: ...PB14 Ultra high sourcing sinking strength This bit is written by software to control the PB14 PAD sourcing sinkg strength 0 Not active 1 Corresponding GPIO is switched to ultra high soucing sinking s...

Page 95: ...MAP_SEL 0xX rw Memory address mapping selection This field is read only indicating the boot mode after reset X0 Boot from main Flash memory 01 Boot from system memory 11 Boot from internal SRAM 7 2 2...

Page 96: ...0 GPIOA pin7 0001 GPIOB pin7 0010 GPIOC pin 7 0101 GPIOF pin 7 Others Reserved Bit 11 8 EXINT6 0x0 rw EXINT6 input source configuration These bits are used to select the input source for the EXINT6 ex...

Page 97: ...guration These bits are used to select the input source for the EXINT9 external interrupt 0000 GPIOA pin9 0001 GPIOB pin9 0010 GPIOC pin9 Others Reserved Bit 3 0 EXINT8 0x0 rw EXINT8 input source conf...

Page 98: ...r Reset value Type Description Bit 31 30 I2S_FD 0x00 resd I2S full duplex Using this field any two of I2S can be configured as full duplex mode If not needed this field must remain 00 to avoid unexpec...

Page 99: ...ith up to 22 interrupt lines EXINT_LINE 23 0 EXINT can detect not only GPIO external interrupt sources but also six internal sources such as PVM output ERTC alarm OTGFS wakeup RTC wakeup RTC tamper an...

Page 100: ...INT_ POLCFG2 0x0C 0x0000 0000 EXINT_ SWTRG 0x10 0x0000 0000 EXINT_ INTSTS 0x14 0x0000 0000 8 3 1 Interrupt enable register EXINT_INTEN Interrupt enable register EXINT_INTEN Bit Register Reset value Ty...

Page 101: ...0x00000 rw Software triggle on line x If the corresponding bit in EXINT_INTEN register is 1 the software writes to this bit The hardware sets the corresponding bit in the EXINT_INTSTS automatically t...

Page 102: ...be transferered up to 65535 Support flexible mapping Figure 9 1 DMA block diagram Note The number of DMA peripherals in Figure 9 1 may decrease depending on different models 9 3 Function overview 9 3...

Page 103: ...dshake mechanism In P2M and M2P mode the peripherals need to send a request signal to the DMA controller The DMA channel will send the peripheral transfer request single until the signal is acknowledg...

Page 104: ...d MWIDTH word B7 B5 B6 B4 B3 B1 B2 B0 word3 word2 word1 word0 4th 3rd 2nd 1st HW3 HW2 HW1 HW0 4th 3rd 2nd 1st W3 W2 W1 W0 AHB Read Sequence AHB Write Sequence Figure 9 5 PWIDTH word MWIDTH byte BF BB...

Page 105: ...H1_SRC 11 CH3_SRC 1 CH 2 4 5 6 7 _SRC 0 must be asserted Table 9 3 lists the DMA flexible request sources Table 9 3 DMA flexible request sources CHx_SRC Request source CHx_SRC DMA source CHx_SRC Reque...

Page 106: ...x20 0x0000 0000 DMA_C2PADDR 0x24 0x0000 0000 DMA_C2MADDR 0x28 0x0000 0000 DMA_C3CTRL 0x30 0x0000 0000 DMA_C3DTCNT 0x34 0x0000 0000 DMA_C3PADDR 0x38 0x0000 0000 DMA_C3MADDR 0x3C 0x0000 0000 DMA_C4CTRL...

Page 107: ...vent occurred Bit 21 FDTF6 0x0 ro Channel 6 transfer complete event flag 0 No transfer complete event occurred 1 Transfer complete event occurred Bit 20 GF6 0x0 ro Channel 6 global event flag 0 No tra...

Page 108: ...r complete event flag 0 No transfer complete event occurred 1 Transfer complete event occurred Bit 4 GF2 0x0 ro Channel 2 global event flag 0 No transfer error half transfer or transfer complete event...

Page 109: ...fer flag clear 0 No effect 1 Clear the HDTF5 flag in the DMA_STS register Bit 17 FDTFC5 0x0 rw1c Channel 5 transfer complete flag clear 0 No effect 1 Clear the FDTF5 flag in the DMA_STS register Bit 1...

Page 110: ...0x0 rw1c Channel 1 half transfer flag clear 0 No effect 1 Clear the HDTF1 flag in the DMA_STS register Bit 1 FDTFC1 0x0 rw1c Channel 1 transfer complete flag clear 0 No effect 1 Clear the FDTF1 flag i...

Page 111: ...er can only written when the CHEN bit in the correspoinding channel is set 0 The value is decremented after each DMA transfer Note This register holds the number of data to transfer instead of transfe...

Page 112: ...rw CH1 source select When DMA_FLEX_EN 1 channel 1 is selected by the CH1_SRC Refer to Section 9 3 7 for more information 9 4 8 DMA channel source register1 DMA_SRC_SEL1 Access 0 wait state accessible...

Page 113: ...Perform write read operation through CRC_DT register Set an initialization value with the CRC_IDT register The value is loaded into CRC_DT register after each CRC reset 10 2 CRC registers CRC_DT regi...

Page 114: ...s used to control how to reverse input data 00 No effect 01 Byte reverse 10 Half word reverse 11 Word reverse Bit 4 1 Reserved 0x0 resd Kept at its default value Bit 0 RST 0x0 rw Reset CRC calculation...

Page 115: ...se filter Support SMBus2 0 protocol PEC generation and verification Acknowledgement control for command and data ARP address resolution protocol Master capability Device capability SMBus reminder capa...

Page 116: ...ce switches from slave mode to master mode and returns to slave mode automatcially at the end of data transfer Stop condition is triggered 2 Communication process Master mode communication 1 Start con...

Page 117: ...n If the clock stretching capability is not supported by master then the STRETCH must be set in the I2C_CTRL register It should be noted that the clock stretching capability of I2C slave must be confi...

Page 118: ...3 0 Data hold time tHD DAT SCLD 3 0 Data setup time tSU DAT SCLH 7 0 SCL high SCLL 7 0 SCL low Note Timing configuration cannot be modified once the I2 C is enabled Figure 11 3 Setup and hold time It...

Page 119: ...1000 tf ns SCL SDA falling edge 300 300 120 300 11 4 2 Data transfer management Data transfer counter is available in the I2 C interface to control communication flow It is mainly used for NACK transm...

Page 120: ...slave address is matched ADDRF 1 enable reload mode by setting RLDEN 1 and then set CNT 7 0 1 When a byte is received the TCRLD is set in the I2C_STS register and the slave will pull the SCL bus low...

Page 121: ...s 7 Master transmit 1 I2C_TXDT data register is empty the shift register is empty TDIS 1 in the I2C_STS register 2 Writing 1 to the TXDT register and data is immediately moved to the shift register 3...

Page 122: ...er mode either ASTOPEN 0 or ASTOPEN 1 Master transmitter Figure 11 4 I2 C master transmission flow Master initialization I2C_STS_TDIS 1 No Set I2C_CTRL2_CNT N if N 255 CNT 0xFF N N 255 RLDEN 1 Configu...

Page 123: ...Data2 EV4 I2C_STS_TDIS 1 write Data3 EV5 I2C_STS_TDIS 1 write DataN EV6 I2C_STS_STOPF 1 set I2C_CLR_STOPC 1 TDIS EV3 EV2 EV4 EV6 A DataN EV5 EV1 Initial setting Master receiver Figure 11 6 I2 C maste...

Page 124: ...pecial timing When READH10 1 the master sends data to the slave before read access to the slave as shown in the figure below Operating method When ASTOPEN 0 data is transferred from the master to the...

Page 125: ...SDIR 1 indicates that the slave is sending data The ADDR 6 0 bit of the I2C_STS register indicates what kind of address has been received which is particularly helpful in the case when the dual addres...

Page 126: ...tion of all data transfer 4 Wait for the generation of a STOP condition Once received the STOPF is set in the I2C_STS register The STOPF can be cleared by writing 1 to the STOPC bit in the I2C_CLR reg...

Page 127: ...if STRETCH 1 write data to I2C_TXDT_DT Set I2C_STS_TDBE 1 and I2C_CLR_TDIS 1 Set I2C_CLR_STOPC 1 Figure 11 11 I2 C slave transmission timing Address S r w A Data1 A SCL Stretch Data2 A DataN NA P Mas...

Page 128: ..._DT Yes I2C_STS_STOPF 1 Yes No No Set I2C_CLR_STOPC 1 Figure 11 13 I2 C slave receive timing Address S r w A Data1 A SCL Stretch Data2 A DataN A P Master to Slave Slave to Master S Start A Acknowledge...

Page 129: ...handled by software SMBus host notify protocol The slave device can send data to the master device through SMBus host notify protocol For example the slave can notify the host to implement ARP with t...

Page 130: ...L is pulled low by a master device during the period from the ACK of the last byte to the 8th bit of the next byte a single byte It should be noted that both tLOW SEXT and tLOW MEXT only deal with the...

Page 131: ...of master communication flow 1 I2C clock initialization by setting the I2C_CLKCTRL register I2 C clock divider DIV 7 0 Data hold time tHD DAT SDAD 3 0 Data setup time tSU DAT SCLD 3 0 SCL high durati...

Page 132: ...XDT register becomes empty TDIS 1 again 4 Writing 2 to the TXDT register TDIS is cleared 5 Repeat step 2 and 3 until the specified data N 1 is sent 6 The master will automatically transmit the Nth dat...

Page 133: ...N 1 I2C_CTRL2_PECTEN 1 Configure slave address GENSTART 1 I2C_STS_ACKFAIL 1 Wait I2C_STS_STOPF 1 Set I2C_CLR_STOPC 1 I2C_CLR_ACKFAILC 1 Yes Yes No Write I2C_TXDT_DT N Bytes Transmitted ASTOPEN 0 No Ye...

Page 134: ...STS_TDIS 1 write Data1 EV3 I2C_STS_TDIS 1 write Data2 EV4 I2C_STS_TDIS 1 write Data3 EV5 I2C_STS_TDIS 1 write DataN EV6 I2C_STS_STOPF 1 set I2C_CLR_STOPC 1 TDIS EV3 EV2 EV4 EV6 A PEC EV5 EV1 DataN A I...

Page 135: ...1 register Enable address 1 by setting ADDR1EN 1 in the I2C_OADDR1 register 3 SMBus related initialization Select SMBus host device default address acknowledged 0b1100001x by setting DEVADDREN 1 Enabl...

Page 136: ...he STOPF is cleared by writing 1 to the STOPC transmission ends 6 Data transfer slave receive clock stretching enabled STRETCH 0 After address matching 1 I2C_RXDT register becomes empty the shift regi...

Page 137: ...S_STOPF 1 Yes Yes No No Set I2C_STS_TDBE 1 and I2C_CLR_TDIS 1 Set I2C_CLR_STOPC 1 Figure 11 19 SMBus slave transmission timing Address S r w A Data1 A Data2 A P Master to Slave Slave to Master S Start...

Page 138: ...1 Yes No I2C_STS_RDBF 1 No Read I2C_RXDT_DT Yes I2C_STS_STOPF 1 Yes No Set I2C_CLR_STOPC 1 Slave initialization I2C_CTRL1_PECEN 1 Yes Figure 11 21 SMBus slave receive timing Address S r w A Data1 A Da...

Page 139: ...N 1 1 Set the peripheral address DMA_CxPADDR I2C_RXDT address 2 Set the memory address DMA_CxMADDR memory address 3 The transmission directionis set from peripheral to memory DTD 0 in the DMA_CHCTRL r...

Page 140: ...be released and go automatically back to slave mode Bus error BUSERR The SDA line during a data transfer must be kept in a stable state whehn the SCL is in high level The SDA can be changed only when...

Page 141: ...MOUT PEC error PECERR Overrun Underrun OUF Arbitration lost ARLOST Bus error BUSERR 11 6 I2C debug mode When the microcontroller enters debug mode CortexTM M4 halted the SMBUS timeout either continues...

Page 142: ...Reserved 0x0 res Kept at its default value Bit 17 STRETCH 0x0 rw Clock stretching mode 0 Clock stretching mode enabled 1 Clock stretching mode disabled Bit 16 SCTRL 0x0 rw Slave receive data control 0...

Page 143: ...nd data reload mode enable 0 Send data reload mode disable 1 Send data reload mode enabled Bit 23 16 CNT 7 0 0x00 rw Transmit data counter Bit 15 NACKEN 0x0 rw Not acknowledge enable 0 Acknowledge ena...

Page 144: ...3 0 0x0 rw SCL output delay TSCLD SCLD 1 x DIV 1 x TI2C_CLK Bit 19 16 SDAD 3 0 0x0 rw SDA output delay TSDAD SDAD 1 x DIV 1 x TI2C_CLK Bit 15 8 SCLH 7 0 0x00 rw SCL high level TSCLH SCLH 1 x DIV 1 x T...

Page 145: ...r Bit 10 OUF 0x0 r Overrun or underrun flag In transmission mode 0 No overrun or underrun 1 Underrun In reception mode 0 No overrun or underrun 1 Overrun Bit 9 ARLOST 0x0 r Arbitration lost flag 0 No...

Page 146: ...s timeout flag SMBus timeout flag is cleared by writing 1 Bit 11 PECERRC 0x0 w Clear PEC receive error flag PEC receive error flag is cleared by writing 1 Bit 10 OUFC 0x0 w Clear overload underload fl...

Page 147: ...ous SmartCard protcoal defined in ISO7816 3 standard and CTS RTS Clear To Send Request To Send hardware flow operation It also allows mutli processor communication and supports silent mode waken up by...

Page 148: ...p by configuraing ID match and bus idle frame Synchronous mode Programmable baud rate generator Shared by transmission and reception up to 9 MBits s Programmable frame format Programmable data word le...

Page 149: ...escribed in the subsequent sections are used to make USART initialization configuration 1 LIN mode While LINEN bit is set 1 CLKEN STOPBN 1 0 SCMEN SLHDEN IRDAEN and DBN bits are all set 0 11 bit or 12...

Page 150: ...it STOPBN 01 two bit STOPBN 10 and 1 5 bit STOPBN 11 stop bits Set the PEN bit will enable parity control PSEL 1 indicates Odd parity while PSEL 0 for Even parity Once the parity control is enabled th...

Page 151: ...ation format is as follows TX RX DIV Where refers to the system clock of USART i e PCLK1 PCLK2 Note 1 Write access to the USART_BAUDR register before UEN The baud rate register value should not be alt...

Page 152: ...register accordingly 7 Baud rate configuration Refer to baud rate generation for details 8 Transmitter enable When the TEN bit is set the USART transmitter will send an idle frame 9 Write operation W...

Page 153: ...ster by software The RDBF flag can also be cleared by writing 0 to it The RDBF bit must be cleared before the end of next frame reception to avoid overrun error Break frame reception Non LIN mode It i...

Page 154: ...oise In the non synchronous mode the USART receiver samples data on the 7th 8th and 9th bits with its oversampling techniques to distinguish valid data input from noise based on different sampling val...

Page 155: ...SART interrupt source and interrupt enable control bit An interrupt will be generated over an event when the corresponding interrupt enable bit is set Table 12 4 USART interrupt request Interrupt even...

Page 156: ...CTSCF 0 rw0c CTS change flag This bit is set by hardware when the CTS status line changes It is cleared by software 0 No change on the CTS status line 1 A change occurs on the CTS status line Bit 8 B...

Page 157: ...DT read operation 0 No framing error is detected 1 Framing error is detected Bit 0 PERR 0 ro Parity error This bit is set by hardware when parity error occurs It is cleared by software USART_STS regis...

Page 158: ...data bits 11 Write operation forbidden Bit 11 WUM 0 rw Wakeup mode This bit determines the way to wake up silent mode 0 Waken up by idle line 1 Waken up by ID match Bit 10 PEN 0 rw Parity enable This...

Page 159: ...ive pin swap 0 Transmit receive pin is not swappable 1 Transmit receive pin is swappable Bit 14 LINEN 0 rw LIN mode enable 0 LIN mode is disabled 1 LIN mode is enabled Bit 13 12 STOPBN 0 rw STOP bit n...

Page 160: ...ode disabled The control signal DE output is disabled RTS pin is used in RS232 mode 1 RS485 mode enabled The control signal DE outputs on the RTS pin Bit 13 11 Reserved 0 resd Forced 0 by hardware Bit...

Page 161: ...value This field specifies the guard time value The transmission complete flag is set after this guard time in smartcard mode Bit 7 0 ISDIV 0x00 rw IrDA smartcard division In IrDA mode 8 bit 7 0 is va...

Page 162: ...gram Figure 13 1 SPI block diagram SPI_SCK controller SPI_STS BF ROE RR MME RR CCE RR TUER R ACS TDBE RDBF Communication controller CS controller SWCSEN SWCSIL SLBEN SLBTD ORA MDIV3EN MDIV 3 0 CLKPOL...

Page 163: ...re unidirectional full duplex mode and SPI IO connection The SPI operats in two wire unidirectional full duplex mode when the SLBEN bit and the ORA bit is both 0 In this case the SPI supports data tra...

Page 164: ...eed to check any flag before disabling the SPI However it is required to wait until the BF becomes 0 before entering power saving mode Figure 13 5 shows single wire bidirectional half duplex mode and...

Page 165: ...In master mode with CS being as an output HWCSOE 1 SWCSEN 0 the CS hardware control is enabled If the SPI is enabled low level is output on the CS pin The CS signal is then released after the SPI is d...

Page 166: ...and configuration procedure of the SPI are described as follows CRC configuration procedure CRC calculation polynominal is configured by setting the SPI_CPOLY register CRC enable The CRC calculation i...

Page 167: ...he current SPI from DMA channel map table described in DMA chapter Configure the destination of DMA transfer Configure the memory address as the destination of DMA transfer in the DMA control register...

Page 168: ...ion procedure are as follows Transmitter configuration procedure Configure full duplex half duplex selector Configure chip select controller Configure SPI_SCK controller Configure CRC if necessary Con...

Page 169: ...x master slave timings Full duplex communication master mode Configured as follows MSTEN 1 Master enable SLBEN 0 Full duplex mode CLKPOL 0 CLKPHA 0 SCK idle output low use the first edge for sampling...

Page 170: ...gure 13 8 Master half duplex transmit SCK BF flag CS MOSI 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 TDBE flag Drive Transmit buffer empty and software can write data Half duplex communication sl...

Page 171: ...1 1 1 1 0 0 0 0 0 0 0 BF flag remains low RDBF flag Sampling Software needs to read the received data 13 2 11TI mode The SPI interface supports TI mode The TIEN bit can be set to enable SPI TI mode I...

Page 172: ...I interrupts RDBF RDBFIE TDBE TDBEIE ROERR MMERR CCERR ERRIE SPI interrupt 13 2 13IO pin control Usually the SPI is connected to external devices through four pins MISO Master In Slave Out The pin rec...

Page 173: ...A single I2 S supports half duplex However it can work with two additional instantiated I2 S modules I2 S2EXT and I2 S3EXT to achieve full duplex mode In other words combining the I2 S2 with the I2 S2...

Page 174: ...I2S2_SCK I2S1_WS I2S2_WS SPI1_MOSI I2S1_SD in out SPI2_MOSI I2S2_SD in out I2Sext_SD in out I2 S full duplex master side It supports master or slave mode It can programmed as a receiver or transmitte...

Page 175: ...slave device reception mode Figure 13 19 I2 S slave device reception I2S master CK SD WS I2S slave CK SD WS Master device transmission Set the I2SMSEL bit and OPERSEL 1 0 10 the I2 S will work in mas...

Page 176: ...bit I2SDBN 10 32 bit Select channel bits by setting the I2SCBN bit I2SDBN 0 16 bit I2SDBN 1 32 bit Note Read Write operation mode depends on the selected audio protocols data bits and channel bits The...

Page 177: ...ut to the slave via IO for data reception and transmission In slave mode the communication clock is provided by master and is input to the SPI via IO In all the I2S_SCK controller is used for the gene...

Page 178: ...f DMA transfer in the DMA control register Datat will be sent to this address after transmit request is received by DMA Configure the source of DMA transfer Configure the memory address as the source...

Page 179: ...protocols data bits and channel bits Refer to the audio protocol selector section for more information Pay more attention to the I2S disable operation under different configurations shown as follows...

Page 180: ...3 10IO pin control The I2S needs three pins for transfer operatioin namely the SD WS and CK The MCLK pin is also required if need to provide main clock for peripherals The I2 S shares some pins with...

Page 181: ...t only mode Bit 13 CCEN 0x0 rw RC calculation enable 0 Disabled 1 Enabled Bit 12 NTC 0x0 rw Transmit CRC next When this bit is set it indicates that the next data transferred is CRC value 0 Next trans...

Page 182: ...arts from the first clock edge 1 Data capture starts from the second clock edge Note The SPI_CTRL1 register must be 0 in I2 S mode 13 4 2 SPI control register2 SPI_CTRL2 Bit Register Reset value Type...

Page 183: ...e STS register Bit 7 BF 0x0 ro Busy flag 0 SPI is not busy 1 SPI is busy Bit 6 ROERR 0x0 ro Receiver overflow error 0 No overflow error 1 Overflow error occurs Bit 5 MMERR 0x0 ro Master mode error Thi...

Page 184: ...e format is set to 8 bit data only the 8 bit LSB 7 0 are calculated based on CRC8 standard when 16 bit data bit is selected follow CRC16 standard Note This register is only used in SPI mode 13 4 7 SPI...

Page 185: ...bit data length 01 24 bit data length 10 32 bit data length 11 Not allowed Bit 0 I2SCBN 0x0 rw I2 S channel bit num This bit can be configured only when the I2 S is set to 16 bit data otherwise it is...

Page 186: ...5 O 4 O O X TMR3 16 Up Down Up Down X 1 65535 O 4 O O X TMR13 TMR14 16 Up X 1 65535 X 1 X X X TMR15 16 Up 8 bit 1 65535 O 2 O X O TMR16 TMR17 16 Up 8 bit 1 65535 O 1 X X O Basic timer TMR6 TMR7 16 Up...

Page 187: ...ER 12 11 13 14 15 16 00 01 02 03 04 05 06 07 14 1 3 2 Counting mode The basic timer only supports upcounting mode It has an internal 16 bit counter in which the value is loaded with the TMRx_PR regist...

Page 188: ...microcontroller enters debug mode Cortex M4 core halted the TMRx counter stops counting when the TMRx_PAUSE bit is set 14 1 4 TMR6 and TMR7 registers These peripheral registers must be accessed by wo...

Page 189: ...ter and the prescaler are reinitialized Note This bit is set and cleared by software Bit 0 TMREN 0x0 rw TMR enable 0 Disabled 1 Enabled 14 1 4 2 TMR6 and TMR7 control register2 TMRx_CTRL2 Bit Register...

Page 190: ...NT fTMR_CLK DIV 15 0 1 At each overflow event DIV value is sent to the DIV register 14 1 4 8 TMR6 and TMR7 period register TMRx_PR Bit Register Reset value Type Description Bit 15 0 PR 0x0000 rw Perio...

Page 191: ...of TMR2 TMR5 can be provided by the internal clock CK_INT external clock external clock mode A and B and internal trigger input ISx Internal clock CK_INT By default the CK_INT divided by a prescaler i...

Page 192: ...e synchronization circuit Figure 14 11 Counting in external clock mode B 30 COUNTER OVFIF TMR_CLK 00 ESDIV 1 0 Clear CNT_CLK EXT 0000 ESF 3 0 31 32 0 1 2 3 4 Internal trigger input ISx Timer synchroni...

Page 193: ...The value in the TMRx_PR is immediately moved to the shadow register by deault When the periodic buffer is enabled PRBEN 1 the value in the TMRx_PR register is transferred to the shadow register only...

Page 194: ..._PR register down to 1 an underflow event is generated and then restarts counting from 0 When the counter counts from 0 to the value of the TMRx_PR register 1 an overflow event is generated and then r...

Page 195: ...3 TMR input function Each of timers TMR2 and TMR3 has four independent channels with each channel being configured as input or output As input the channel can be used for the filtering selection divi...

Page 196: ...mparator and an output controller It is used to program the period duty cycle and polarity of the output signal Figure 14 20 Capture compare channel output stage channel 1 to 4 Output mode controller...

Page 197: ...e and the TMRx_CxDT register will determine the level of CxORAW in advance Figure 14 21 gives an example of output compare mode toggle with C1DT 0x3 When the counter value is equal to 0x3 C1OUT toggle...

Page 198: ...ed until the next overflow event This function can only be used in output capture or PWM modes and does not work in forced mode Figure 14 25 shows the example of clearing CxORAW signal When the EXT in...

Page 199: ...mode the counter is controlled by a selected trigger input The counter starts counting when the trigger input is high and stops as soon as the trigger input is low Figure 14 27 Example of suspend mode...

Page 200: ...ounting period TMRx_PR registers Configure the slave timer trigger input signal TRGIN as master timer output STIS 2 0 in the TMRx_STCTRL register Configure the slave timer to use external clock mode A...

Page 201: ...er as trigger mode SMSEL 3 b110 in the TMR2_STCTRL register Figure 14 31 Starting master and slave timers synchronously by an external trigger COUNTER PR 15 0 TMREN TMR_CLK 0 DIV 15 0 32 22 PR 15 0 TR...

Page 202: ...y counting mode selection 00 One way counting mode depending on the OWCDIR bit 01 Two way counting mode1 count up and down alternately the output flag bit is set only when the counter counts down 10 T...

Page 203: ...x_STCTRL Bit Register Reset value Type Description Bit 15 ESP 0x0 rw External signal polarity 0 High or rising edge 1 Low or falling edge Bit 14 ECMBEN 0x0 rw External clock mode B enable This bit is...

Page 204: ...input 111 External clock mode A Rising edge of the TRGIN input clocks the counter Note Please refer to count mode section for the details on encoder mode A B C 14 2 4 4 TMR2 and TMR3 DMA interrupt en...

Page 205: ...0 No trigger event occurs 1 Trigger event is generated Trigger event an active edge is detected on TRGIN input or any edge in suspend mode Bit 5 Reserved 0x0 resd Kept at its default value Bit 4 C4IF...

Page 206: ...er Reset value Type Description Bit 15 C2OSEN 0x0 rw Channel 2 output switch enable Bit 14 12 C2OCTRL 0x0 rw Channel 2 output control Bit 11 C2OBEN 0x0 rw Channel 2 output buffer enable Bit 10 C2OIEN...

Page 207: ...rection of the channel 1 input or output and the selection of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IRAW 10 Input C1IN is mapped on C2IRAW 11 Input C1IN is mapped on STCI This m...

Page 208: ...d the selection of input pin when C4EN 0 00 Output 01 Input C4IN is mapped on C4IRAW 10 Input C4IN is mapped on C3IRAW 11 Input C4IN is mapped on STCI This mode works only when the internal trigger in...

Page 209: ...scription Bit 4 C2EN 0x0 rw Channel 2 enable Pleaser refer to C1EN description Bit 3 2 Reserved 0x0 resd Kept at its default value Bit 1 C1P 0x0 rw Channel 1 polarity When the channel 1 is configured...

Page 210: ...ared with the CVAL value Whether the written value takes effective immediately depends on the C1OBEN bit and the corresponding output is generated on C1OUT as configured 14 2 4 14 TMR2 and TMR3 channe...

Page 211: ...00 rw DMA transfer bytes This field defines the number of DMA transfers 00000 1 byte 00001 2 bytes 00010 3 bytes 00011 4 bytes 10000 17 bytes 10001 18 bytes Bit 7 5 Reserved 0x0 resd Kept at its defau...

Page 212: ...in the TMRx_PR is immediately moved to the shadow register by deault When the periodic buffer is enabled PRBEN 1 the value in the TMRx_PR register is transferred to the shadow register only at an ove...

Page 213: ...CVAL CIDT Capture compare seletion Figure 14 37 Channel 1 input stage C1IRAW STCI C1IFP1 C1IN C1IPS C1IF_rising C1IF_falling fDTS Filter Downcounter Edge detector Polarity selection Capture compare se...

Page 214: ...t CxOCTRL 3 b100 101 to enable forced output mode In this case the CxORAW is forced to be the programmed level irrespective of the counter value Despite this the channel flag bit and DMA request still...

Page 215: ...AW TMR_CLK 0 DIV 15 0 32 110 C1OCTRL 2 0 3 C1DT 15 0 C1ORAW 0 0 CIDT 15 0 C1ORAW 32 C1DT 15 0 1 C1ORAW 32 C1DT 15 0 Figure 14 41 One pulse mode 0 1 2 3 4 5 6 40 41 42 43 44 5F 60 61 0 COUNTER 61 PR 15...

Page 216: ...s enabled Bit 6 4 Reserved 0x0 resd Kept at its default value Bit 3 OCMEN 0x0 rw One cycle mode enable This bit is use to select whether to stop counting at an update event 0 The counter does not stop...

Page 217: ...rved 0x000 resd Kept at its default value Bit 1 C1SWTR 0x0 wo Channel 1 event triggered by software This bit is set by software to generate a channel 1 event 0 No effect 1 Generate a channel 1 event B...

Page 218: ...0 Need to compare the CVAL with C1DT before generating an output 1 No need to compare the CVAL and C1DT An output is generated immediately when a trigger event occurs Bit 1 0 C1C 0x0 rw Channel 1 conf...

Page 219: ...is configured as input mode 0 C1IN active edge is on its rising edge When used as external trigger C1IN is not inverted 1 C1IN active edge is on its falling edge When used as external trigger C1IN is...

Page 220: ...alue Bit 1 0 TMR14_CH1_IRMP 0x0 rw TMR14 channel 1 input remap 00 TMR14 channel 1 input is connected to GPIO 01 ERTC_CLK 10 HEXT 32 11 CLK_OUT 14 4 General purpose timer TMR15 14 4 1 TMR15 introductio...

Page 221: ...be provided by the internal clock CK_INT external clock external clock mode A and internal trigger input ISx Internal clock CK_INT By default the CK_INT divided by the prescaler is used to drive the c...

Page 222: ...e next overflow event occurs Table 14 9 TMRx internal trigger connection Slave controller IS0 STIS 000 IS1 STIS 001 IS2 STIS 010 IS3 STIS 011 TMR1 TMR15 TMR2 TMR3 TMR2 TMR1 TMR15 TMR3 USB_OTG_SOF TMR3...

Page 223: ...14 48 Overflow event when PRBEN 1 0 1 2 3 21 22 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 32 PR 15 0 OVFIF TMR_CLK 0 DIV 15 0 22 Clear Clear Clear Repetition counter mode The repletion counter mode is...

Page 224: ...re enabled If the selected trigger signal is detected when the CxIF is set the CxOF is set To capture the rising edge of C1IN input following the configuration procedure mentioned below Set C1C 01 in...

Page 225: ...RAW is forced to be the programmed level irrespective of the counter value Despite this the channel flag bit and DMA request still depend on the compare result Output compare mode Set CxOCTRL 2 b001 0...

Page 226: ...3 4 5 6 40 41 42 43 44 5F 60 61 0 COUNTER 61 PR 15 0 42 C1DT 15 0 TRGIN C1ORAW C1OUT Dead time insertion The TMR15 contains a set of reverse channel output This function is enabled by the CxCEN bit an...

Page 227: ...f Once OEN 0 the channel output level is defined by the CxIOS bit If FCSODIS 0 the timer output is disabled otherwise the output enable remains high When complementary outputs are used The outputs are...

Page 228: ...by setting the SMSEL 2 0 bit Slave modes include Slave mode Reset mode The counter and its prescaler can be reset by a selected trigger signal An overflow event can be generated when OVFS 0 Figure 14...

Page 229: ...8 32 OVFIF See chapter 14 2 3 5 for more information about timer synchronization 14 4 3 7 Debug mode When the microcontroller enters debug mode CortexTM M4 core halted the TMRx counter stops counting...

Page 230: ...s at an update event Bit 2 OVFS 0x0 rw Overflow event source This bit is used to select overflow event or DMA request sources 0 Counter overflow setting the OVFSWTR bit or overflow event generated by...

Page 231: ...1 Enabled Bit 6 4 STIS 0x0 rw Subordinate TMR input selection This field is used to select the subordinate TMR input 000 Internal selection 0 IS0 001 Internal selection 1 IS1 010 Internal selection 2...

Page 232: ...ter TMR15_ISTS Bit Register Reset value Type Description Bit 15 11 Reserved 0x0 resd Kept at its default value Bit 10 C2RF 0x0 rw0c Channel 2 recapture flag Please refer to C1RF description Bit 9 C1RF...

Page 233: ...o generate a break event 0 No effect 1 Generate a break event Bit 6 TRGSWTR 0x0 rw Trigger event triggered by software This bit is set by software to generate a trigger event 0 No effect 1 Generate a...

Page 234: ...TMRx_C1DT 011 Switch C1ORAW level when TMRx_CVAL TMRx_C1DT 100 C1ORAW is forced low 101 C1ORAW is forced high 110 PWM mode A OWCDIR 0 C1ORAW is high once TMRx_C1DT TMRx_CVAL else low OWCDIR 1 C1ORAW i...

Page 235: ...hat the input edge can pass the filter only after N sampling events 0000 No filter sampling is done at f 1000 f f 8 N 6 0001 f f _ N 2 1001 f f 8 N 8 0010 f f _ N 4 1010 f f 16 N 5 0011 f f _ N 8 1011...

Page 236: ...h break function Control bit Output state 1 OEN bit FCSODIS bit FCSOEN bit CxEN bit CxCEN bit CxOUT output state CxCOUT output state 1 X 0 0 0 Output disabled no driven by the timer CxOUT 0 Cx_EN 0 Ou...

Page 237: ...rred to the actual prescaler register when an overflow event occurs 14 4 4 11 TMR15 period register TMR15_PR Bit Register Reset value Type Description Bit 15 0 PR 0x0000 rw Period value This defines t...

Page 238: ...111 f_SAMPLING f_DTS 32 N 8 Bit 15 OEN 0x0 rw Output enable This bit acts on the channels as output It is used to enable CxOUT and CxCOUT outputs 0 Disabled 1 Enabled Bit 14 AOEN 0x0 rw Automatic outp...

Page 239: ...ter for the first time 14 4 4 16 TMR15 DMA control register TMR15_DMACTRL Bit Register Reset value Type Description Bit 15 13 Reserved 0x0 resd Kept at its default value Bit 12 8 DTB 0x00 rw DMA trans...

Page 240: ...al clock CK_INT Internal clock CK_INT By default the CK_INT divided by the prescaler is used to drive the counter to start counting Figure 14 63 Control circuit with CK_INT divided by 1 CK_INT TMREN C...

Page 241: ...overflow event can be adjusted by setting the repettion counter value Figure 14 66OVFIF when RPR 2 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 32 PR 15 0 2 1 0 RPR 7 0 OVFIF 14 5 3 3 TMR inp...

Page 242: ...ure 14 69 Channel output stage Output mode controller CxORAW Output enable circuit C1OUT CVAL CxDT CVAL CxDT To the master mode controller CVAL CxDT Compare Polarity selection Dead time generate Outpu...

Page 243: ...words the comparison result is advanced so the comparison result between the counter value and the TMRx_CxDT register will determine the level of CxORAW in advance Figure 14 70 gives an example of out...

Page 244: ...igure 14 73 gives an example of dead time insertion when CxP 0 CxCP 0 OEN 1 CxEN 1 and CxCEN 1 Figure 14 73 Complementary output with dead time insertion Delay Delay C1ORAW C1OUT C1COUT 14 5 3 5 TMR b...

Page 245: ...t again at the next overflow event Note When the break input is active the OEN cannot be set nor the status flag BRKIF can be cleared Figure 14 74 Example of TMR break function CxORAW Delay Delay Dela...

Page 246: ...rated by slave timer controller 1 Only counter overflow generates an overflow event Bit 1 OVFEN 0x0 rw Overflow event enable 0 Enabled 1 Disabled Bit 0 TMREN 0x0 rw TMR enable 0 Disabled 1 Enabled 14...

Page 247: ...fault value Bit 9 C1RF 0x0 rw0c Channel 1 recapture flag This bit indicates whether a recapture is detected when C1IF 1 This bit is set by hardware and cleared by writing 0 0 No capture is detected 1...

Page 248: ...1 event Bit 0 OVFSWTR 0x0 wo Overflow event triggered by software This bit is set by software to generate an overflow event 0 No effect 1 Generate an overflow event 14 5 4 6 TMR16 and TMR17 channel m...

Page 249: ...the CVAL and C1DT An output is generated immediately when a trigger event occurs Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define the direction of the channel 1 input or output...

Page 250: ...1 polarity When the channel 1 is configured as output mode 0 C1OUT is active high 1 C1OUT is active low When the channel 1 is configured as input mode 0 C1IN active edge is on its rising edge When use...

Page 251: ...e external I O pins connected to the complementary CxOUT and CxCOUT channels depends on the CxOUT and CxCOUT channel state and the GPIO and the IOMUX registers 14 5 4 8 TMR16 and TMR17 counter value T...

Page 252: ...NG f_DTS 32 N 5 0110 f_SMPLING f_DTS 4 N 6 1110 f_SAMPLING f_DTS 32 N 6 0111 f_SAMPLING f_DTS 4 N 8 1111 f_SAMPLING f_DTS 32 N 8 Bit 15 OEN 0x0 rw Output enable This bit acts on the channels as output...

Page 253: ...ting to the TMRx_BRK register for the first time 14 5 4 14 TMR16 and TMR17 DMA control register TMRx_DMACTRL Bit Register Reset value Type Description Bit 15 13 Reserved 0x0 resd Kept at its default v...

Page 254: ...C2OUT C3OUT C4OUT C2COUT C3COUT TRGOUT To other timers To ADC BRK Clock failure event From clock control CSS Clock Security System TMRx_BRK TMRx_CH4 TMRx_CH3 TMRx_CH2 TMRx_CH1 TMRx_EXT TMRx_CH1 TMRx_C...

Page 255: ...C ISx CK_DIV Trigger select Slave mode control External clock control CI1RAW Filter Edge detector C2IF_Rising C2IF_Falling Polarity selection Note The delay between the signal on the input side and th...

Page 256: ...imer IS0 STIS 000 IS1 STIS 001 IS2 STIS 010 IS3 STIS 011 TMR1 TMR15 TMR2 TMR3 TMR2 TMR1 TMR15 TMR3 USB_OTG_SOF TMR3 TMR1 TMR2 TMR15 TMR15 TMR2 TMR3 TMR16 TMR17_OC Figure 14 81 Counter timing with pres...

Page 257: ...unting mode In downcounting mode the counter counts from the value programmed in the TMRx_PR register down to 0 and restarts from the value programmed in the TMRx_PR register and generates a counter u...

Page 258: ...PR 15 0 2 1 0 RPR 7 0 OVFIF Encoder interface mode To enble the encoder interface mode write SMSEL 2 0 3 b001 3 b010 3 b011 In this mode the two inputs C1IN C2IN are required Depending on the level o...

Page 259: ...signal is detected and the capture compare interrupt flag bit CxIF is set An interrupt DMA request will be generated if the CxIEN bit and CxDEN bit are enabled If the selected trigger signal is detect...

Page 260: ...the CxDT register The counter value is compared with the value of the TMRx_CxDT register and the corresponding level signal is sent according to the counting direction For more information on PWM mod...

Page 261: ...The counter only counts only one cycle and the output signal sents only one pulse Figure 14 92 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31...

Page 262: ...7 CxDT EXT CxORAW Dead time insertion The channel 1 to 3 of the advanced control timers contains a set of reverse channel output This function is enabled by the CxCEN bit and its polarity is defined...

Page 263: ...is activated The CxIOS and CxCIOS bits are used to program the level after dead time Even in this case the CxIOS and CxCIOS cannot be driven to their actival level a the same time It should be note th...

Page 264: ...100 Example of suspend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C D 10 PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 101 SMSEL 2 0 CI1F1 TMR_EN CNT_CLK Slave mode Trigger mode The counter can start counting...

Page 265: ...1_C3DT 0x3C 0x0000 TMR1_C4DT 0x40 0x0000 TMR1_BRK 0x44 0x0000 TMR1_DMACTRL 0x48 0x0000 TMR1_DMADT 0x4C 0x0000 TMR1_CM3 0x70 0x0000 TMR1_C5DT 0x74 0x0000 14 6 4 1 TMR1 control register1 TMR1_CTRL1 Bit...

Page 266: ...EN 0x0 rw TRGOUT2 enable 0 TRGOUT2 disabled 1 TRGOUT2 enabled Bit 30 15 Reserved 0x0 resd Kept at its default value Bit 14 C4IOS 0x0 rw Channel 4 idle output state Bit 13 C3CIOS 0x0 rw Channel 3 compl...

Page 267: ...SDIV 0x0 rw External signal divide This field is used to select the frequency division of an external trigger 00 Normal 01 Divided by 2 10 Divided by 4 11 Divided by 8 Bit 11 8 ESF 0x0 rw External sig...

Page 268: ...ription Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 TDEN 0x0 rw Trigger DMA request enable 0 Disabled 1 Enabled Bit 13 HALLDE 0x0 rw HALL DMA request enable 0 Disabled 1 Enabled Bit 12 C...

Page 269: ...ent occurs 1 Trigger event is generated Trigger event an active edge is detected on TRGIN input or any edge in suspend mode Bit 5 HALLIF 0x0 rw0c HALL interrupt flag This bit is set by hardware on HAL...

Page 270: ...1 event 0 No effect 1 Generate a channel 1 event Bit 0 OVFSWTR 0x0 wo Overflow event triggered by software This bit is set by software to generate an overflow event 0 No effect 1 Generate an overflow...

Page 271: ...disabled The new value written to the TMRx_C1DT takes effect immediately 1 Buffer function of TMRx_C1DT is enabled The value to be written to the TMRx_C1DT is stored in the buffer register and can be...

Page 272: ...of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IRAW 10 Input C1IN is mapped on C2IRAW 11 Input C1IN is mapped on STCI This mode works only when the internal trigger input is selected...

Page 273: ...ital filter Bit 3 2 C3IDIV 0x0 rw Channel 3 input divider Bit 1 0 C3C 0x0 rw Channel 3 configuration This field is used to define the direction of the channel 1 input or output and the selection of in...

Page 274: ...n by the timer CxOUT 0 Cx_EN 0 Output disabled no driven by the timer CxCOUT 0 CxCEN 0 0 0 1 Output disabled no driven by the timer CxOUT 0 Cx_EN 0 CxORAW polarity CxCOUT CxORAW xor CxCP CxCEN 1 0 1 0...

Page 275: ...e of the TMRx counter The timer stops working when the period value is 0 14 6 4 13 TMR1 repetition period register TMR1_RPR Bit Register Reset value Type Description Bit 15 0 RPR 0x00 rw Repetition of...

Page 276: ...14 6 4 18 TMR1 break register TMR1_BRK Bit Register Reset value Type Description Bit 31 17 Reserved 0x0 resd Kept at its default value Bit 19 16 BKF 0x0 rw Brake input filter This field is used to set...

Page 277: ..._CCTRL CxP and CxCP TMRx_BRK FCSODIS and FCSOEN 11 Write protection level 1 The following bits and all bits in level 2 are write protected TMRx_CMx C2OCTRL and C2OBEN Note Once WPC 0 its content remai...

Page 278: ...tion Bit 15 6 Reserved 0x000 resd Kept at its default value Bit 7 C5OSEN 0x0 rw Channel 5 output switch enable Bit 6 4 C5OCTRL 0x0 rw Channel 5 output control Bit 3 C5OBEN 0x0 rw Channel 5 output buff...

Page 279: ...er Figure 15 1 Window watchdog block diagram EN 7 bit window value WIN 6 0 Prescaler 1 2 4 8 7 bit counter CNT 6 0 PCLK 4096 CNT 0x40 reset reload at CNT WIN reset To prevent sytem reset the counter m...

Page 280: ...peripheral registers must be accessed by word 32 bits Table 15 2 WWDT register map and reset value Register name Offset Reset value WWDT_CTRL 0x00 0x7F WWDT_CFG 0x04 0x7F WWDT_STS 0x08 0x00 15 5 1 Con...

Page 281: ...ter than the window register value a reset is generated The counter must be reloaded between 0x40 and WIN 6 0 15 5 3 Status register WWDT_STS Bit Register Reset value Type Description Bit 31 1 Reserve...

Page 282: ...reload the counter value to avoid the WDT reset WDT write protected The WDT_DIV and WDT_RLD registers are write protected Writing the value 0x5555 to the WDT_CMD register will unlock write protection...

Page 283: ...bits Min timeout ms RLD 11 0 0x000 Max timeout ms RLD 11 0 0xFFF 4 0 0 1 409 6 8 1 0 2 819 2 16 2 0 4 1638 4 32 3 0 8 3276 8 64 4 1 6 6553 6 128 5 3 2 13107 2 256 6 or 7 6 4 26214 4 16 4 Debug mode Wh...

Page 284: ...ndby mode Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 0 RLD 0xFFF rw Reload value The write protection must be unlocked in order to enabl...

Page 285: ...t calibration clock output alarm event or wakeup event Multiplexe function input reference clock input one channel tamper detection and time stamp Figure 17 1 ERTC block diagram PCLK1 1 2V power domai...

Page 286: ...TC registers the steps below should be respected 1 Enable power interface clock by setting PWCEN 1 in the CRM_APB1EN register 2 Unlock write protection of the battery powered domain by setting BPWEN 1...

Page 287: ...is performed every two ERTC_CLK The shadow register is reset by a system reset To ensure consistency between the 3 values ERTC_SBS ERTC_TIME and ERTC_DATE registers reading lower order registers will...

Page 288: ...ion modes Sleep Deepsleep and Standby modes 17 3 4 ERTC calibration Smooth digital calibration Smooth digital calibration has a higher and well distributed performance than the coarse digital calibrat...

Page 289: ...ion interrupt is enabled If the TPTSEN bit is already set a time stamp event will be generated accordingly Once a tamper event occurs the battery powered registers will be reset so as to ensure data s...

Page 290: ...1 Configure the EXINT line corresponding to ERTC interrupts as an interrupt mode and enable it and select a rising edge 2 Enable a NVIC channel corresponding to ERTC interrupts 3 Eanble an ERTC inter...

Page 291: ..._TAMP 0x40 0x0000 0000 ERTC_ALASBS 0x44 0x0000 0000 ERTC_BPRx 0x50 0x60 0x0000 0000 17 4 1 ERTC time register ERTC_TIME Bit Register Reset value Type Description Bit 31 23 Reserved 0x000 resd Kept at...

Page 292: ...ery powered domain is not affected by a system reset It is used to store the daylight saving time change or others that need to be saved permanently Bit 17 DEC1H 0x0 wo Decrease 1 hour 0 No effect 1 S...

Page 293: ...ld is supported when WATEN 0 and WATWF 1 17 4 4 ERTC initialization and status register ERTC_STS Bit Register Reset value Type Description Bit 31 17 Reserved 0x0000 resd Kept at its default value Bit...

Page 294: ...value located in the battery powered domain The synchronization is performed every two ERTC_CLK Bit 4 INITF 0x0 ro Calendar initialization flag 0 Calendar has not been initialized 1 Calendar has been...

Page 295: ...U 0x0 rw Hour units Bit 15 MASK2 0x0 rw Minute mask 0 No minute mask 1 Aarm clock doesn t care about minutes Bit 14 12 MT 0x0 rw Minute tens Bit 11 8 MU 0x0 rw Minute units Bit 7 MASK1 0x0 rw Second m...

Page 296: ...e ERTC_STS register It is cleared when TSF bit is reset 17 4 12ERTC time stamp date register ERTC_TSDT Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default valu...

Page 297: ...1 Tamper detection pull up disabled Bit 14 13 TPPR 0x0 rw Tamper detection pre charge time 0 1 ERTC_CLK cycle 1 2 ERTC_CLK cycles 2 4 ERTC_CLK cycles 3 8 ERTC_CLK cycles Bit 12 11 TPFLT 0x0 rw Tamper...

Page 298: ...mparison Alarm A doesn t care about subseconds 1 SBS 0 is compared 2 SBS 1 0 are compared 3 SBS 2 0 are compared 14 SBS 13 0 are compared 15 SBS 14 0 are compared Bit 23 15 Reserved 0x000 rw Kept at i...

Page 299: ...r to AT32F425 data sheet for more information ADC input range VREF VIN VREF In terms of digital control Regular channels and preempted channels with different priority Regular channels and preempted c...

Page 300: ...CCEIEN PCCEIEN VMORIEN Voltage monitor Preempted data register 4 16 bits Ordinary data register 16 bits EXINT15 Input pin description VDDA Analog supply ADC analog supply VSSA Analog supply ground ADC...

Page 301: ...hows the basic operation process of the ADC It is recommended to do the calibration after the initial power on in order to improve the accuracy of sampling and conversion After the calibration trigger...

Page 302: ...in the ADC_CTRL2 register or by an external event The external events include timer and pin triggers The OCTESEL and PCTESEL bits in the ADC_CTRL2 register are used to select specific trigger sources...

Page 303: ...C_IN5 ADC_IN0 ADC_IN5 OCLEN 2 OSN1 ADC_IN5 OSN2 ADC_IN0 OSN3 ADC_IN5 Ordinary channel trigger CCE flag set ADC_IN5 ADC_IN0 ADC_IN5 CCE flag set Ordinary channel trigger ADC_IN14 ADC_IN1 ADC_IN14 PCLEN...

Page 304: ...n the sub group Each trigger event selects different sub group in order Set the PCPEN bit in the ADC_CTRL1 register will enable the partition mode of the preempted group In this mode the preempted gro...

Page 305: ...0x1FFE 0x3FFC 0x7FF8 0xFFF0 0xFFE0 0xFFC0 Shift 3 digits 0x0400 0x0800 0x0FFF 0x1FFE 0x3FFC 0x7FF8 0xFFF0 0xFFE0 Shift 4 digits 0x0200 0x0400 0x0800 0x0FFF 0x1FFE 0x3FFC 0x7FF8 0xFFF0 Shift 5 digits 0...

Page 306: ...complete flag follows the conversion sequence management mode Figure 18 9 shows the behavior when the ordinary trigger mode works together with resume mode in 4x oversampling rate and sequential mode...

Page 307: ...7 DT 6 DT 5 DT 4 DT 3 DT 2 DT 1 DT 0 0 0 0 0 0 0 0 DT 11 DT 10 DT 9 DT 8 DT 7 DT 6 DT 5 DT 4 DT 3 DT 2 DT 1 DT 0 DT 11 DT 10 DT 9 DT 8 DT 7 DT 6 DT 5 DT 4 DT 3 DT 2 DT 1 DT 0 0 0 0 0 Preempted channe...

Page 308: ...value ADC_STS 0x000 0x0000 0000 ADC_CTRL1 0x004 0x0000 0000 ADC_CTRL2 0x008 0x0000 0000 ADC_SPT1 0x00C 0x0000 0000 ADC_SPT2 0x010 0x0000 0000 ADC_PCDTO1 0x014 0x0000 0000 ADC_PCDTO2 0x018 0x0000 0000...

Page 309: ...ry channels 0 Voltage monitoring disabled on ordinary channels 1 Voltage monitoring enabled on ordinary channels Bit 22 PCVMEN 0x0 rw Voltage monitoring enable on preempted channels 0 Voltage monitori...

Page 310: ...nnel 00001 ADC_IN1 channel 01111 ADC_IN15 channel 10000 ADC_IN16 channel 10001 ADC_IN17 channel 10010 11111 Unused configuration is not allowed 18 5 3 ADC control register2 ADC_CTRL2 Accessed by words...

Page 311: ...rred or initialization completed 1 Enable initialization or initializationis is ongoing Bit 2 ADCAL 0x0 rw A D Calibration 0 No calibration occurred or calibration completed 1 Enable calibration or ca...

Page 312: ...1 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 17 15 CSPT15 0x0 rw Sample time selection of channel ADC_IN15 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cyc...

Page 313: ...239 5 cycles 18 5 5 ADC sampling time register 2 ADC_SPT2 Accessed by words Bit Register Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 27 CSPT9 0x0 rw Sampl...

Page 314: ...0x0 rw Sample time selection of channel ADC_IN4 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 11 9 CSPT3 0x0 rw Sam...

Page 315: ...words Bit Register Reset value Type Description Bit 31 16 Reserved 0x00000 resd Kept at its default value Bit 15 0 VMHB 0xFFF rw Voltage monitoring high boundary 18 5 8 ADC voltage monitor low thresh...

Page 316: ...x00 rw Number of 6th conversion in ordinary sequence Bit 24 20 OSN5 0x00 rw Number of 5th conversion in ordinary sequence Bit 19 15 OSN4 0x00 rw Number of 4th conversion in ordinary sequence Bit 14 10...

Page 317: ...value Bit 15 0 PDTx 0x0000 rw Conversion data from preempted channel 18 5 14ADC ordinary data register ADC_ ODT Accessed by words Bit Register Reset value Type Description Bit 31 16 ADC2ODT 0x0000 ro...

Page 318: ...9 OOSTREN 0x0 rw Ordinary oversampling trigger mode enable 0 Disabled only one trigger is needed for all oversampling conversions 1 Enabled Each oversampling conversion needs a trigger Bit 8 5 OSSSEL...

Page 319: ...he identifier list mode Supports the identifier mask mode FIFO overrun management Time triggered communication mode 16 bit timers Time stamp on transmission 19 3 Baud rate The nominal bit time of the...

Page 320: ...s performed at the edge location of bit segment 1 and big segment 2 simulatenously During the actual transmission each bit of the CAN nodes has certain phase error due to the oscillator drift transmis...

Page 321: ...eld 2 7 EOF ACK RTR r0 IDE SOF Data frame or remote frame Error frame Inter frame space or overload frame Error flag Error echo Error delimiter 6 6 8 Data frame or remote frame Intermission Suspend tr...

Page 322: ...n RF0MN 00 RFF0MIEN 1 RF0FF 1 RF0FIEN 1 RF0OF 1 RF0OIEN 1 RX0_INT Figure 19 5 Receive interrupt 1 generation RF1MN 00 RFF1MIEN 1 RF1FF 1 RF1FIEN 1 RF1OF 1 RF1OIEN 1 RX1_INT Figure 19 6 Status error in...

Page 323: ...e processing time of message reception One FIFO scheme is used to ensure that the CPU can concentrate on application tasks for a long period of time without the loss of messages In the meantime the pr...

Page 324: ...for message reception and transmission Switch to Sleep mode The CAN controller switches to Sleep mode when the DZEN bit is set in the CAN_MCTRL register and the current CAN bus transmission is complet...

Page 325: ...programmed identifiers and which bits do not need In identifier list mode the identifier must match the pre programmed identifier The two modes can be used in conjunction with filter width to deliver...

Page 326: ...Mask CAN_F7FB1 31 16 ID 8 9 CAN_F9FB1 31 0 ID No 9 CAN_F7FB2 15 0 ID 9 CAN_F9FB2 31 0 ID 10 CAN_F7FB2 31 16 ID 10 10 CAN_F10FB1 15 0 ID Yes 11 8 CAN_F8FB1 31 0 ID Yes 11 CAN_F10FB1 31 16 Mask CAN_F8F...

Page 327: ...mailbox can be transmitted as soon as the CAN bus becomes idle The mailbox will enter EMPTY state at the end of the message transmission Figure 19 12 Transmit mailbox status EMPTY PENDING Send reques...

Page 328: ...ltering it is regarded as a valid message and is stored in the corresponding FIFO The number of the received messages RFxMN 1 0 will be incremented by one whenever the receive FIFO receives a valid me...

Page 329: ...off state in two ways when AEBOEN 0 in communication mode once 128 times of 11 consecutive recessive bits have been detected on the CAN RX the software request enters freeze mode and the bus off state...

Page 330: ...ts default value Bit 16 PTD 0x1 rw Prohibit trans when debug 0 Transmission works during debug 1 Transmission is prohibited during debug Receive FIFO can be still accessible normally Note Transmission...

Page 331: ...The message with the first request order is first transmitted Bit 1 DZEN 0x1 rw Doze mode enable 0 Sleep mode is disabled 1 Sleep mode is enabled Note The hardware will automatically leave sleep mode...

Page 332: ...hardware only when the corresponding bit is set in the CAN_ESTS register and the corresponding interrupt enable bit in the CAN_INTEN register is enabled When set this bit will generate a status change...

Page 333: ...t mailbox is free these two bits refer to the number of the next transmit mailbox free For example in case of free CAN the value of these two bit becomes 01 after a message transmit request is written...

Page 334: ...by hardware at the start of the next transmission Bit 10 TM1ALF 0x0 rw1c Transmit mailbox 1 arbitration lost flag 0 No arbitration lost 1 Transmit mailbox 1 arbitration lost Note This bit is set when...

Page 335: ...y hardware when a new transmission request is received Clearing this bit will clear the TSMF0 ALMF0 and TEMF0 bits of mailbox 0 19 7 1 4 CAN receive FIFO 0 register CAN_RF0 Bit Register Reset value Ty...

Page 336: ...1 full flag 0 Receive FIFO 1 is not full 1 Receive FIFO 1 is full Note This bit is set by hardware when three messages are pending in the FIFO 1 It is cleared by software by writing 1 Bit 2 Reserved 0...

Page 337: ...F bit are set Bit 5 RF1FIEN 0x0 rw Receive FIFO 1 full interrupt enable 0 Receive FIFO 1 full interrupt disabled 1 Receive FIFO 1 full interrupt enabled Note The flag bit of this interrupt is the RF1F...

Page 338: ...BOF 0x0 ro Bus off flag 0 Bus off state is not entered 1 Bus off state is entered Note When the TEC is greater than 255 the bus off state is entered and this bit is set by hardware Bit 1 EPF 0x0 ro Er...

Page 339: ...CAN_RDH0 CAN_RFI0 CAN_RDT0 CAN_RDL0 CAN_RDH0 CAN_RFI0 FIFO0 CAN_RFC0 CAN_RFDTL0 CAN_RFDTH0 CAN_RFI0 CAN_RDT0 CAN_RDL0 CAN_RDH0 CAN_RFI0 CAN_RDT0 CAN_RDL0 CAN_RDH0 CAN_RFI1 FIFO1 CAN_RFC1 CAN_RFDTL1 C...

Page 340: ...ilbox data byte 3 Bit 23 16 TMDT2 0xXX rw Transmit mailbox data byte 2 Bit 15 8 TMDT1 0xXX rw Transmit mailbox data byte 1 Bit 7 0 TMDT0 0xXX rw Transmit mailbox data byte 0 19 7 2 4 Transmit mailbox...

Page 341: ...t 7 0 RFDT0 0xXX ro Receive FIFO data byte 0 19 7 2 8 Receive FIFO mailbox data high register CAN_RFDTHx x 0 1 Note All the receive mailbox registers are read only Bit Register Reset value Type Descri...

Page 342: ...activation control register CAN_ FACFG Bit Register Reset value Type Description Bit 31 14 Reserved 0x00000 resd Kept at its default value Bit 13 0 FAENx 0x0000 rw Filter active enable Each bit corres...

Page 343: ...O SRAM USB2 0 FS USB 2 0 FS Serial Transceiver USB 2 0 I F GPIO 20 2 OTGFS functional description The OTGFS module consists of an OTGFS controller PHY and 1280 byte SRAM The OTGFS supports control tra...

Page 344: ...he OTGFS to perform USB bus sampling USBFS 48M clock has two sources HICK 48M When the HICK 48M clock is used as a USB control clock it is recommended to enable ACC feature Divided by PLL The PLL outp...

Page 345: ...Register OR AND Device All Endpoints Interrupt Register Interrupt source Core interruput register Note Because an interrupt mask only masks an interrupt software must clear an interrupt before unmaski...

Page 346: ...is written to the FIFO along with each received packet Therefore a minimum space of largest packet size 4 1 must be allocated to receirve data packets In most cases two largest packet size 4 1 spaces...

Page 347: ...ous endpints are enabled then at least two largest packet size 4 2 spaces must be allocated to receive back to back packets In most cases two largest packet size 4 2 spaces are recommended so that the...

Page 348: ...SH is cleared write the transmit FIFO number to be refreshed into the OTGFS_GRSTCTL TXFNUM register Set TXFFLSH 0x1 in the OTGFS_GRSTCTL register and wait until it is cleared Set the CGNPINNAK bit in...

Page 349: ...st Before disabling a channel the application must ensure that there is at least one free space available in the non periodic request queue when disabling a non perioid channel or the periodic request...

Page 350: ...mmed maximum packet size and transfer size Figure 20 3 Writing the transmit FIFO Wait for GAHBCFG NPTXFEMPLVL or GAHBCFG PTXFEMPLVL interrupt Read GNPTXSTS HPTXSIZ registers for available FIFO and que...

Page 351: ...a babble interrupt When the OTGFS controller detects a port babble it flushes the receive FIFO and disables the port Then the controller generates a Port disable interrupt Once receiving the interrupt...

Page 352: ...load 5 New HFIR Value 6 SOF back in Synchronization 400 450 The sequence of operation is as follows 1 After power on reset the current HFIR value set by the application is shown 2 The application load...

Page 353: ...ion Refer to channel 2 ch_2 for more information The assumptions are as follows The application is attempting to receive two largest packet size packets transfer size is 64 bytes The receive FIFO cont...

Page 354: ...is written to the receive FIFO 11 Read and ignore the receive packet status 12 The controller generates a CHHLTD interrupt as soon as the halt status is read from the receive FIFO 13 In response to t...

Page 355: ...e two packets 128 bytes for full speed transfer The non periodic request queue depth is 4 1 OUT SETUP operation process for common bulk and control transfer The sequence of operations shown in Figure...

Page 356: ...e that this queue can hold 4 entries De allocate ch_1 DATA1 MPS DATA1 write_tx_fifo ch_1 5 set_ch_en ch_2 set_ch_en ch_2 set_ch_en ch_2 read_rx_stsre ad_rx_fifo De allocate ch_2 11 13 1 MPS ch_1 ch_2...

Page 357: ...rrupt IN transfers Figure 20 8 shows the operation process of a typical interrupt IN transfer Refer to channel 2 ch_2 The assumptions are as follows The application is attempting to receive one larges...

Page 358: ...pt as soon as the receive packet is read 9 To handle the XFERC interrupt read the PKTCN bit in the OTGFS_HCTSIZ2 register If the PKTCNT bit in the OTGFS_HCTSIZ2 is not equal to 0 disable the channel b...

Page 359: ...g to send one largest packet size packet transfer size is 64 bytes to every frame The periodic transmit FIFO can store one packet 1KB bytes for full speed transfer The periodic request queue depth is...

Page 360: ...AHB Host USB Device DATA0 MPS DATA0 Periodic Request Queue Assume that this queue can hold 4 entries RXFLVL interrupt write_tx_fifo ch_1 init_reg ch_1 write_tx_fifo ch_1 init_reg ch_1 3 1 MPS 1 MPS D...

Page 361: ...acket 1031 bytes for full speed transfer The periodic request queue depth is 4 1 Common interrupt IN operation process The sequence of operations shown in Figure 21 9 channel 2 is as follows 1 Initial...

Page 362: ...IN transfers Unmask XACTERR XFERC FRMOVRUN BBLERR if XFERC or FRMOVRUN if XFERC and HCTSIZx PKTCNT 0 Reset Error Count De allocate Channel else Unmask CHHLTD Disable Channel else if XACTERR or BBLERR...

Page 363: ...n example of common synchronous OUT transfers Figure 20 9 Example of common synchronous OUT IN transfers set_ch_en ch_2 set_ch_en ch_2 read_rx_sts read_rx_fifo read_rx_sts init_reg ch_2 init_reg ch_2...

Page 364: ...dpoint initialization on enumeration completion At this time the device is ready to accept SOF packets and perform control transfers on control endpoint 0 20 5 4 2 Endpoint initialization on USB reset...

Page 365: ...plication to perform when the application receives a SetConfiguration SetInterface command in a SETUP packet When a SetConfiguration command is received the application must program the endpoint regis...

Page 366: ...et in the OTGFS_DOEPINTx register during the last OUT transfer it indicates the end of data OUT stage of control transfer 5 Once the completion of data OUT stage the application must perform the follo...

Page 367: ...the last SETUP packet received before the generation of the SETUP interrupt If the SETUP packet indicates two level control commands the application must perform the following steps Set OTGFS_DOEPCTLx...

Page 368: ...e to the RXFLVL bit in the OTGFS_GINTSTS register Reading an empty receive FIFO will result in unexpected behavior Figure 20 10 shows a flowchart Figure 20 10 Read receive FIFO Frame transfer complete...

Page 369: ...e is available space in the receive FIFO irrespective of the NAK and Stall bits on the control endpoints The controller sets the IN NAK and OUT NAK bits for the control IN OUT endpoints on which the S...

Page 370: ...f this condition occurs the OTGFS controller generates an interrupt B2BSTUP bit in the OTGFS_DOEPINTx register 20 5 4 13 IN data transfers This section describes the internal data flow during IN data...

Page 371: ...count 0x1 2 If an endpoint is enabled for data transfers the controller updates the Transfer size register At the end of the IN transfer indicated by endpoint disable interrupt bit the application mus...

Page 372: ...interrupt transfers Application requirements 1 For OUT data transfers the transfer size of the endpoint transfer register must be set to a multiple of the largest packet size for the endpoint and adj...

Page 373: ...de for an OUT endpoint is written to the receive FIFO one one of the following conditions The transfer size and packet count are both 0 The last OUT data packet written to the receive FIFO is a short...

Page 374: ...he OTGFS_GINTSTS register 4 Upon receiving the packet count of USB packets the controller internally sets the NAK bit for the endpoint to prevent it from receiving any more packets 5 The application p...

Page 375: ...its Endpoint enable 0x1 CNAK 0x1 Even Odd frame 0x0 Even 0x1 Odd 3 Wait for the RXFLVL interrupt in the OTGFS_GINTSTS register and read all the data packets from the receive FIFO See Read FIFO for mor...

Page 376: ...of the PKTCNT bit in the OTGFS_DIEPTSIZx register Program the OTGFS_DIEPCTLx register Read the OTGFS_DSTS register to determine the current frame number Program the OTGFS_DIEPCTLx with the maximum pa...

Page 377: ...modate the complete ISO OUT data packet the controller drops the received ISO OUT data When the synchronous OUT data packet is received with CRC errors When the synchronous OUT token received by the c...

Page 378: ...rom any synchronous IN endpoint because this can trigger the incomplete synchronous IN interrupt 2 The incomplete synchronous IN transfer interrupt in the OTGFS_GINTSTS register indicates that at leas...

Page 379: ...frame is not present in the FIFO the controller generates an INTKNTXFEMP interrupt A zero length data packet is transmitted on the USB for synchronous IN endpoints An NAK handshake signal is transmitt...

Page 380: ...ccess and host port control and status registers are active in both host and device modes When the OTGFS controller operates in either host or device mode the application must not access the register...

Page 381: ...regiser for power and clock control It is valid in both host and device modes 20 6 2 OTGFS register address map Table 20 4 shows the USB OTG register map and their reset values These peripheral regis...

Page 382: ...x510 0x0000 0000 OTGFS_HCCHAR1 0x520 0x0000 0000 OTGFS_HCINT1 0x528 0x0000 0000 OTGFS_HCINTMSK1 0x52C 0x0000 0000 OTGFS_HCTSIZ1 0x530 0x0000 0000 OTGFS_HCCHAR2 0x540 0x0000 0000 OTGFS_HCINT2 0x548 0x0...

Page 383: ...660 0x0000 0000 OTGFS_HCINT11 0x668 0x0000 0000 OTGFS_HCINTMSK11 0x66C 0x0000 0000 OTGFS_HCTSIZ11 0x670 0x0000 0000 OTGFS_HCCHAR12 0x680 0x0000 0000 OTGFS_HCINT12 0x688 0x0000 0000 OTGFS_HCINTMSK12 0x...

Page 384: ...0x0000 0080 OTGFS_DIEPTSIZ3 0x970 0x0000 0000 OTGFS_DTXFSTS3 0x978 0x0000 0200 OTGFS_DIEPCTL4 0x980 0x0000 0000 OTGFS_DIEPINT4 0x988 0x0000 0080 OTGFS_DIEPTSIZ4 0x990 0x0000 0000 OTGFS_DTXFSTS4 0x998...

Page 385: ...Bit Register Reset value Type Description Bit 31 22 Reserved 0x0000 resd Kept at its default value Bit 21 CURMOD 0x0 ro Current Mode of Operation Accesible in both host and device modes This bit indi...

Page 386: ...st mode and device modes Global interrupt mask The application uses this bit to mask or unmask the interrupts sent by the interrupt line to itself 0 Mask the interrupts sent to the application 1 Unmas...

Page 387: ...The application must program these bits based on the enumeration speed The number of bit times added per PHY clock is 0 25 bit times 20 6 3 5 OTGFS reset register OTGFS_GRSTCTL The application resets...

Page 388: ...ared after a few clock cycles by the controller Bit 1 PIUSFTRST 0x0 rw1s Accesible in both host mode and device modes PIU FS dedicated controller soft reset This bit is ued to reset PIU full speed ded...

Page 389: ...d only when a remote wakeup signal triggered by device is detected on the USB bus Bit 30 Reserved 0x0 resd Kept at its default value Bit 29 DISCONINT 0x0 rw1c Accesible in host mode only Disconnect de...

Page 390: ...t register to determine the exact source of the interrupt The application must clear the corresponding status bit in the corresponding Device OUT Endpoint n Interrupt register to clear this bit Bit 18...

Page 391: ...hake signal is sent out on the USB bus The STALL bit has priority over the NAK bit Bit 5 NPTXFEMP 0x1 ro Accesible in both host and device modes Non periodic TxFIFO empty This interrupt is generated w...

Page 392: ...pt Register to interrupt the application When an interrupt bit is masked the interrupt related to this interrupt bit is not generated However the Interrupt Register bit corresponding to this interrupt...

Page 393: ...modes Mode mismatch interrupt mask Bit 0 Reserved 0x0 resd Kept at its default value 20 6 3 8 OTGFS receive status debug read OTG status read and POP registers OTGFS_GRXSTSR OTGFS_GRXSTSP A read to th...

Page 394: ...O size register OTGFS_GRXFSIZ The application can program the SRAM size that must be allocated to the receive FIFO Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its...

Page 395: ...requests in host mode 00 Non periodic transmit request queue is full 01 1 location available 02 2 locations available N n locations available 0 n 8 Others Reserved Reset value Configurable Bit 15 0 NP...

Page 396: ...the depth and memory start address of the IN endpoint transmit FIFO in device mode Each of the FIFOs contains an IN endpoint data This register can be used repeatedly for instantiated IN endpoint FIF...

Page 397: ...application uses this filed to program the interval between two consecutive SOFs full speed The number of PHY locks in this field indicates the frame interval The application can write a value to the...

Page 398: ...of free space available to be written in the periodic transmit FIFO in terms of 32 bit words 0000 Periodic transmit FIFO is full 0001 1 space avaiable 0010 2 space avaiable N n space avaiable 0 n 512...

Page 399: ...to control power supply to this port by writing 1 or 0 0 Power off 1 Power on Note This bit is not associated with interfaces The application must follow the programming manual to set this bit for va...

Page 400: ...overcurrent 1 Overcurrent condition Bit 3 PRTENCHNG 0x0 rw1c Port enable disable change The controller sets this bit when the status of the port enable bit 2 in this register changes This bit can only...

Page 401: ...ates whether the transfer is in IN or OUT 0 OUT 1 IN Bit 14 11 EPTNUM 0x0 rw Endpoint number Indicates the endpoint number on the device serving as data source or receiver Bit 10 0 MPS 0x000 rw Maximu...

Page 402: ...nels described in the previous section Bit Register Reset value Type Description Bit 31 11 Reserved 0x000000 resd Kept at its default value Bit 10 DTGLERRMSK 0x0 rw Data toggle error mask Bit 9 FRMOVR...

Page 403: ...terval 10 90 of the frame interval 11 95 of the frame interval Bit 10 4 DEVADDR 0x00 rw Device address The application must program this field every time a SetAddress command is received Bit 3 Reserve...

Page 404: ...nous OUT packets Bit 2 GNPINNAKSTS 0x0 ro Global Non periodic IN NAK status 0 A handshake is sent based on the data status in the transmit FIFO 1 A NAK handshake is sent on all non periodic IN endpoin...

Page 405: ...after speed detection through a sequence 01 Reserved 10 Reserved 11 Full speed PHY clock is running at 48MHz Others Reserved Bit 0 SUSPSTS 0x0 ro Suspend status In device mode this bit is set as long...

Page 406: ...x0 resd Kept at its defaut value Bit 4 OUTTEPDMSK 0x0 rw OUT token received when endpoint disabled mask 0 Interrupt masked 1 Interrupt unmasked Bit 3 SETUPMSK 0x0 rw SETUP phase done mask Applies to c...

Page 407: ...empty interrupt mask bits These bits serve as mask bits for the device IN endpoint interrupt register A transmit FIFO empty interrupt bit per IN endpint Bit 0 for IN endpoint 0 bit 7 for IN endpoint 7...

Page 408: ...Kept at its default value Bit 1 0 MPS 0x0 rw Applies to IN and OUT endpoints The application uses this bit to program the maximum packet size for the current logical endpoint 00 64 bytes 01 32 bytes...

Page 409: ...ntrol non synchronous IN and OUT endpoints The application sets this bit to stall all tokens from the USB host to this endpoint If a NAK bit glocal non periodic IN NAK bit or global OUT NAK bit is set...

Page 410: ...The application uses this field to set the maximum packet size for the current logical endpoint The values are in bytes 20 6 5 11 OTGFS device control OUT endpoint 0 control register OTGFS_DOEPCTL0 Th...

Page 411: ...ntrol OUT endpoint 0 is the same as that of the control IN endpoint 0 00 64 bytes 01 32 bytes 10 16 bytes 11 8 bytes 20 6 5 12 OTGFS device control OUT endpoint x control register OTGFS_DOEPCTLx x x 1...

Page 412: ...OUT NAK bit is set along with this bit the STALL bit has priority Only the application can clear this bit but the controller never Bit 20 SNP 0x0 rw Snoop mode This bit configures the endpint to Snoo...

Page 413: ...point number This register indicates the status of an endpoint when USB and AHB related events occurs as shown in Figure 20 2 When the IEPINT bit of the OTGFS_GINTSTS register is set the application m...

Page 414: ...lies to control OUT endpoints only Indicates that an OUT token was received when the endpoint has not yet been enabled An interrupt is generated on the endpoint for which an OUT token was received Bit...

Page 415: ...e in bytes for the endpoint 0 The controller interrupts the application when the transfer size becomes 0 The transfer size can be set to the maximum packet size of the endpoint to be interrupted at th...

Page 416: ...s endpoint number The application must set this register before enabling endpoint x Once the endpoint x is enabled using the endpoint enable pin in the device endpoint x control register the controlle...

Page 417: ...alue Type Description Bit 31 5 Reserved 0x0000000 resd Kept at its default value Bit 4 SUSPENDM 0x0 ro PHY suspend Indicates that the PHY has been suspended Bit 3 1 Reserved 0x0 resd Kept at its defau...

Page 418: ...oarse calibration and fine calibration 21 3 Interrupt requests Table 21 1 ACC interrupt requests Interrupt event Event flag Enable bit Calibration ready CALRDY CALRDYIEN Reference signal lost RSLOST E...

Page 419: ...1 ms HICKCLK HICK clock The original HICK output frequency is 48MHz but the sampling clock used by the HICK calibration module is frequency divider 1 6 clock about 8MHz HICKCAL HICK module calibratio...

Page 420: ...e obtained by comparing the difference calculated as absolute value between the actual sampling value and C2 before and after crossing C2 so as to get the best calibration value HICKCAL or HICKTRIM If...

Page 421: ...OST is written with 0 Reference signal detection occurs only when CALON 1 Bit 0 CALRDY 0x0 ro Internal high speed clock calibration ready 0 Interal 8MHz oscillator calibration is not ready 1 Interal 8...

Page 422: ...ernal high speed auto clock trimming This field is read only but not written Internal high speed clock is adjusted by ACC module which is added to the ACC_HICKCAL 7 0 bit These bits allow the users to...

Page 423: ...n value closest to the theoretical value In theory the actual frequency after calibration can be trimmed to be within an accuracy of 0 5 steps from the targe frequency 8MHz 21 6 7 Compare value 3 ACC_...

Page 424: ...ects from TMR10_C1OUT USART1 and USART through the IR_SRC_SEL 1 0 bit in the SCFG_CFG1 register while the high frequency carrier signal is provided by the TMR11_C1OUT register The IR_POL bit in the SC...

Page 425: ...and HCLK There are several ID codes inside the MCU which is accessible by the debugger using the DEBUG_IDCODE at address 0xE0042000 It is part of the DEBUG and is mapped on the external PPB bus These...

Page 426: ...USE 0 rw TMR13 debug control bit 0 TMR13 runs normally 1 TMR13 stops running Bit 25 Reserved 0x0 resd Always 0 Bit 24 TMR17_PAUSE 0 rw TMR17 debug control bit 0 TMR17 runs normally 1 TMR17 stops runni...

Page 427: ...s not unpowered in Standby mode and the system clock is provided by the internal RC oscillator HICK Bit 1 DEEPSLEEP_DEBUG 0 rw Debug Deepsleep mode control bit 0 In Deepsleep mode all clcoks in the 1...

Page 428: ...25 Series Reference Manual 2022 03 30 Page 428 Ver 2 01 24 Revision history Document Revision History Date Version Revision Note 2022 01 12 2 00 Initial release 2022 03 30 2 01 Added contents and book...

Page 429: ...ng legal situation in any injudical districts or infringement of any patent copyright or other intellectual property right ARTERY s products are not designed for the following purposes and thus not in...

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