ARTERY AT32F425 Series, Reference Manual

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AT32F425 Series Reference Manual
2022.03.30 Page 258 Ver 2.01
Figure 14-85
Counter timing diagram with internal clock divided by 1 and TMRx_PR=0x32
0 1 2 3
...
31 32 31 30 2F 2E
...
2 1 0 1 2 3 COUNTER 31 32 31 30
...
PR[15:0]
OVFIF
TMR_CLK
0 DIV[15:0]
32
Clear Clear Clear
11
TWCMSEL
[1
：
0]
Repetition counter mode:
The repletion counter mode is enabled when the repetition counter value is not equal to 0. In this mode,
the repetition counter is decremented at each counter overflow. An overflow event is generated when
the repetition counter reaches 0. The frequency of the overflow event can be adjusted by setting the
repettion counter value.
Figure 14-86
OVFIF when RPR=2
0 1 2 3 ... 31 32 0 1 2 3
...
31 32 0 1 2 3 COUNTER 31 32 0 1
32
...
PR[15:0]
2 1 0 RPR[7:0]
OVFIF
Encoder interface mode
To enble the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two
inputs (C1IN/C2IN) are required. Depending on the level on one input, the counter counts up or down
on the edge of the other input. The OWCDIR bit indicates the direction of the counter, as shown in the
table below:
Table 14-15 Couting direction versus encoder signals
Active edge
Level on opposite signal
(C1INFP1 to C2IN, C2INFP2
to C1IN)
C1INFP1 signal C2INFP2 signal
Rising Falling Rising Falling
Count on C1IN only
High Down Up No count No count
Low Up Down No count No count
Count on C2IN only
High No count No count Up Down
Low No count No count Down Up
Count on both C1IN and
C2IN
High Down Up Up Down
Low Up Down Down Up
Figure 14-87 Example of encoder interface mode C
20
21 22 23 24 25 26 27 26 25 24
23
22 21 20 1F COUNTER
0x3
TWCMSEL
[1:0]
CI1RAW
CI2RAW
UP DOWN