AT32F425
Series Reference Manual
2022.03.30
Page 125
Ver 2.01
11.4.4 I
2
C slave communication flow
1.
I
2
C
clock initialization (by setting the I2C_CLKCTRL register)
―
I
2
C
clock divider: DIV[7: 0]
―
Data hold time (t
H D ; D A T
):
SDAD[3: 0]
―
Data setup time (t
S U ; D AT
)
: SCLD[3: 0]
This register can be configured by means of Artery_I2C_Timing_Configuration tool.
2.
Set local address 1
―
Set address mode:
7-bit address: by setting ADDR1MODE = 0 in the I2C_OADDR register
10-bit address: by setting ADDR1MODE = 1 in the I2C_OADDR register
―
Set address 1: by setting the ADDR1 bit in the I2C_OADDR1 register
―
Enable address 1: by setting ADDR1EN=1 in the I2C_OADDR1 register
3.
Set local address 2
―
Set address 2: by setting the ADDR2 bit in the I2C_OADDR2 register
―
Set address 2 mask bit: by setting the ADDR2MASK bit in the I2C_OADDR2 register
―
Enable address 2: by setting ADDR2EN=1 in the I2C_OADDR2 register
Note: Only 7-bit address mode is available in the address 2 mode. The ADDR2MASK bit is used
to mask some address bits freely so that the slave can respond to some specific addresses. Refer
to Section 14.2 for more information about the ADDR2MASK bit.
In the case of using only one address, only address 1 needs to be configured, without the need of
address 2 mode.
4.
Wait for address matching
When the local address is received, the ADDRF bit is set in the I2C_STS register. The data transfer
direction can be obtained by read access to the SDIR bit in the I2C_STS register. When SDIR=0,
it indicates that the slave is receiving data, where as SDIR=1 indicates that the slave is sending
data. The ADDR[6:0 bit of the I2C_STS register indicates what kind of address has been received,
which is particularly helpful in the case when the dual address mode is used and the address 2
mode mask bit is set.
Data transfer starts when the ADDRF is cleared by setting ADDRC=1 of the I2C_CLR register.
5.
Data transfer (slave transmission, clock stretching enabled, STRETCH=0)
After address matching:
1.
I2C_TXDT data register becomes empty, the shift register becomes empty, and TDIS=1 in the
I2C_STS register
2.
Data is then transferred to the shift register after writing 1 to the TXDT register
3.
The TXDT register then becomes empty, and the TDIS is set again
4.
TDIS is cleared by writing 2 to the TXDT register
5.
Repeat step 3 and 4 until the completion of data transfer
6.
Wait for the generation of an NACK signal. Once received, the ACKFAILF is set in the I2C_STS
register. The ACKFAILF flag is cleared by writing 1 to the ACKFAILC
7.
Wait for the generation of a STOP condition. Once received, the STOPF is set in the I2C_STS
register. At the end of data transfer, the STOPF is cleared by writing 1 to the STOPC,
transmission ends.
In the case of the clock stretching being disabled (STRETCH=1), if data has not yet been written to
the TXDT register before the transmission of the first bit of the to-be-transferred data (that is, before
the generation of SDA edge), an underrun error may occur, and the OUF bit is set in the I2C_STS
register, sending 0xFF to the bus.
In order to write data in time, data must be written to the DT register first before communication, in
two different ways:
―
Write operation through software: Clear the TXDT register by setting the TDBE bit through
