AT32F421
Series Reference Manual
2022.11.11
Page 98
Rev 2.02
9
DMA controller (DMA)
9.1 Introduction
Direct memory access (DMA) controller is designed for 32-bit MCU applications with the aim of
enhancing system performance and reducing the generation of interrupts.
The DMA controller contains 5 DMA channels. Each channel manages memory access requests from
one or more peripherals. An arbiter is available for coordinating the priority of each DMA request.
9.2 Main features
AMBA compliant (Rev. 2.0)
Only support AHB OKAY and ERROR responses
HBUSREQ and HGRANT of AHB master interface are not supported
Support 5 channels
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfers
Support hardware handshake
Support 8-bit, 16-bit and 32- bit data transfers
Programmable amount of data to be transferred: up to 65535
Figure 9-1
DMA block diagram
Note: The number of DMA peripherals in Figure 9-1 may decrease depending on different models.
9.3 Functional overview
9.3.1
DMA configuration
1.
Set the peripheral address in the DMA_CxPADDR register
The initial peripheral address for data transfer remains unchanged during transmission.
2.
Set the memory address in the DMA_CxMADDR register
The initial memory address for data transfer remains unchanged during transmission.
3.
Configure the amount of data to be transferred in the DMA_CxDTCNT register
Programmable data transfer size is up to 65535. This value is decremented after each data transfer.
4.
Configure the channel setting in the DMA_CxCTRL register
Including channel priority, data transfer direction/width, address incremented mode, circular mode
and interrupt mode
Channel priority (CHPL)
There are four levels, including very high priority, high priority, medium priority and low priority.
DMA1
Arbiter
ch2
ch3
ch5
ch1
AHB
Slave
AHB
Master
...
ADC
I2C1
I2C2
SPI1
SPI2
TMR1
TMR3
TMR15
TMR16
TMR17
USART1
USART2
DMA request
DMA ack