AT32F421
Series Reference Manual
2022.11.11
Page 263
Rev 2.02
Encoder interface mode
To enable the encoder interface mode, write SMSEL[2: 0]= 3’b001/3’b010/3’b011. In this mode, the two
inputs (C1IN/C2IN) are required. Depending on the level on one input, the counter counts up or down
on the edge of the other input. The OWCDIR bit indicates the direction of the counter.
Figure 14-105 Encoder mode structure
encoder mode
C2P
C2IFP2
C1DF
TMRx_CH3
XOR
TMRx_CH1
TMRx_CH2
C2IRAW
C2DF
C1P
C1IFP1
CNT
director
SMSEL=3'b001/010/011
C1INSEL
C1IRAW
filter
filter
polarity select
polarity select
edge
detector
OR
encoder
mode A
encoder
mode B
encoder
mode C
SMSEL
001
010
011
DIV_CLK
TMRx_DIV
CNT
counter
DIV counter
RPR
counter
preload
TMRx_RPR
preload
Overflow event
pos/neg edge
Encoder mode A: SMSEL=3’b001. The counter counts on C1IFP1 (rising edge and falling edge), and
the counting direction is dependent on the edge direction of C1IFP1 and the level of C2IFP2.
Encoder mode B: SMSEL=3’b010, the counter counts on C2IFP2 (rising edge and falling edge), and the
counting direction is dependent on the edge direction of C2IFP2 and the level of C1IFP1.
Encoder mode C: SMSEL=3’b011, the counter counts on C1IFP1 and C2IFP2 (rising edge and falling
edge), and the counting direction is dependent on the C1IFP1 edge direction + C2IFP2 level, and
C2IFP2 edge dir C1IFP1 level.
To use the encoder mode, follow the configuration steps as below:
–
Set the C1DF[3:0] bit in the TMRx_CM1 register to set channel 1 input signal filtering; set the C1P
bit in the TMRx_CCTRL register to set channel 1 input signal active level.
–
Set the C2DF[3:0] bit in the TMRx_CM1 register to set channel 2 input signal filtering; set the C2P
bit in the TMRx_CCTRL register to set channel 2 input signal active signal.
–
Set the C1C[1:0] bit in the TMRx_CM1 register to set channel 1 as input mode; set the C2C[1:0] bit
in the TMRx_CM1 register to set channel 2 as input mode.
–
Set the SMSEL[2:0] bit in the TMRx_STCTRL register to select encoder mode A
(SMSEL=3’b001),
encoder mode B (
SMSEL=3’b010) or encoder mode C (SMSEL=3’b011).
–
Set the PR[15:0] bit in the TMRx_PR register to set the counting period.
–
Set the DIV[15:0] bit in the TMRx_DIV register to set the counting frequency.
–
Set the IOs corresponding to TMRx_CH1 and TMRx_CH2 as multiplexed mode.
–
Set the TMREN bit in the TMRx_CTRL1 register to enable the counter.
Table 14-15 Counting direction versus encoder signals
Active edge
Level on opposite signal
(C1INFP1 to C2IN, C2INFP2
to C1IN)
C1INFP1 signal
C2INFP2 signal
Rising
Falling
Rising
Falling
Count on C1IN only
High
Down
Up
No count
No count
Low
Up
Down
No count
No count
Count on C2IN only
High
No count
No count
Up
Down
Low
No count
No count
Down
Up