AT32F421
Series Reference Manual
2022.11.11
Page 109
Rev 2.02
11
I
2
C interface
11.1 I
2
C introduction
I
2
C (inter-integrated circuit) bus interface manages the communication between the microcontroller and
serial I
2
C bus. It supports master and slave modes, with up to 400 Kbit/s of communication speed.
11.2 I
2
C main features
I
2
C bus
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Master and slave modes
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Multimaster capability
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Stand speed (100 kHz), fast speed (400 kHz)
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7-bit and 10-bit address modes
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Broadcast call mode
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Status flag
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Error flag
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Clock stretching capability
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Communication event interrupts
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Error interrupts
Support DMA transfer
Support SMBus2.protocol
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PEC generation and verification
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SMBus reminder capability
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ARP(address resolution protocol)
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Timeout detection
PMBus
11.3 I
2
C functional overview
I
2
C bus consists of a data line (SDA) and clock line (SCL). It can achieve a maximum of 100 kHz speed
in standard mode, whereas up to 400kHz in fast mode. A frame of data transfer begins with a Start
condition and ends with a Stop condition. The bus is kept in busy state after receiving a Start condition,
and becomes idle as long as it receives a Stop condition.
Start condition: SDA switches from high to low when SCL is set high.
Stop condition: SDA switches from low to high when SCL is set high.
Figure 11-1 I
2
C bus protocol
SDA
SCL
Start condition
Stop condition
8
9
2
1
MSB
ACK
3 to 7