AT32F413
Series Reference Manual
2022.06.27
Page 226
Rev 2.00
Figure 14-45
Control circuit with CK_INT divided by 1
CK_INT
TMREN
COUNTER
12
11
13
14
15
16
00
01
02
03
04
05
06
07
External clock
(
TRGIN/EXT
)
The counter clock can be provided by two external clock sources, namely, TRGIN and EXT signals.
When SMSEL=3’111, external clock mode A is selected. Set the STIS[2: 0] bit to select TRGIN signal to
drive the counter to start counting.
When ECMBEN=1, external clock mode B is selected. The counter starts counting driven by EXT signal.
Figure 14-46
Block diagram of external clock mode A
EXT
C1IFP2
C1IFP1
C1INC
ISx
CK_DIV
Trigger select
Slave mode
control
External clock
control
CI1RAW
Filter
Edge
detector
C2IF_Rising
C2IF_Falling
Polarity
selection
Note: The delay between the signal on the input side and the actual clock of the counter is due to the
synchronization circuit.
Figure 14-47
Counting in external clock mode A
30
COUNTER
OVFIF
TMR_CLK
110
STIS[2:0]
Clear
CNT_CLK
C2IRAW
000
C2IF[2:0]
31
32
0
1
2
3
4
Figure 14-48
Block diagram of external clock m ode B
CK_DIV
Slave mode
control
External clock
control
EXT
Divider
Filterr
Downcounter
Polarity
selection
Note: The delay between the ext signal on the input side and the actual clock of the counter is due to
the synchronization circuit.