AT32F413
Series Reference Manual
2022.06.27
Page 193
Rev 2.00
Configure the slave timer trigger input signal TRGIN as master timer output (STIS[2: 0] in the
TMRx_STCTRL register)
Configure the slave timer to use external clock mode A (SMSEL[2: 0]=3’b111 in the
TMRx_STCTRL register )
Set TMREN =1 in both master timer and slave timer to enable them
Using master timer to start slave timer:
Configure master timer output signal TRGOUT as an overflow event (PTOS[2: 0]=3’b010). The
master timer outputs a pulse signal at each counter overflow event, which is used as the
counting clock of the slave timer.
Configure master timer counting period (TMRx_PR registers)
Configure slave timer trigger input signal TRGIN as master timer input
Configure slave timer as trigger mode (SMSEL=3’b110 in the TMR2_STCTRL register)
Set TMREN=1 to enable master timer.
Figure 14-25
Using master timer to start slave timer
0
1
2
3
...
31
32
0
1
...
31
32
0
1
2
3
...
31
COUNTER
0
1
2
3
32
PR[15:0]
TMREN
TMR_CLK
0
DIV[15:0]
32
22
PR[15:0]
Overflow
event
1
...
21
22
0
1
2
3
...
21
COUNTER
0
1
2
3
22
0
0
DIV[15:0]
TMR_CLK
Master
TMR
Slave
TMR
Starting master and slave timers synchronously by an external trigger:
In this example, configure the master timer as master/slave mode synchronously and enable its slave
timer synchronization function. This mode is used for synchronization between master timer and slave
timer.
Set the STS bit of the master timer.
Configure master timer output signal TRGOUT as an overflow event (PTOS[2: 0]=3’b010). The
master timer outputs a pulse signal at each counter overflow event, which is used as the
counting clock of the slave timer.
Configure the slave timer mode of the master timer as trigger mode, and select C1IN as trigger
source
Configure slave timer trigger input signal TRGIN as master timer output
Configure slave timer as trigger mode (SMSEL=3’b110 in the TMR2_STCTRL register)