AT32F413
Series Reference Manual
2022.06.27
Page 136
Rev 2.00
11.5.2 Control register2 (I2C_CTRL2)
Bit
Register
Reset value
Type
Description
Bit 15: 13 Reserved
0x0
resd
Forced to be 0 by hardware.
Bit 12
DMAEND
0x0
rw
End of DMA transfer
0: The next DMA transfer is no the last one.
1: The next DMA transfer is the last one.
Bit 11
DMAEN
0x0
rw
DMA transfer enable
0: Disabled
1: Enabled
Bit 10
DATAIEN
0x0
rw
Data transfer interrupt enable
An interrupt is generated when TDBE =1 or RDBF=1.
0: Disabled
1: Enabled
Bit 9
EVTIEN
0x0
rw
Event interrupt enable
0: Disabled
1: Enabled
An interrupt is generated in the following conditions:
– STARTF = 1 (Master mode)
– ADDR7F = 1 (Master/slave mode)
– ADDRHF= 1 (Master mode)
– STOPF = 1 (Slave mode)
– TDC = 1, but no TDBE or RDBF event
– If DATAIEN = 1, the TDBE event is 1.
– If DATAIEN = 1, the RDBF event is 1.
Bit 8
ERRIEN
0x0
rw
Error interrupt enable
0: Disabled
1: Enabled
An interrupt is generated in the following conditions:
– BUSERR = 1
– ARLOST = 1
– ACKFAIL = 1
– OVER = 1
– PECERR = 1
– TMOUT = 1
– ALERTF = 1
Bit 7: 0
CLKFREQ
0x00
rw
I
2
C input clock frequency
Correct input clock frequency must be set to generate
correct timings. The range allowed is between 2 MHz and
120 MHz.
2: 2MHz
3: 3MHz
……
120: 120MHz
11.5.3 Own address register1 (I2C_OADDR1)
Bit
Register
Reset value
Type
Description
Bit 15
ADDR1MODE
0x0
rw
Address mode
0: 7-bit address
1: 10-bit address
Bit 14: 10 Reserved
0x00
resd
Kept at its default value.
Bit 9: 0
ADDR1
0x000
rw
Own address1
In 7-bit address mode, bit 0 and bit [9
：
8] don’t care.